Alan Mishchenko 24083998ab Deriving cell mapping with &if -kz.

2014-10-04 19:18:34 -07:00

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abc

Renaming DSD commands (dsd_tune -> dsd_match; dsd_clean -> dsd_filter).

2014-09-28 11:32:26 -07:00

abci

Deriving cell mapping with &if -kz.

2014-10-04 19:18:34 -07:00

cmd

Deriving AIG after cell mapping.

2014-10-03 17:15:43 -07:00

io

Deriving AIG after cell mapping.

2014-10-03 17:15:43 -07:00

main

Replacing tabs with spaces.

2014-09-12 13:46:11 -07:00

test

Updating project settings to have simpler include paths.

2012-07-07 20:14:12 -07:00

ver

Synchronizing packages.

2014-09-20 17:01:47 -07:00

wlc

Bug fix in Verilog writer.

2014-10-02 14:53:30 -07:00