abc/src/map/scl
Martin Povišer 208b48667f Merge branch 'master' of https://github.com/berkeley-abc/abc into yosys-experimental 2024-04-22 16:33:29 +02:00
..
module.make Infrastructure to support full Liberty format and unitification of library representations. 2013-09-15 18:23:49 -07:00
scl.c Added switch -p in "read_lib" to skip writing cell prefix. 2024-04-14 09:51:00 -07:00
scl.h New package to read/write a subset of Liberty for STA. 2012-08-29 16:20:39 -07:00
sclBufSize.c Changing declaration of Vec_Ptr_t sorting function to satisfy some compilers. 2021-09-26 11:30:54 -07:00
sclBuffer.c Changing declaration of Vec_Ptr_t sorting function to satisfy some compilers. 2021-09-26 11:30:54 -07:00
sclCon.h stringizing macro argument 2017-03-03 12:03:55 +01:00
sclDnsize.c Adding callback for wire caps during sizing. 2023-11-06 17:35:41 -08:00
sclLib.h Added switch -p in "read_lib" to skip writing cell prefix. 2024-04-14 09:51:00 -07:00
sclLibScl.c ensure initial library writing also honors prefix 2024-04-16 08:58:28 -04:00
sclLibUtil.c Compiler warnings. 2023-02-28 15:40:06 +07:00
sclLiberty.c Merge branch 'master' of https://github.com/berkeley-abc/abc into yosys-experimental 2024-04-22 16:33:29 +02:00
sclLoad.c Improvements to Scl_Lib/SC_Cell data-structure. 2015-09-24 12:12:36 -07:00
sclSize.c Adding callback for wire caps during sizing. 2023-11-06 17:35:41 -08:00
sclSize.h Adding callback for wire caps during sizing. 2023-11-06 17:35:41 -08:00
sclTime.h Normalization of slew/load values. 2013-10-13 20:55:24 -07:00
sclUpsize.c Adding callback for wire caps during sizing. 2023-11-06 17:35:41 -08:00
sclUtil.c Fix typo on the message reporting max output load. 2017-10-11 18:14:03 +07:00