mirror of https://github.com/YosysHQ/abc.git
29 lines
427 B
Verilog
29 lines
427 B
Verilog
module fsm (out);
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output out;
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wire [2:0] ns;
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wire [2:0] cs;
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always @( ns or cs )
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begin
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case (cs)
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0 : ns = 3'b010;
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1 : ns = 3'b001;
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2 : ns = 3'b000;
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3 : ns = 3'b101;
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4 : ns = 3'b001;
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5 : ns = 3'b111;
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6 : ns = 3'b001;
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7 : ns = 3'b110;
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endcase
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end
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assign out = cs == 3'b001;
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wire [2:0] const0 = 3'h0;
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CPL_FF#3 ff3 ( .q(cs), .qbar(), .d(ns), .clk(), .arst(), .arstval(const0) );
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endmodule
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