Logo
Explore Help
Sign In
luke/abc
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/abc.git synced 2026-09-05 00:51:01 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
1116313d28d4e7665459bb90cca210bc86c7ffe5
abc/src/opt
T
History
Alan Mishchenko 1116313d28 Improved DSD.
2012-11-11 14:38:24 -08:00
..
cgt
Updating project settings to have simpler include paths.
2012-07-07 20:14:12 -07:00
csw
Updating project settings to have simpler include paths.
2012-07-07 20:14:12 -07:00
cut
Replacing 'st_table' by 'st__table' to resolve linker problems.
2012-09-29 17:11:03 -04:00
dar
Bug fix in XOR balancing (command 'balance -x').
2012-10-05 15:02:26 -07:00
dau
Improved DSD.
2012-11-11 14:38:24 -08:00
fsim
Replacing Mb/Gb to be MB/GB.
2012-07-09 22:57:03 -07:00
fxu
Added an API to convert a multi-output PLA into a shared AIG.
2012-08-29 12:43:55 -07:00
lpk
Updating project settings to have simpler include paths.
2012-07-07 20:14:12 -07:00
mfs
Enabled recording the name of the file GIA is coming from.
2012-09-04 13:52:42 -07:00
nwk
Integrating GIA with LUT mapping.
2012-10-24 17:39:38 -07:00
res
Updating project settings to have simpler include paths.
2012-07-07 20:14:12 -07:00
ret
Replacing 'st_table' by 'st__table' to resolve linker problems.
2012-09-29 17:11:03 -04:00
rwr
Replacing 'st_table' by 'st__table' to resolve linker problems.
2012-09-29 17:11:03 -04:00
rwt
Updating project settings to have simpler include paths.
2012-07-07 20:14:12 -07:00
sim
Updating project settings to have simpler include paths.
2012-07-07 20:14:12 -07:00
Powered by Gitea Version: 1.27.2 Page: 1391ms Template: 4ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API