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2348 Commits

Author SHA1 Message Date
Alan Mishchenko f23ea8e33f Updates to NDR format (flops, memories, signed mult, etc). 2018-04-29 15:14:01 -07:00
Alan Mishchenko 89c981c6ee The ECO code (fix to the broken build). 2018-04-28 18:58:23 -07:00
Alan Mishchenko fa00219d4c Adding switch &w -p to dump AIG in a Verilog file. 2018-04-25 16:58:29 -07:00
Alan Mishchenko f093aef867 The ECO code. 2018-04-25 13:19:41 -07:00
Alan Mishchenko cce9ff2113 The ECO code. 2018-04-25 13:01:36 -07:00
Alan Mishchenko 5d1abad84d Typo in the command description. 2018-04-25 11:59:34 -07:00
Alan Mishchenko 0e15e4dd15 Memory abstraction. 2018-04-20 16:06:13 -07:00
Alan Mishchenko 1c6655578c Memory abstraction. 2018-04-19 17:05:04 -07:00
Alan Mishchenko 098103012d Memory abstraction. 2018-04-15 21:23:22 -07:00
Alan Mishchenko a2d59be3f7 Integrating SAT-based CEX minimization (bug fix). 2018-03-25 18:19:06 -07:00
Alan Mishchenko e639e8fd1b Integrating SAT-based CEX minimization. 2018-03-25 16:46:09 -07:00
Alan Mishchenko 9ff7134f24 Adding new NPN code developed by XueGong Zhou at Fudan University. 2018-03-25 11:28:56 -07:00
Alan Mishchenko 53e7d1f9ef Adding switch 'scorr -f' to dump inductive invariant as an AIG. 2018-03-22 10:10:09 -07:00
Alan Mishchenko 69416b7ca1 Temporary bug fix for signal names in WLC (correction). 2018-03-21 20:52:36 -07:00
Alan Mishchenko d410faf85c Temporary bug fix for signal names in WLC. 2018-03-21 20:18:17 -07:00
Alan Mishchenko 3d16d44cff Bug fix in blasting with boxes. 2018-03-06 23:21:49 -08:00
Alan Mishchenko 48e128aa72 Extending primitives supported by WLC. 2018-03-03 17:57:30 -08:00
Alan Mishchenko f6b9cc013d Adding parameters and improvements to %blast. 2018-02-28 19:38:55 -08:00
Alan Mishchenko 7e9f3f027b Adding parameters and improvements to %blast. 2018-02-28 18:45:44 -08:00
Alan Mishchenko 33971604cf Adding support for adders with carry-in in WLC and NDR. 2018-02-24 09:50:24 -08:00
Alan Mishchenko fe56e29d44 Bug fix in NDR handling. 2018-02-20 16:56:52 -08:00
Alan Mishchenko 76b00a2d3e Compilation problem with pow(). 2018-02-19 09:07:44 -08:00
Alan Mishchenko fd390aae9d Extending MiniLUT to return attributes. 2018-02-11 17:14:07 -08:00
Alan Mishchenko f716948c27 Experiments with LUT mapping. 2018-02-10 15:45:54 -08:00
Alan Mishchenko c6bce9c20e Fixing input swapping issue in MUXes derived from NDR. 2018-02-07 09:02:28 -08:00
Alan Mishchenko 28602ccf2c Improvements to NDR to represent hierarchical designs. 2018-02-05 00:39:10 -08:00
Alan Mishchenko 3202c2581e Improvements to NDR to represent hierarchical designs. 2018-02-05 00:37:39 -08:00
Alan Mishchenko 30a06d002a Adding support of reading and writing designs using a new internal format (bug fix). 2018-01-29 17:01:01 -08:00
Alan Mishchenko 99ddb64095 Adding support of reading and writing designs using a new internal format. 2018-01-28 18:53:20 -08:00
Alan Mishchenko 5158acb113 Experiments with circuit-based SAT. 2018-01-27 13:05:37 -08:00
Alan Mishchenko e4cd0d60f1 Experiments with SAT-based simulation. 2018-01-25 00:09:27 -08:00
Alan Mishchenko 6274498e01 Updates to exact synthesis commands. 2018-01-19 14:03:24 -08:00
Alan Mishchenko 834e248019 New command 'testexact'. 2018-01-04 22:33:29 -08:00
Alan Mishchenko f3dcf87cea New exact synthesis command 'allexact'. 2017-12-30 16:13:52 -08:00
Alan Mishchenko 7d7ce3ecd0 New exact synthesis command 'allexact'. 2017-12-28 23:04:24 -08:00
Alan Mishchenko 680af1891b Bug fix in 'write_aiger_cex'. 2017-12-20 15:41:39 -08:00
Alan Mishchenko c7b65a15d3 Adding parameter structure to 'twoexact' and 'lutexact'. 2017-12-06 15:09:11 -08:00
Alan Mishchenko e37bbba72d An improvement to 'twoexact' and 'lutexact'. 2017-12-06 13:00:08 -08:00
Alan Mishchenko 67181d0446 An improvement to 'twoexact' and 'lutexact'. 2017-12-06 11:18:43 -08:00
Alan Mishchenko c4322a0afd Switch -a to use only AND-gates in 'twoexact' and 'lutexact'. 2017-12-06 10:31:21 -08:00
Alan Mishchenko 3f35ac8180 New command 'lutexact'. 2017-12-05 18:22:27 -08:00
Alan Mishchenko 1743979b75 Adding switch -a to 'write_verilog' to write factored forms without XORs and MUXes. 2017-12-03 14:39:11 -08:00
Alan Mishchenko a49dfbcf91 Portability changes for gcc-6 suggested by Clifford. 2017-12-03 08:08:36 -08:00
Alan Mishchenko 46175d0429 Portability changes for gcc-6 suggested by Clifford. 2017-12-02 19:47:24 -08:00
Alan Mishchenko 3cc4080c55 Portability changes for gcc-6 suggested by Clifford. 2017-12-02 19:44:08 -08:00
Baruch Sterin 7bcfe64369 C++ comaptibility: add namespace support to Glucose 2017-11-23 23:32:44 -08:00
Baruch Sterin 77ca1b7470 C++ compatibility: fix bad pointer comparison 2017-11-23 23:32:42 -08:00
Alan Mishchenko d85bc1dd68 Changes to make GIA structural hashing use a dedicated array instead of pObj->Value. 2017-11-13 18:50:04 -08:00
Alan Mishchenko 716969190a Profiling quantification and other changes. 2017-11-06 16:43:32 -08:00
Alan Mishchenko accf4825e5 Adding API to dump MiniAIG into a Verilog file and other small changes. 2017-10-22 15:44:13 -07:00