Carmine50
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cbd4456805
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[CEC][SimGen][Experiment ID] Added experiment ID option to test different experiments with simgen
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2024-12-18 19:53:44 +01:00 |
Carmine50
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070ae52a46
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[CEC][SimGen][Custom Parameters] Added custom parameters for SimGen CEC algo
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2024-12-18 19:36:50 +01:00 |
Carmine50
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99648e132f
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[CEC][SimGen][CLI] Added command line function to call SimGen main function.
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2024-12-18 18:43:38 +01:00 |
Alan Mishchenko
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8ba3d9b91c
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Trying anothe resource limit in scorr.
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2024-12-14 13:44:18 -08:00 |
Alan Mishchenko
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6754da13f2
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Compiler warning.
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2024-12-08 00:19:54 -08:00 |
Ethan Mahintorabi
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01c9a65a47
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map: Add Mio_Library_t* parameter to Abc_NtkMap
This lets users of the ABC API call map without relying on the static
Mio_Library_t* in Abc_FrameReadLibGen.
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2024-12-02 06:55:42 +00:00 |
Alan Mishchenko
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14168eb509
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Updating command "rungen" to generate random functions.
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2024-11-27 22:01:27 -08:00 |
Alan Mishchenko
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1f3cf0aad9
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Experiment with "scorr".
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2024-11-17 15:44:32 -08:00 |
Alan Mishchenko
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3aff0af0c5
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Adding command for generating sorters.
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2024-11-11 21:02:59 -08:00 |
Alan Mishchenko
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b5a76d8ba3
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Compilation problem.
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2024-11-10 19:30:24 -08:00 |
Alan Mishchenko
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f2e4ceb0e3
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Update to "lutexact".
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2024-11-10 19:12:40 -08:00 |
Alan Mishchenko
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aeb977286f
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Updates to LUT cascade synthesis.
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2024-11-10 18:54:35 -08:00 |
Alan Mishchenko
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c787e32f86
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Adding postiive minterm count for random functions generated by "lutexact".
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2024-11-05 22:01:07 -08:00 |
Alan Mishchenko
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091ff4e7a9
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Adding generation of random functions to "lutexact"
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2024-11-05 19:23:04 -08:00 |
Alan Mishchenko
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ecd948027e
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Fixing assertion failures in &put.
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2024-10-23 14:49:57 +07:00 |
Alan Mishchenko
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cb2140dc0c
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Adding PI/PO name transfer after mapping+retiming.
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2024-10-21 20:37:52 +07:00 |
alanminko
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743f3a7bdd
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Merge pull request #250 from wjrforcyber/typo
Refactor(Typo):Typo currently exists
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2024-10-21 01:54:12 -07:00 |
alanminko
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498ec539e6
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Merge pull request #340 from aletempiac/acd_improvements
Performance improvements to ACD
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2024-10-21 01:39:32 -07:00 |
alanminko
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a239dd8c0b
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Merge pull request #328 from heshpdx/master
Perf improvement in satsolver
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2024-10-21 01:38:40 -07:00 |
Alan Mishchenko
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f1773bd612
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Procedure to detect node equivalences across two AIGs.
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2024-10-21 15:15:08 +07:00 |
Alan Mishchenko
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74e7c64662
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Bug fix in &scorr
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2024-10-21 13:16:29 +07:00 |
aletempiac
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baf4ddb16a
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Bug fix (just in the code; it does not affect the execution)
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2024-10-15 19:04:49 +02:00 |
aletempiac
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d1f78b36cb
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Bug fix (just in the code; it does not affect the execution)
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2024-10-15 19:00:45 +02:00 |
aletempiac
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52c842b648
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Cleaning code
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2024-10-15 17:54:38 +02:00 |
aletempiac
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46f2300b7b
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Performance improvements in ACD
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2024-10-15 14:45:09 +02:00 |
Alan Mishchenko
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707442e091
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Bug fix in &scorr.
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2024-10-08 10:01:29 +07:00 |
Alan Mishchenko
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2e3384390a
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Updating "lutexact" to run on symmetric functions.
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2024-10-07 14:10:02 +07:00 |
Alan Mishchenko
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af1de4fa9c
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Improved bit-blasting of some word-level operators.
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2024-10-01 20:34:58 +07:00 |
Alan Mishchenko
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a78d358e1c
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Extending &funtrace to dump and load precomputed library.
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2024-10-01 20:33:01 +07:00 |
Alan Mishchenko
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6004b7b21e
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Adding API for inserting danginling flop.
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2024-10-01 15:55:45 +07:00 |
Alan Mishchenko
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4369321167
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Bug fix.
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2024-09-28 22:39:10 +02:00 |
alanminko
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9539306436
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Merge pull request #334 from mikesinouye/multilib
Increase buffer size in filename append utility to support more liberty files.
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2024-09-22 20:48:15 -07:00 |
Yukio Miyasaka
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35a8768c50
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ttopt bugfix
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2024-09-22 14:34:18 -07:00 |
Mike Inouye
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8179c73e62
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Try support for Windows again.
Signed-off-by: Mike Inouye <mikeinouye@google.com>
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2024-09-18 23:46:28 +00:00 |
Mike Inouye
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5bd52161cd
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Add #include <stdlib.h> for Windows build support.
Signed-off-by: Mike Inouye <mikeinouye@google.com>
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2024-09-18 23:29:11 +00:00 |
Mike Inouye
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ee5acbbc01
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Use <limits.h>'s PATH_MAX macro instead of fixed size.
Signed-off-by: Mike Inouye <mikeinouye@google.com>
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2024-09-18 23:05:32 +00:00 |
Mike Inouye
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db735b632f
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Increase buffer size in filename append utility to support more liberty files.
Signed-off-by: Mike Inouye <mikeinouye@google.com>
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2024-09-18 22:24:41 +00:00 |
Alan Mishchenko
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9c152b71e9
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Trasferring equivalence in the special-case usage of &scorr.
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2024-09-12 18:11:59 -07:00 |
Alan Mishchenko
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0d10253bd0
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Another way of writing primary outputs in Verilog.
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2024-09-06 06:27:53 -07:00 |
Alan Mishchenko
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3ddd46131c
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Updating "read_lib" to output all gates when gain-based modeling is used.
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2024-09-05 17:53:13 -07:00 |
Alan Mishchenko
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3de73f2756
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Updating internal cut manager to prefer cuts with high fanin fanout counts.
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2024-09-05 13:27:17 -07:00 |
Alan Mishchenko
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03d92930fa
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Updating &funtrace to trace function of the primary outputs of the AIG.
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2024-09-03 17:16:48 -07:00 |
Mahesh Madhav
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ad8f8a2aab
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Convert the other divide to a multiply
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2024-09-03 04:48:07 +00:00 |
Mahesh Madhav
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cd711089d7
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Perf improvement in satsolver
Switch one FP divide to an FP multiply (variable is constant).
Calculate ratio inside of verbosity clause, since that is where it is used.
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2024-09-03 04:30:14 +00:00 |
alanminko
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5d6a568c9e
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Merge pull request #327 from YosysHQ/povik/aiger-cell-mapping
Save cell mapping as new 'M' AIGER extension
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2024-08-28 13:23:17 -07:00 |
Martin Povišer
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786a39a294
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Make casts explicit
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2024-08-28 22:09:34 +02:00 |
Martin Povišer
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cb294bbebc
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Save cell mapping as new 'M' AIGER extension
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2024-08-28 16:21:10 +02:00 |
wjrforcyber
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252afb1521
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Refactor(Resub): Clear mark A/B
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2024-08-28 16:51:33 +08:00 |
wjrforcyber
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bcf292fdeb
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Refactor(Resub): Clear markB at the beginning
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2024-08-28 15:41:09 +08:00 |
Alan Mishchenko
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af77b80194
|
Regrouping recently added code.
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2024-08-18 13:57:35 -07:00 |