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2,024 Commits 27 Branches 57 Tags 58 MiB
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17 Commits

Author SHA1 Message Date
Alan Mishchenko b98345ced5 Improvements to buffering and sizing. 2013-08-09 12:36:48 -07:00
Alan Mishchenko 95684b044a Improvements to buffering and sizing. 2013-08-09 11:15:20 -07:00
Alan Mishchenko 881b2ec46f Integrated buffering and sizing. 2013-08-08 18:23:00 -07:00
Alan Mishchenko 655dc4e727 Improvements to buffering and sizing. 2013-08-07 12:32:33 -07:00
Alan Mishchenko 8576e4b440 Improvements to buffering and sizing. 2013-08-06 22:51:39 -07:00
Alan Mishchenko 7a6f335ea6 Improvements to buffering and sizing. 2013-08-06 12:22:13 -07:00
Alan Mishchenko 1a55882ad9 Adding new (un)buffering with phase information. 2013-08-05 18:33:38 -07:00
Alan Mishchenko 1558fe6110 Adding code to estimate buffer trees. 2013-08-05 10:45:06 -07:00
Alan Mishchenko 9d19598162 Change from input slew to input drive strength in the BLIF file. 2013-08-04 12:19:24 -07:00
Alan Mishchenko 56a233be91 Adding switch 'buffer -p' to enable buffing of the primary inputs. 2013-08-02 23:23:45 -07:00
Alan Mishchenko f09a704250 Added commands 'maxsize' and 'unbuffer'. 2013-07-29 21:01:05 -07:00
Alan Mishchenko 1dca7458f3 Improved buffering. 2013-07-29 18:55:13 -07:00
Alan Mishchenko 4c6804c3ae Improved gate-sizing. 2013-07-29 10:10:21 -07:00
Alan Mishchenko 00d023713b Tuning standard-cell mapping flow. 2013-07-24 09:54:53 -07:00
Alan Mishchenko 84c0b9d69b Tuning standard-cell mapping flow. 2013-07-23 16:15:03 -07:00
Alan Mishchenko f392645daf Generating GENLIB library from SCL. 2013-07-22 13:25:51 -07:00
Alan Mishchenko fd28deefc7 Restructuring gate-sizing code trying to separate timing analysis. 2013-07-21 17:55:15 -07:00