luke
/
abc
mirror of https://github.com/YosysHQ/abc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
5,562 Commits 27 Branches 57 Tags 58 MiB
Commit Graph

1736 Commits

Author SHA1 Message Date
Alan Mishchenko a78d358e1c Extending &funtrace to dump and load precomputed library. 2024-10-01 20:33:01 +07:00
Alan Mishchenko 6004b7b21e Adding API for inserting danginling flop. 2024-10-01 15:55:45 +07:00
Alan Mishchenko 9c152b71e9 Trasferring equivalence in the special-case usage of &scorr. 2024-09-12 18:11:59 -07:00
Alan Mishchenko 0d10253bd0 Another way of writing primary outputs in Verilog. 2024-09-06 06:27:53 -07:00
Alan Mishchenko 03d92930fa Updating &funtrace to trace function of the primary outputs of the AIG. 2024-09-03 17:16:48 -07:00
Alan Mishchenko 03b786af99 Experiments with adder-based circuits. 2024-08-17 16:26:20 -07:00
Alan Mishchenko 2055b1b490 Adding an option to dump satisfying assignments into a BLIF file. 2024-08-14 14:41:35 -07:00
Alan Mishchenko c099e62032 Adding a switch to complement the primary outputs of an AIG. 2024-08-14 13:40:52 -07:00
Alan Mishchenko e2b7750d3b Experiments with bit-blasting. 2024-08-14 11:40:41 -07:00
alanminko 324ceeaa08
Merge pull request #320 from YosysHQ/povik/revert-pdr 
Revert recent PDR changes
 2024-08-12 17:17:24 -07:00
Alan Mishchenko 81fcf8494e Updating "lutexact" to support single-rail LUT cascade. 2024-08-12 16:26:55 -07:00
Martin Povišer de8620d777 Revert "pdr -X to write CEXes immediately" 
This reverts commit e62e8ac528.
 2024-08-12 22:53:53 +02:00
Martin Povišer ec8419c84b Revert "Improved anytime pdr" 
This reverts commit 5444cf281c.
 2024-08-12 22:53:40 +02:00
Alan Mishchenko 35a1bbbdb4 Ongoing development related to Boolean decomposition. 2024-08-09 18:33:36 -07:00
Alan Mishchenko 4156a88dbb Extending &funtrace to trace functions found in an AIG. 2024-08-09 12:39:43 -07:00
alanminko 0129b4c60a
Merge pull request #316 from YosysHQ/povik/yosyshq-commands 
Pull command changes from YosysHQ fork
 2024-08-08 14:59:31 -07:00
alanminko e6b36cb5da
Merge pull request #315 from YosysHQ/povik/yosyshq-build 
Pull build-related changes from YosysHQ fork
 2024-08-08 14:58:42 -07:00
Alan Mishchenko 95f1837960 Ongoing development related to Boolean decomposition. 2024-08-07 10:07:39 -07:00
Jannis Harder 5444cf281c Improved anytime pdr 
(cherry picked from commit c832967200)
 2024-08-07 15:46:44 +02:00
Jannis Harder e62e8ac528 pdr -X to write CEXes immediately 
(cherry picked from commit f63471bdf5)
 2024-08-07 15:46:44 +02:00
Jannis Harder adbcb914b2 Add '-p' option to 'constr' to allow fully removing constraints 
Invoking 'constr -r' converts constraints into POs but does not fully
remove them. Now 'constr -pr' can be used to completely remove them,
leaving the set of non-constraint POs unchanged.

(cherry picked from commit 8c923ad492)
 2024-08-07 14:51:38 +02:00
Martin Povišer 57c3bd36f2 Patch to support WASI builds 
Co-authored-by: whitequark <whitequark@whitequark.org>
 2024-08-07 14:49:13 +02:00
Jannis Harder 6d52a1e449 fold: Option (-s) to make sequential cleanup optional 
(cherry picked from commit 1bd088d027)
 2024-08-07 14:47:00 +02:00
Alan Mishchenko 43adbc77e8 New command for LUT cascade decomposition. 2024-08-06 11:50:54 -07:00
Alan Mishchenko 1963422c10 Experiments with detecting multipliers. 2024-08-05 20:18:30 -07:00
Alan Mishchenko b25d9c482a Changing interface of &genrel. 2024-08-02 18:30:09 -07:00
Alan Mishchenko 7d88bf21e9 New command to detect presence of a function in the AIG. 2024-08-02 14:34:57 -07:00
Alan Mishchenko 1954e2fcaa Updating DSD profiling procedures. 2024-08-01 18:36:20 -07:00
Alan Mishchenko 35d67f6c90 The same problem in another place. 2024-07-31 18:03:38 -07:00
Alan Mishchenko 4f68f08a7b Compilation problem. 2024-07-31 17:44:19 -07:00
Alan Mishchenko 9062ed964c Experiments with circuit generators. 2024-07-31 17:39:11 -07:00
Alan Mishchenko 96edf40d60 Allow for disabling variable ordering in "lutmin". 2024-07-28 15:25:22 -07:00
Alan Mishchenko 3e1979f3c6 Experimental features of &scorr. 2024-07-28 13:00:32 -07:00
Alan Mishchenko 93388c0d26 Experiments with DSD. 2024-07-27 14:48:02 -07:00
Alan Mishchenko f8a6432d75 Implementation of functional abstraction. 2024-07-24 20:23:07 -07:00
Alan Mishchenko d036ba520e Updating usage messages of QBF commands. 2024-07-24 09:46:56 -07:00
Alan Mishchenko 5450779250 Improved SOP to BDD conversion. 2024-07-21 16:46:39 -07:00
Alan Mishchenko c7ac6be504 Updating parameters. 2024-07-12 07:28:20 -07:00
Alan Mishchenko ae2e3f90f7 Adding command &genmux. 2024-07-11 22:23:06 -07:00
Alan Mishchenko 24d420370a Adding switch "i" in "show" to display original AIG IDs of mapped nodes. 2024-06-16 17:49:39 +08:00
Alan Mishchenko c64f927828 Various changes and bug fixes. 2024-05-19 14:47:18 -07:00
Alan Mishchenko 3616fd8fb5 New command "resub_unate" and various changes. 2024-05-17 02:56:33 -07:00
Alan Mishchenko d9a08eb44b New command &window to extract windows from an AIG. 2024-05-15 21:41:29 -07:00
Alan Mishchenko 6ad6539c0f New command &genrel to generate relations for windows in the AIG. 2024-05-14 22:35:43 -07:00
Alan Mishchenko daf3313ce6 New aliases. 2024-05-13 23:31:50 -07:00
Alan Mishchenko 554da94ea6 New command &odc to study observability don't-cares. 2024-05-13 22:59:11 -07:00
Alan Mishchenko 66c7f67b96 New command "resub_core". 2024-05-13 21:31:28 -07:00
Alan Mishchenko c194c112ae New way to generate counter-examples. 2024-05-08 23:13:31 -07:00
Alan Mishchenko 3c56ccb8fb Add warning when trying to CEC AIGs with xor-gates. 2024-05-08 08:15:45 -07:00
alanminko ae92ea0214
Merge pull request #297 from aletempiac/yosys-flow 
Integrating delay-driven LUT decomposition in &if
 2024-05-07 06:43:53 -07:00