luke
/
abc
mirror of https://github.com/YosysHQ/abc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
5,698 Commits 27 Branches 57 Tags 58 MiB
Commit Graph

1776 Commits

Author SHA1 Message Date
MyskYko 664d285fcb patch 2025-03-05 04:10:49 -08:00
jiunhaochen 083d3884dd Command rewire 2025-03-01 23:44:55 +08:00
Alan Mishchenko 75ef06017d LUT cascade mapping. 2025-02-27 13:40:11 -08:00
Alan Mishchenko 45c250fb5b New command &randsyn (fixing scalability issue). 2025-02-23 15:49:49 -08:00
Alan Mishchenko a9d959acbe Command "stochmap". 2025-02-23 15:47:28 -08:00
Alan Mishchenko 9e35825e6b New command &randsyn. 2025-02-21 13:20:15 -08:00
alanminko 7bd782382e
Merge pull request #367 from MyskYko/rrr 
New implementation
 2025-02-14 06:19:30 +07:00
MyskYko f51543457d change default parameter 2025-02-13 12:40:48 -08:00
MyskYko 6e3b38c7d3 add rrr 2025-02-12 06:16:02 -08:00
Alan Mishchenko b7bf6c20b6 Improvements to LUT cascade mapping. 2025-02-11 17:32:19 -08:00
Alan Mishchenko d5e1a5d445 Bug fix in &gencex. 2025-01-02 00:33:22 +07:00
Alan Mishchenko 350dcd3ea4 Enabling shared variables in bound set evaluation. 2024-12-28 00:05:00 -08:00
Alan Mishchenko 7d247a08f7 Experiments with bound-set evaluation. 2024-12-26 00:37:37 -08:00
alanminko ef8230d9be
Merge pull request #353 from Carmine50/master 
cec: Modifying algorithm for generating simulation vectors for SAT sweeping (SimGen) and adding new feature to specify the simulation vector of the PIs for SAT sweeping algorithm.
 2024-12-24 11:36:05 -08:00
Carmine50 64e8bb02b9 [CEC][SimGen][Bits to Words] Changing the units of measure for random simulation from number bits to number words 2024-12-24 14:48:57 +01:00
Carmine50 1a89f7ff63 [CEC][SimGen][CLI] Changed function name and help message. Added new option to specify file where to dump simulation vectors. Commented out too verbose information 2024-12-24 11:43:18 +01:00
Alan Mishchenko e21399f3bc Compiler warning. 2024-12-23 08:55:59 -08:00
alanminko 01c6102ca7
Merge pull request #350 from wjrforcyber/put_bug_on_choice 
Fix(&put): &put bug with choices
 2024-12-23 08:52:29 -08:00
Alan Mishchenko 207cfddaa8 Experiments with structural LUT cascade mapping. 2024-12-21 21:24:45 -08:00
Carmine50 b999084ade [CEC][SimGen][CLI] Removed option of nMaxStep since it was unused 2024-12-19 18:12:28 +01:00
Carmine50 30af6f9868 [CEC][SimGen][CLI] Change name of command for simgen 2024-12-19 17:25:45 +01:00
Carmine50 91dcfae020 [CEC][SimGen][Experiment ID] Added experiment ID option to test different experiments with simgen 2024-12-18 19:56:12 +01:00
Carmine50 cbd4456805 [CEC][SimGen][Experiment ID] Added experiment ID option to test different experiments with simgen 2024-12-18 19:53:44 +01:00
Carmine50 99648e132f [CEC][SimGen][CLI] Added command line function to call SimGen main function. 2024-12-18 18:43:38 +01:00
wjrforcyber a8c65f1343
Fix(&put): &put bug with choices 
Related: #349
 2024-12-17 14:05:58 +08:00
Alan Mishchenko 8ba3d9b91c Trying anothe resource limit in scorr. 2024-12-14 13:44:18 -08:00
Ethan Mahintorabi 01c9a65a47
map: Add Mio_Library_t* parameter to Abc_NtkMap 
This lets users of the ABC API call map without relying on the static
Mio_Library_t* in Abc_FrameReadLibGen.
 2024-12-02 06:55:42 +00:00
Alan Mishchenko 14168eb509 Updating command "rungen" to generate random functions. 2024-11-27 22:01:27 -08:00
Alan Mishchenko 1f3cf0aad9 Experiment with "scorr". 2024-11-17 15:44:32 -08:00
Alan Mishchenko 3aff0af0c5 Adding command for generating sorters. 2024-11-11 21:02:59 -08:00
Alan Mishchenko aeb977286f Updates to LUT cascade synthesis. 2024-11-10 18:54:35 -08:00
Alan Mishchenko c787e32f86 Adding postiive minterm count for random functions generated by "lutexact". 2024-11-05 22:01:07 -08:00
Alan Mishchenko 091ff4e7a9 Adding generation of random functions to "lutexact" 2024-11-05 19:23:04 -08:00
Alan Mishchenko ecd948027e Fixing assertion failures in &put. 2024-10-23 14:49:57 +07:00
alanminko 743f3a7bdd
Merge pull request #250 from wjrforcyber/typo 
Refactor(Typo):Typo currently exists
 2024-10-21 01:54:12 -07:00
Alan Mishchenko 2e3384390a Updating "lutexact" to run on symmetric functions. 2024-10-07 14:10:02 +07:00
Alan Mishchenko a78d358e1c Extending &funtrace to dump and load precomputed library. 2024-10-01 20:33:01 +07:00
Alan Mishchenko 6004b7b21e Adding API for inserting danginling flop. 2024-10-01 15:55:45 +07:00
Alan Mishchenko 9c152b71e9 Trasferring equivalence in the special-case usage of &scorr. 2024-09-12 18:11:59 -07:00
Alan Mishchenko 0d10253bd0 Another way of writing primary outputs in Verilog. 2024-09-06 06:27:53 -07:00
Alan Mishchenko 03d92930fa Updating &funtrace to trace function of the primary outputs of the AIG. 2024-09-03 17:16:48 -07:00
Alan Mishchenko 03b786af99 Experiments with adder-based circuits. 2024-08-17 16:26:20 -07:00
Alan Mishchenko 2055b1b490 Adding an option to dump satisfying assignments into a BLIF file. 2024-08-14 14:41:35 -07:00
Alan Mishchenko c099e62032 Adding a switch to complement the primary outputs of an AIG. 2024-08-14 13:40:52 -07:00
Alan Mishchenko e2b7750d3b Experiments with bit-blasting. 2024-08-14 11:40:41 -07:00
alanminko 324ceeaa08
Merge pull request #320 from YosysHQ/povik/revert-pdr 
Revert recent PDR changes
 2024-08-12 17:17:24 -07:00
Alan Mishchenko 81fcf8494e Updating "lutexact" to support single-rail LUT cascade. 2024-08-12 16:26:55 -07:00
Martin Povišer de8620d777 Revert "pdr -X to write CEXes immediately" 
This reverts commit e62e8ac528.
 2024-08-12 22:53:53 +02:00
Martin Povišer ec8419c84b Revert "Improved anytime pdr" 
This reverts commit 5444cf281c.
 2024-08-12 22:53:40 +02:00
Alan Mishchenko 35a1bbbdb4 Ongoing development related to Boolean decomposition. 2024-08-09 18:33:36 -07:00