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738 Commits

Author SHA1 Message Date
Alan Mishchenko 367b20f04d Fixing mismatch in the TLS flow induced by adding cell configs in the DSD manager. 2016-01-30 20:59:57 -08:00
Alan Mishchenko 87f6828d50 Adding support for delay/area tradeoff. 2016-01-13 12:13:54 -08:00
Alan Mishchenko a4f9776388 Consolidating timing manager Scl_Con_t and propagating changes. 2016-01-07 16:50:01 -08:00
Alan Mishchenko 15a891f97a Bug fix in constraint file reader. 2016-01-07 11:57:16 -08:00
Alan Mishchenko c158dd5a94 Migrating to using 32-bit timing representation in &nf. 2016-01-05 16:40:00 -08:00
Alan Mishchenko 19ad75f125 Migrating back to using 'float' in area-flow computation in &nf. 2016-01-05 14:05:07 -08:00
Alan Mishchenko 6642e40af5 Corner-case bug in 'read_profile'. 2015-12-22 22:09:25 -10:00
Alan Mishchenko 19586f105c Adding code to support gate profiles. 2015-12-14 00:44:33 -08:00
Alan Mishchenko e9abb0f489 Adding code to support gate profiles. 2015-12-07 01:31:41 -08:00
Alan Mishchenko 0f29ba75f6 Adding commands to read/write/print gate profiles. 2015-12-05 18:10:43 -08:00
Alan Mishchenko f7c969ca66 Improvements to timing optimization. 2015-11-11 23:12:05 -08:00
Alan Mishchenko 3c9f7d2bc8 Extending and improving timing manager. 2015-11-08 19:59:34 -08:00
Alan Mishchenko efb8ad0af8 Extending and improving timing manager. 2015-11-08 12:08:50 -08:00
Alan Mishchenko 96d8f899d9 Extending and improving timing manager. 2015-11-08 11:44:37 -08:00
Baruch Sterin c0ba25a693 silence clang errors when compiling as C++ 2015-11-05 01:23:31 -08:00
Alan Mishchenko 8ee49ff150 Bug fix in constructing internal choices by 'amap'. 2015-11-04 15:15:18 -08:00
Alan Mishchenko 35143e830b Experiments with precomputation and matching. 2015-10-27 10:48:40 -07:00
Alan Mishchenko bd586dd355 Changes for delay-oriented computation. 2015-10-26 16:44:04 -07:00
Alan Mishchenko 9519341aaf Extending library handling to 8 inputs. 2015-10-25 20:23:44 -07:00
Alan Mishchenko 61d4623207 Adding switch in 'print_genlib' and 'write_genlib' to print area-min gates only. 2015-10-23 17:17:23 -07:00
Alan Mishchenko 3712dd30d0 Changes for delay-oriented computation. 2015-10-23 15:14:31 -07:00
Alan Mishchenko 2c37498bfb Compiler warnings. 2015-10-21 23:53:42 -07:00
Alan Mishchenko 0145b0ca72 Moving BDD-based threshold function detection to the BDD part of the code. 2015-10-16 18:34:06 -07:00
Alan Mishchenko 15a86aefd2 Experiments with precomputation and matching. 2015-10-15 15:32:36 -07:00
Alan Mishchenko 20c46b5a45 Experiments with precomputation and matching. 2015-10-12 18:29:15 -07:00
Alan Mishchenko 46223f903b Two fixes in 'dsd_filter'. 2015-10-07 17:48:07 -07:00
Alan Mishchenko b19d09f04c Bug fix in 'if -g' (incorrect use of a macro). 2015-10-07 08:37:25 -07:00
Alan Mishchenko 78951b4c6f Improvements to Scl_Lib/SC_Cell data-structure. 2015-09-24 12:12:36 -07:00
Alan Mishchenko f1bc346894 Several bug-fixed related to synthesis, library handling, and timimg info. 2015-09-23 18:44:07 -07:00
Alan Mishchenko 19a4bb930e Threshold logic checking code by Augusto Neutzling and Jody Matos. 2015-09-23 15:24:25 -07:00
Alan Mishchenko 97751e43b7 New constraint manager and memory reporting 'ps'. 2015-09-08 19:53:49 -07:00
Alan Mishchenko faeeaeb5e7 Updating Mio to use int instead of float. 2015-08-31 15:09:46 -07:00
Alan Mishchenko 4530ef6444 Alternative way to bit-blast a divisor. 2015-08-29 00:08:41 -07:00
Alan Mishchenko 04be8af560 Important bug fixes in standard-cell library handling and mapper &nf. 2015-08-28 17:47:00 -07:00
Alan Mishchenko 77d64787e0 Changes to be able to compile ABC without CUDD. 2015-08-24 19:49:18 -07:00
Alan Mishchenko 1fffe8f6f3 New switch in 'read_lib' to replace gate/pin names by short strings. 2015-08-24 18:07:10 -07:00
Alan Mishchenko 5bf0f86450 New switch in 'read_lib' to replace gate/pin names by short strings. 2015-08-24 17:40:20 -07:00
Alan Mishchenko 0e4561ab9f Experiments with mapping plus small changes. 2015-08-23 20:38:55 -07:00
Alan Mishchenko 10e0f3c58d Small changes to enable collecting results using &ps -D file. 2015-07-09 11:50:24 -07:00
Alan Mishchenko fd5b7e8b5d Bug fix in programmable cell parser and minor tuning. 2015-07-08 16:59:22 -07:00
Alan Mishchenko 609be7a114 C++ compiler typecast problem. 2015-07-08 15:04:26 -07:00
Alan Mishchenko 9894fc762e Add fix to Liberty parser to skip extra semicolon. 2015-07-06 07:57:18 -07:00
Alan Mishchenko b4d0abb77d Undo recent assert. 2015-06-27 21:38:32 -07:00
Alan Mishchenko 66ef4a9ac1 Potential performance bug in the mapper. 2015-06-27 19:57:49 -07:00
Alan Mishchenko d0d7763ef8 Supporting AND-gate cuts in 'if' and '&if' 2015-06-21 13:31:02 -07:00
Alan Mishchenko 14b7a520a1 Bug fix in 'dsd_tune' when processing cells with 0-input LUTs. 2015-05-15 22:36:11 -07:00
Alan Mishchenko 37b6b5f1f8 Making sure 0-input LUTs are supported by the DSD matching code. 2015-05-14 13:12:17 -07:00
Alan Mishchenko c0f0e145c4 Improving the criteria to select representative gates in 'map' with floating-point-delay libraries having more than one gate in some functionality classes. 2015-04-25 14:58:29 -07:00
Alan Mishchenko 9e20b3016d Adding switch 'map -f' to not use large gates for high-fanout nodes (disabled by default). 2015-04-24 14:51:34 -07:00
Alan Mishchenko a78fb767ee Adding platform-independent (alphabetic) way of sorting Genlib gates and selecting representatives based on area/delay. 2015-04-17 21:02:15 +09:00
Alan Mishchenko 3de5d18c5f Adding APIs to retrieve NOR/OR gates from the library. 2015-04-14 18:53:28 +09:00
Alan Mishchenko b3e5ccd256 Getting default AND-node delay from Genlib library. 2015-04-06 10:56:14 +07:00
Alan Mishchenko bb22a20cb0 Support for representing programmable cell configuration data (bug fix). 2015-03-09 08:36:22 -07:00
Alan Mishchenko 193c46e3c6 Support for representing programmable cell configuration data. 2015-03-08 20:19:56 -07:00
Alan Mishchenko 56f783157a Support for representing programmable cell configuration data. 2015-03-08 20:17:59 -07:00
Alan Mishchenko 6da21b8b88 Experiments with SAT-based cube enumeration. 2015-03-05 23:00:30 -08:00
Alan Mishchenko 874d394089 Corner case bug in wire-cap estimation. 2015-02-18 09:18:01 -08:00
Alan Mishchenko fd877c3f37 Several improvements to CBA data-structure. 2015-02-09 15:36:25 -08:00
Alan Mishchenko 68467cfff7 Fixed a typo in variable names. 2015-02-07 22:29:14 -08:00
Alan Mishchenko 8410daf3e4 Improvements and tuning of CBA with buffering/sizing. 2015-02-04 16:29:55 -08:00
Alan Mishchenko 7b1c25086b Improvements and tuning of CBA. 2015-02-01 20:50:59 -08:00
Alan Mishchenko 77dbe2b656 Major rehash of the CBA code. 2015-01-31 19:52:32 -08:00
Alan Mishchenko 0f22046bcb New assertions and bug fix in DSD balancing. 2015-01-27 09:54:35 -08:00
Alan Mishchenko 58d28539a7 Gate sizing with barrier buffers. 2014-12-21 22:22:31 -08:00
Alan Mishchenko 6733abd72e Exprimental features in tech-mapping. 2014-12-21 01:04:39 -08:00
Alan Mishchenko 55f0a2805c Bug fix in reading box library. 2014-12-20 10:16:13 -08:00
Alan Mishchenko aadfea8b4d Integrating barrier buffers. 2014-12-13 12:37:04 -08:00
Alan Mishchenko b379b3ee20 Adding new mapping feature. 2014-12-11 20:45:41 -08:00
Alan Mishchenko 1398de7c46 Integrating barrier buffers. 2014-12-08 14:10:41 -08:00
Alan Mishchenko 3653bf53e9 Bug fix in truth table computation. 2014-10-15 14:26:44 -07:00
Alan Mishchenko 3ac8aa9c12 Recommended changes for portability. 2014-10-12 09:10:27 -07:00
Alan Mishchenko 8b160138f1 MUX decomposition during mapping. 2014-10-11 17:19:41 -07:00
Alan Mishchenko 09a5950c8f Deriving network in terms of programmable cells. 2014-10-11 15:53:32 -07:00
Alan Mishchenko ccb5bb34d7 Suggested patch for type-punned warnings 2014-10-10 08:58:18 -07:00
Alan Mishchenko ca9eca3b22 Small changes. 2014-10-08 13:26:23 -07:00
Alan Mishchenko 141c1de0a2 Compiler warnings. 2014-10-08 10:52:32 -07:00
Alan Mishchenko e4d5887671 Detection of threshold functions. 2014-10-08 10:41:20 -07:00
Alan Mishchenko 734435f441 Deriving cell mapping with &if -kz. 2014-10-04 19:36:41 -07:00
Alan Mishchenko 24083998ab Deriving cell mapping with &if -kz. 2014-10-04 19:18:34 -07:00
Alan Mishchenko fa5f05e3a2 Deriving AIG after cell mapping. 2014-10-03 17:15:43 -07:00
Alan Mishchenko 76666174b4 Synchronizing packages. 2014-09-20 16:41:11 -07:00
Alan Mishchenko 2d4342f8c4 Synchronizing packages. 2014-09-20 14:50:52 -07:00
Alan Mishchenko 00b8cda3d3 Synchronizing packages. 2014-09-20 14:10:05 -07:00
Alan Mishchenko 1fb65889a3 Updating command 'dsd_clean'. 2014-09-20 13:56:26 -07:00
Alan Mishchenko a02b020356 Updating DSD balance to handle XOR gate as having the same delay as AND gate. 2014-09-19 19:06:01 -07:00
Alan Mishchenko f989aea224 Improvements to Boolean matching. 2014-09-19 15:08:46 -07:00
Alan Mishchenko b05ee94311 Improvements to Boolean matching. 2014-09-19 14:06:51 -07:00
Alan Mishchenko ee72791293 Improvements to Boolean matching. 2014-09-18 22:26:54 -07:00
Alan Mishchenko 69699da912 Improvements to Boolean matching. 2014-09-18 16:44:04 -07:00
Alan Mishchenko 596f387b03 Improvements to Boolean matching. 2014-09-18 15:13:12 -07:00
Alan Mishchenko a0ed347992 Improving DSD manager. 2014-09-18 14:50:08 -07:00
Alan Mishchenko 043cfcd775 Concurrency for Boolean matching. 2014-09-18 11:46:14 -07:00
Alan Mishchenko 023e92c470 Improvements to Boolean matching. 2014-09-17 18:58:20 -07:00
Alan Mishchenko 6d0b555dab Support for leakage power in Liberty parser and sizer. 2014-09-16 16:44:51 -07:00
Alan Mishchenko 288d64d033 New choice computation. 2014-09-16 14:59:28 -07:00
Alan Mishchenko 1d5cb52e4a Improvements to Boolean matching. 2014-09-16 11:56:40 -07:00
Alan Mishchenko 70a3474849 Improvements to the timing manager. 2014-08-25 20:47:11 -05:00
Alan Mishchenko 47dde4e478 Correcting incorrect handling of timing in several &-commands. 2014-08-25 16:55:39 -07:00
Alan Mishchenko ec5bc5825d Adding specialized matching to 'if'. 2014-08-16 18:34:20 -07:00
Alan Mishchenko 97e620a4b7 Adding specialized matching to 'if'. 2014-08-16 18:28:41 -07:00