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1,330 Commits 29 Branches 57 Tags 61 MiB
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160 Commits

Author SHA1 Message Date
Alan Mishchenko d40af538e2 Unified print-out of property failures produced by all engines. 2012-09-09 20:46:34 -07:00
Alan Mishchenko f6b67d7846 Added new command &gla_shrink. 2012-09-04 23:57:58 -07:00
Alan Mishchenko 942600414d Added simulation of comb circuits with user-specified patterns in command 'sim'. 2012-08-24 11:12:51 -07:00
Alan Mishchenko 94193472c8 Fixing assertion mismatch in bmc2. 2012-07-14 09:25:18 -07:00
Alan Mishchenko b9ee5d8564 Improvements in the proof-logging SAT solver. 2012-07-11 12:45:46 -07:00
Alan Mishchenko 637736827a Adding several command-line arguments to 'dsat'. 2012-07-09 19:24:39 -07:00
Alan Mishchenko ff0ec52d4d Updating memory print-out of &vta and &gla. 2012-07-08 14:01:28 -07:00
Alan Mishchenko 6c3363f777 Adding restart to rarity simulation in sim3 and &sim3. 2012-07-08 13:23:05 -07:00
Alan Mishchenko 1c33107cbb Updating project settings to have simpler include paths. 2012-07-07 20:14:12 -07:00
Alan Mishchenko 3aab724573 Fixing time primtouts throughout the code. 2012-07-07 17:46:54 -07:00
Alan Mishchenko 7452455155 Changing the rules of assigning the names when AIG is converted into a logic network. 2012-05-11 08:35:54 +07:00
Alan Mishchenko a4144cf0d1 Making demiter dump files in the current directory. 2012-03-26 12:55:58 -07:00
Alan Mishchenko 8ed3e40a52 Logic sharing for multi-input gates. 2012-03-25 22:47:08 -07:00
Alan Mishchenko 3abd9773a4 Enabled demitering dual-output miters. 2012-03-23 22:52:30 -07:00
Alan Mishchenko 0792ab0eb6 Additional features for delay optimization 2012-03-21 23:19:49 -07:00
Alan Mishchenko fec988f619 Renamed Aig_ObjPioNum to be Aig_ObjCioId. 2012-03-09 19:59:35 -08:00
Alan Mishchenko c46c957a07 Renamed Aig_ObjIsPi/Po to be ...Ci/Co and Aig_Man(Pi/Po)Num to be ...(Ci/Co)... 2012-03-09 19:50:18 -08:00
Alan Mishchenko 2c8f1a67ec Renamed Aig_ManForEachPi/Po to be ...Ci/Co and Aig_ObjCreatePi/Po to be ...Ci/Co. 2012-03-09 19:32:44 -08:00
Alan Mishchenko 7fa9de2da4 Redirecting printf messages. 2012-03-02 01:31:44 -08:00
Alan Mishchenko b06908d1e8 Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default (bug fix). 2012-02-25 15:54:11 -08:00
Alan Mishchenko b4fe108d86 Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default. 2012-02-24 16:11:49 -08:00
Alan Mishchenko 3552d39b71 Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default. 2012-02-24 13:37:31 -08:00
Alan Mishchenko d80f43a185 Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default. 2012-02-24 13:21:32 -08:00
Alan Mishchenko 791b107e7a Silencing some of the gcc warnings. 2012-02-16 21:53:16 -08:00
Alan Mishchenko c39fd3741a Added returning counter-example after BMC, which was recently added to 'dprove'. 2012-01-23 12:41:55 -08:00
Alan Mishchenko 8014f25f6d Major restructuring of the code. 2012-01-21 04:30:10 -08:00
Alan Mishchenko fffd733f94 Replaced 'bmc' by 'bmc2' in 'dprove'. Added switches to 'dprove' to control BMC frames and conflicts. 2012-01-19 14:24:56 -08:00
Alan Mishchenko d2db956a61 Started experiments with a new solver. 2011-11-25 18:08:48 -08:00
Alan Mishchenko 5b75410a5e Fixed the overflow timeout problem in bmc/bmc2/bmc3/int/pdr/sim, etc. 2011-10-31 15:04:47 -05:00
Alan Mishchenko 12b70d4946 Changes to CNF generation code. 2011-10-17 10:39:05 +03:00
Alan Mishchenko df6d509023 Sequential cleanup with symbolic/ternary simulation. 2011-08-25 14:14:50 +07:00
Alan Mishchenko 3469b605e1 Sequential cleanup with symbolic/ternary simulation. 2011-08-24 17:39:57 +07:00
Alan Mishchenko 49df91f071 Several bug fixes. 2011-08-02 12:58:37 +07:00
Alan Mishchenko 6c6c0b0686 Enabled saving vector of counter-examples in the ABC framework. 2011-08-02 00:31:03 +07:00
Alan Mishchenko 0d65c49048 Improvements to 'bmc3' (start frame; stop when all POs are SAT; stop when 2^nRegs frames are completed). 2011-07-31 20:22:57 +07:00
Alan Mishchenko 02711b6392 Added generation of counter-examples to induction in 'ind'. 2011-07-30 19:18:26 +07:00
Alan Mishchenko c60852f4a9 Changes to enable smarter simulation. 2011-07-30 13:37:02 +07:00
Alan Mishchenko 2ea0ded0bc Changes to enable smarter simulation. 2011-07-30 13:30:04 +07:00
Alan Mishchenko ce38474c74 Improving and updating the abstraction code. 2011-07-29 15:38:44 +07:00
Alan Mishchenko 76447062cc Adding &equiv3, a new way of refining equivalence classes. 2011-07-22 20:20:19 +07:00
Alan Mishchenko 9a2a0f2912 Changes to enable smarter simulation. 2011-07-21 17:55:44 +07:00
Alan Mishchenko bb86d9142e New demitering features. 2011-07-20 13:52:54 +07:00
Alan Mishchenko f866920eb5 Added a new demitering feature for dual-output miters. 2011-07-02 13:58:12 -07:00
Alan Mishchenko 31360734b7 Added new command 'outdec'. 2011-05-19 11:43:11 +07:00
Alan Mishchenko e2e3f6a228 Improvements in sequential verification. 2011-05-06 20:33:06 -07:00
Alan Mishchenko 5222f382af Adding SAT-solver-level timeouts to the BMC engines. 2011-04-08 15:35:59 -07:00
Alan Mishchenko 92a1c5b58e Several bug fixes and other improvements. 2011-03-12 19:44:38 -08:00
Alan Mishchenko 148a786b69 Made abc.h independent of CUDD and Extra. 2011-03-03 12:28:52 -08:00
Alan Mishchenko 71cbf17e7f Unified the use of counter-examples in three packages. 2011-02-13 17:46:48 -08:00
Alan Mishchenko d4291dab37 Cumulative changes of the last two weeks. 2011-02-01 15:47:55 -08:00