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5,041 Commits 27 Branches 57 Tags 58 MiB
Commit Graph

380 Commits

Author SHA1 Message Date
Alan Mishchenko 8888e8e82e Experiments with the mapper. 2022-06-23 07:48:10 -07:00
Alan Mishchenko 21922e3e9f Adding switch to dsd_match to skip small functions. 2022-05-18 10:43:07 -07:00
Alan Mishchenko 787dbb9433 Two rare corner-case bugs in &if mapper. 2021-09-26 11:05:48 -07:00
Alan Mishchenko 9fac6c7a8b Experiments with CEC. 2021-07-10 10:50:33 -07:00
Alan Mishchenko 96b9192c78 Experiments with MUX decomposition. 2021-07-08 21:54:07 -07:00
Alan Mishchenko 8889ccb18c Updating LUT synthesis code. 2021-05-26 23:25:08 -07:00
Alan Mishchenko e463930709 Updating the mapper when user-specific matching is used. 2021-01-09 18:39:37 -08:00
Alan Mishchenko 73f8b598ac Rare bug fix in mapping with choices. 2020-10-29 17:21:37 -07:00
Alan Mishchenko f6dc4a588c Making sure arrival time of constant node is -infinity. 2020-01-02 17:58:05 -05:00
Alan Mishchenko b292595062 Adding switch to &if to consider special type of 6-input cuts. 2019-09-26 14:05:16 -07:00
Alan Mishchenko 390adc39ca Making &mfs work with boxes larger than 6 inputs. Adding option &if -w to print delay profile. 2019-09-19 16:49:36 -07:00
Alan Mishchenko ee1bd8f0be Fixing some update gcc. 2019-07-24 11:44:28 +07:00
Alan Mishchenko 62487de97b Adding support for user-specified wire delays in &if. 2019-05-29 14:46:25 -07:00
Alan Mishchenko f0efc6e098 Prevent assertions from firing for deep logic networks. 2019-03-20 22:07:27 +02:00
Alan Mishchenko 01569b8f5f Fixing some warnings by adding cast from 'int' to 'size_t' in memset, memcpy, etc. 2019-03-05 15:57:50 -08:00
Alan Mishchenko 1f016988b2 Fixing float overflow during edge-flow computation in 'if' mapper (change to avoid dependence on the order of additions). 2018-12-12 22:15:10 -08:00
Alan Mishchenko 2f88284d7b Fixing float overflow during edge-flow computation in 'if' mapper. 2018-12-12 10:47:53 -08:00
Alan Mishchenko 5aa3025ce7 Adding switch &w -n to modify the comment section of the AIGER file written. 2018-11-21 13:12:01 -08:00
Alan Mishchenko 7e9f3f027b Adding parameters and improvements to %blast. 2018-02-28 18:45:44 -08:00
Alan Mishchenko accf4825e5 Adding API to dump MiniAIG into a Verilog file and other small changes. 2017-10-22 15:44:13 -07:00
Alan Mishchenko c696ae95d0 Maintenance and updates. 2017-09-24 23:38:01 -07:00
Alan Mishchenko 287f9efcce Maintenance and updates. 2017-09-20 19:27:46 -07:00
Alan Mishchenko 3a1032c151 Maintenance and updates. 2017-09-18 08:27:05 -07:00
Alan Mishchenko 2e56f44c66 Compiler warnings. 2017-07-22 11:41:17 +07:00
Alan Mishchenko 859e769f22 Synchronizing various data-structures. 2017-07-04 15:23:51 -07:00
Alan Mishchenko bf6a053c64 Saturating floating point computation. 2017-07-01 13:48:31 -07:00
Alan Mishchenko 8ad3d6bec8 Bug fixes by Clifford Wolf. 2017-01-08 03:10:42 +07:00
Alan Mishchenko 460167ec74 Compiler warnings. 2017-01-07 08:57:08 +07:00
Alan Mishchenko 693b587c5c Adding truth table occurrence counters for 'if -c'. 2016-08-08 18:20:05 -07:00
Alan Mishchenko 713976f2cf Enabled progress bar in the 'if' mapper (warning). 2016-08-08 12:38:21 -07:00
Alan Mishchenko a819e33c6f Enabled delay computation for the cut output using cut inputs. 2016-08-08 12:36:10 -07:00
Alan Mishchenko 473012aaf0 Enabled progress bar in the 'if' mapper. 2016-08-08 11:56:33 -07:00
Alan Mishchenko fd8eb8c855 Adding one argument to the delay-estimation API used for exact synthesis. 2016-07-31 13:31:57 -07:00
Alan Mishchenko cf91699e05 Infrastructure for using the results of exact SAT-based synthesis during mapping. 2016-07-29 16:34:47 -07:00
Alan Mishchenko fb33d69db8 Infrastructure for using the results of exact SAT-based synthesis during mapping. 2016-07-29 16:03:42 -07:00
Alan Mishchenko 53e8647719 Adding option to rehash AIG after mapping. 2016-04-27 18:33:23 -07:00
Alan Mishchenko 367b20f04d Fixing mismatch in the TLS flow induced by adding cell configs in the DSD manager. 2016-01-30 20:59:57 -08:00
Alan Mishchenko 2c37498bfb Compiler warnings. 2015-10-21 23:53:42 -07:00
Alan Mishchenko 0145b0ca72 Moving BDD-based threshold function detection to the BDD part of the code. 2015-10-16 18:34:06 -07:00
Alan Mishchenko 46223f903b Two fixes in 'dsd_filter'. 2015-10-07 17:48:07 -07:00
Alan Mishchenko b19d09f04c Bug fix in 'if -g' (incorrect use of a macro). 2015-10-07 08:37:25 -07:00
Alan Mishchenko 19a4bb930e Threshold logic checking code by Augusto Neutzling and Jody Matos. 2015-09-23 15:24:25 -07:00
Alan Mishchenko 0e4561ab9f Experiments with mapping plus small changes. 2015-08-23 20:38:55 -07:00
Alan Mishchenko 10e0f3c58d Small changes to enable collecting results using &ps -D file. 2015-07-09 11:50:24 -07:00
Alan Mishchenko fd5b7e8b5d Bug fix in programmable cell parser and minor tuning. 2015-07-08 16:59:22 -07:00
Alan Mishchenko 609be7a114 C++ compiler typecast problem. 2015-07-08 15:04:26 -07:00
Alan Mishchenko b4d0abb77d Undo recent assert. 2015-06-27 21:38:32 -07:00
Alan Mishchenko d0d7763ef8 Supporting AND-gate cuts in 'if' and '&if' 2015-06-21 13:31:02 -07:00
Alan Mishchenko 14b7a520a1 Bug fix in 'dsd_tune' when processing cells with 0-input LUTs. 2015-05-15 22:36:11 -07:00
Alan Mishchenko 37b6b5f1f8 Making sure 0-input LUTs are supported by the DSD matching code. 2015-05-14 13:12:17 -07:00