mirror of https://github.com/YosysHQ/abc.git
Integrating barrier buffers.
This commit is contained in:
Alan Mishchenko
parent
aadfea8b4d
commit
e946deec81
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@ -211,7 +211,7 @@ Gia_Man_t * Gia_ManFlattenLogicHierarchy2( Abc_Ntk_t * pNtk )
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SeeAlso []
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***********************************************************************/
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void Gia_ManFlattenLogicPrepare( Abc_Ntk_t * pNtk )
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int Gia_ManFlattenLogicPrepare( Abc_Ntk_t * pNtk )
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{
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Abc_Obj_t * pTerm, * pBox;
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int i, k;
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@ -228,8 +228,9 @@ void Gia_ManFlattenLogicPrepare( Abc_Ntk_t * pNtk )
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Abc_ObjForEachFanout( pBox, pTerm, k )
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pTerm->iData = k;
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}
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return Abc_NtkPiNum(pNtk) + Abc_NtkPoNum(pNtk);
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}
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int Gia_ManFlattenLogicHierarchy_rec( Gia_Man_t * pNew, Vec_Ptr_t * vSupers, Abc_Obj_t * pObj, Vec_Int_t * vBufs )
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int Gia_ManFlattenLogicHierarchy_rec( Gia_Man_t * pNew, Vec_Ptr_t * vSupers, Abc_Obj_t * pObj, Vec_Ptr_t * vBuffers )
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{
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Abc_Ntk_t * pModel;
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Abc_Obj_t * pBox, * pFanin;
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@ -237,62 +238,66 @@ int Gia_ManFlattenLogicHierarchy_rec( Gia_Man_t * pNew, Vec_Ptr_t * vSupers, Abc
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if ( pObj->iTemp != -1 )
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return pObj->iTemp;
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if ( Abc_ObjIsNet(pObj) || Abc_ObjIsPo(pObj) || Abc_ObjIsBi(pObj) )
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return (pObj->iTemp = Gia_ManFlattenLogicHierarchy_rec(pNew, vSupers, Abc_ObjFanin0(pObj), vBufs));
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return (pObj->iTemp = Gia_ManFlattenLogicHierarchy_rec(pNew, vSupers, Abc_ObjFanin0(pObj), vBuffers));
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if ( Abc_ObjIsPi(pObj) )
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{
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pBox = (Abc_Obj_t *)Vec_PtrPop( vSupers );
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pModel = (Abc_Ntk_t *)pBox->pData;
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pModel = Abc_ObjModel(pBox);
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//printf( " Exiting %s\n", Abc_NtkName(pModel) );
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assert( Abc_ObjFaninNum(pBox) == Abc_NtkPiNum(pModel) );
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assert( pObj->iData >= 0 && pObj->iData < Abc_NtkPiNum(pModel) );
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pFanin = Abc_ObjFanin( pBox, pObj->iData );
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iLit = Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pFanin, vBufs );
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iLit = Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pFanin, vBuffers );
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Vec_PtrPush( vSupers, pBox );
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return (pObj->iTemp = (vBufs ? Gia_ManAppendBuf(pNew, iLit) : iLit));
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//if ( vBuffers ) Vec_PtrPush( vBuffers, pFanin ); // save BI
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if ( vBuffers ) Vec_PtrPush( vBuffers, pObj ); // save PI
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return (pObj->iTemp = (vBuffers ? Gia_ManAppendBuf(pNew, iLit) : iLit));
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}
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if ( Abc_ObjIsBo(pObj) )
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{
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pBox = Abc_ObjFanin0(pObj);
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assert( Abc_ObjIsBox(pBox) );
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Vec_PtrPush( vSupers, pBox );
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pModel = (Abc_Ntk_t *)pBox->pData;
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pModel = Abc_ObjModel(pBox);
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//printf( "Entering %s\n", Abc_NtkName(pModel) );
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assert( Abc_ObjFanoutNum(pBox) == Abc_NtkPoNum(pModel) );
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assert( pObj->iData >= 0 && pObj->iData < Abc_NtkPoNum(pModel) );
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pFanin = Abc_NtkPo( pModel, pObj->iData );
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iLit = Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pFanin, vBufs );
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iLit = Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pFanin, vBuffers );
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Vec_PtrPop( vSupers );
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return (pObj->iTemp = (vBufs ? Gia_ManAppendBuf(pNew, iLit) : iLit));
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//if ( vBuffers ) Vec_PtrPush( vBuffers, pObj ); // save BO
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if ( vBuffers ) Vec_PtrPush( vBuffers, pFanin ); // save PO
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return (pObj->iTemp = (vBuffers ? Gia_ManAppendBuf(pNew, iLit) : iLit));
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}
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assert( Abc_ObjIsNode(pObj) );
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Abc_ObjForEachFanin( pObj, pFanin, i )
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Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pFanin, vBufs );
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Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pFanin, vBuffers );
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return (pObj->iTemp = Abc_NodeStrashToGia( pNew, pObj ));
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}
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Gia_Man_t * Gia_ManFlattenLogicHierarchy( Abc_Ntk_t * pNtk )
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Gia_Man_t * Gia_ManFlattenLogicHierarchy( Abc_Ntk_t * pNtk, Vec_Ptr_t ** pvBuffers )
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{
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int fUseBufs = 1;
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Gia_Man_t * pNew, * pTemp;
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Abc_Ntk_t * pModel;
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Abc_Obj_t * pTerm;
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Vec_Ptr_t * vSupers;
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int i;//, Counter = -1;
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Vec_Ptr_t * vBuffers = fUseBufs ? Vec_PtrAlloc(1000) : NULL;
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int i, Counter = 0;
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assert( Abc_NtkIsNetlist(pNtk) );
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// Abc_NtkPrintBoxInfo( pNtk );
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// create DFS order of nets
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// set the PI/PO numbers
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Counter -= Abc_NtkPiNum(pNtk) + Abc_NtkPoNum(pNtk);
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if ( !pNtk->pDesign )
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Gia_ManFlattenLogicPrepare( pNtk );
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Counter += Gia_ManFlattenLogicPrepare( pNtk );
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else
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Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pModel, i )
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Gia_ManFlattenLogicPrepare( pModel );
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Counter += Gia_ManFlattenLogicPrepare( pModel );
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// start the manager
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pNew = Gia_ManStart( Abc_NtkObjNumMax(pNtk) );
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pNew->pName = Abc_UtilStrsav(pNtk->pName);
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pNew->pSpec = Abc_UtilStrsav(pNtk->pSpec);
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if ( fUseBufs )
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pNew->vBarBufs = Vec_IntAlloc( 1000 );
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// create PIs and buffers
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Abc_NtkForEachPi( pNtk, pTerm, i )
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@ -302,16 +307,20 @@ Gia_Man_t * Gia_ManFlattenLogicHierarchy( Abc_Ntk_t * pNtk )
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vSupers = Vec_PtrAlloc( 100 );
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Gia_ManHashAlloc( pNew );
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Abc_NtkForEachPo( pNtk, pTerm, i )
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Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pTerm, pNew->vBarBufs );
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Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pTerm, vBuffers );
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Gia_ManHashStop( pNew );
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Vec_PtrFree( vSupers );
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printf( "Hierarchy reader flattened %d instances of boxes.\n", pNtk->pDesign ? Vec_PtrSize(pNtk->pDesign->vModules)-1 : 0 );
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printf( "Hierarchy reader flattened %d instances of boxes and added %d barbufs (out of %d).\n",
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pNtk->pDesign ? Vec_PtrSize(pNtk->pDesign->vModules)-1 : 0, Vec_PtrSize(vBuffers), &Counter );
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// create buffers and POs
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Abc_NtkForEachPo( pNtk, pTerm, i )
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Gia_ManAppendCo( pNew, pTerm->iTemp );
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// save buffers
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// Vec_IntPrint( pNew->vBarBufs );
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if ( pvBuffers )
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*pvBuffers = vBuffers;
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else
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Vec_PtrFreeP( &vBuffers );
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// cleanup
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pNew = Gia_ManCleanup( pTemp = pNew );
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@ -319,6 +328,100 @@ Gia_Man_t * Gia_ManFlattenLogicHierarchy( Abc_Ntk_t * pNtk )
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return pNew;
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}
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/**Function*************************************************************
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Synopsis [Inserts the result of mapping into logic hierarchy.]
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Description [When this procedure is called PIs/POs of pNtk
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point to the corresponding nodes in network with barbufs.]
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Abc_Obj_t * Gia_ManInsertOne_rec( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNew, Abc_Obj_t * pObj )
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{
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Abc_Obj_t * pFanin; int i;
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if ( pObj == NULL )
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return Abc_NtkCreateNodeConst0( pNtk );
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assert( Abc_ObjNtk(pObj) == pNew );
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if ( pObj->pCopy )
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return pObj->pCopy;
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Abc_ObjForEachFanin( pObj, pFanin, i )
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Gia_ManInsertOne_rec( pNtk, pNew, pFanin );
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pObj->pCopy = Abc_NtkDupObj( pNtk, pObj, 0 );
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Abc_ObjForEachFanin( pObj, pFanin, i )
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Abc_ObjAddFanin( pObj, pFanin );
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return pObj->pCopy;
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}
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void Gia_ManInsertOne( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNew )
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{
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Abc_Obj_t * pObj, * pBox; int i, k;
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// check that PIs point to barbufs
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Abc_NtkForEachPi( pNtk, pObj, i )
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assert( !pObj->pCopy || Abc_ObjNtk(pObj->pCopy) == pNew );
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// make barbufs point to box outputs
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Abc_NtkForEachBox( pNtk, pBox, i )
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Abc_ObjForEachFanout( pBox, pObj, k )
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{
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pObj->pCopy = Abc_NtkPo(Abc_ObjModel(pBox), k)->pCopy;
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assert( !pObj->pCopy || Abc_ObjNtk(pObj->pCopy) == pNew );
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}
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// remove internal nodes
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Abc_NtkForEachNode( pNtk, pObj, i )
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Abc_NtkDeleteObj( pObj );
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// start traversal from box inputs
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Abc_NtkForEachBox( pNtk, pBox, i )
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Abc_ObjForEachFanin( pBox, pObj, k )
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if ( Abc_ObjFaninNum(pObj) == 0 )
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Abc_ObjAddFanin( pObj, Gia_ManInsertOne_rec(pNtk, pNew, Abc_NtkPi(Abc_ObjModel(pBox), k)->pCopy) );
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// start traversal from primary outputs
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Abc_NtkForEachPo( pNtk, pObj, i )
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if ( Abc_ObjFaninNum(pObj) == 0 )
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Abc_ObjAddFanin( pObj, Gia_ManInsertOne_rec(pNtk, pNew, pObj->pCopy) );
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}
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void Gia_ManInsertLogicHierarchy( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNew )
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{
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Vec_Ptr_t * vBuffers;
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Gia_Man_t * pGia = Gia_ManFlattenLogicHierarchy( pNtk, &vBuffers );
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Abc_Ntk_t * pModel;
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Abc_Obj_t * pObj;
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int i;
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assert( Gia_ManPiNum(pGia) == Abc_NtkPiNum(pNtk) );
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assert( Gia_ManPiNum(pGia) == Abc_NtkPiNum(pNew) );
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assert( Gia_ManPoNum(pGia) == Abc_NtkPoNum(pNtk) );
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assert( Gia_ManPoNum(pGia) == Abc_NtkPoNum(pNew) );
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assert( Gia_ManBufNum(pGia) == Vec_PtrSize(vBuffers) );
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assert( Gia_ManBufNum(pGia) == pNew->nBarBufs2 );
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Gia_ManStop( pGia );
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// clean the networks
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if ( !pNtk->pDesign )
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Abc_NtkCleanCopy( pNtk );
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else
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Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pModel, i )
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Abc_NtkCleanCopy( pModel );
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// annotate PIs and POs of each network with barbufs
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Abc_NtkForEachPi( pNew, pObj, i )
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Abc_NtkPi(pNtk, i)->pCopy = pObj;
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Abc_NtkForEachPo( pNew, pObj, i )
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Abc_NtkPo(pNtk, i)->pCopy = pObj;
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Abc_NtkForEachBarBuf( pNew, pObj, i )
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((Abc_Obj_t *)Vec_PtrEntry(vBuffers, i))->pCopy = pObj;
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Vec_PtrFree( vBuffers );
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// connect each model
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Abc_NtkCleanCopy( pNew );
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Gia_ManInsertOne( pNtk, pNew );
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if ( pNtk->pDesign )
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Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pModel, i )
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if ( pModel != pNtk )
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Gia_ManInsertOne( pModel, pNew );
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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