mirror of https://github.com/YosysHQ/abc.git
glucose2: Allow re-definition of gates
This enables e.g. rewriting the circuit based on discovered equivalences. This avoids re-introducing doubly linked lists for the fanout by instead keeping a vector of variables whose fanout lists contain gate inputs that were changed to a different literal. The first time propagation runs with that vector nonempty, it deduplicates that vector and then traverses the affected lists and moves every changed gate input into the correct list.
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@ -246,6 +246,16 @@ inline void Solver::setVarFaninLits( Var v, Lit lit1, Lit lit2 ){
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int mincap = var(lit1) < var(lit2)? var(lit2): var(lit1);
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mincap = (v < mincap? mincap: v) + 1;
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if (var2NodeData[ v ].lit0 != toLit(~0)) {
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flushFanout.push(var(var2NodeData[ v ].lit0));
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flushFanout.push(var(var2NodeData[ v ].lit1));
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var2NodeData[ v ].lit0 = lit1;
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var2NodeData[ v ].lit1 = lit2;
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return;
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}
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var2NodeData[ v ].lit0 = lit1;
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var2NodeData[ v ].lit1 = lit2;
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@ -1043,6 +1043,49 @@ void Solver::uncheckedEnqueue(Lit p, CRef from)
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|________________________________________________________________________________________________@*/
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CRef Solver::propagate()
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{
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if (flushFanout.size() != 0) {
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sort(flushFanout);
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int w = 1;
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for (int r = 1; r < flushFanout.size(); r++) {
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if (flushFanout[w - 1] != flushFanout[r])
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flushFanout[w++] = flushFanout[r];
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}
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flushFanout.shrink_(flushFanout.size() - w);
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for (int i = 0; i < flushFanout.size(); i++) {
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Var v = flushFanout[i];
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var2NodeData[v].sort = 0;
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Lit current = var2Fanout0[v];
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Lit prev = toLit(~0);
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while (current != toLit(~0)) {
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Var found = sign(current) ? var(var2NodeData[var(current)].lit1) : var(var2NodeData[var(current)].lit0);
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if (found == v) {
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prev = current;
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current = var2FanoutN[toInt(current)];
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} else {
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Lit move = current;
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current = var2FanoutN[toInt(current)];
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if (prev == toLit(~0)) {
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var2Fanout0[v] = current;
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} else {
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var2FanoutN[toInt(prev)] = current;
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}
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var2FanoutN[toInt(move)] = var2Fanout0[found];
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var2Fanout0[found] = move;
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var2NodeData[found].sort = 0;
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}
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}
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}
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flushFanout.shrink_(flushFanout.size());
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}
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CRef confl = CRef_Undef;
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int num_props = 0;
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watches.cleanAll();
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@ -1860,6 +1903,8 @@ void Solver::reset()
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var2NodeData .shrink_(var2NodeData .size());
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var2Fanout0 .shrink_(var2Fanout0 .size());
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var2FanoutN .shrink_(var2FanoutN .size());
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flushFanout.shrink_(flushFanout.size());
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//var2FanoutP.clear(false);
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if( CRef_Undef != itpc ){
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itpc = CRef_Undef; // clause allocator has been cleared, do not worry
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@ -396,6 +396,7 @@ protected:
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//vec<Lit> var2FaninLits; // (~0): undefine
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vec<unsigned> var2TravId;
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vec<Lit> var2Fanout0, var2FanoutN;//, var2FanoutP;
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vec<Var> flushFanout;
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CRef itpc; // the interpreted clause of a gate
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void inplace_sort( Var v );
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