mirror of https://github.com/YosysHQ/abc.git
Making MiniLUT work for more than 6 inputs.
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@ -213,7 +213,6 @@ Gia_Man_t * Gia_ManFromMiniLut( Mini_Lut_t * p, Vec_Int_t ** pvCopies )
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Vec_Int_t * vLits = Vec_IntAlloc( 100 );
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int i, k, Fan, iGiaLit, nNodes;
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int LutSize = Abc_MaxInt( 2, Mini_LutSize(p) );
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assert( LutSize <= 6 );
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// get the number of nodes
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nNodes = Mini_LutNodeNum(p);
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// create ABC network
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@ -234,11 +233,12 @@ Gia_Man_t * Gia_ManFromMiniLut( Mini_Lut_t * p, Vec_Int_t ** pvCopies )
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else if ( Mini_LutNodeIsNode( p, i ) )
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{
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unsigned * puTruth = Mini_LutNodeTruth( p, i );
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word Truth = LutSize == 6 ? *(word *)puTruth : ((word)*puTruth << 32) | (word)*puTruth;
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word Truth = ((word)*puTruth << 32) | (word)*puTruth;
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word * pTruth = LutSize < 6 ? &Truth : (word *)puTruth;
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Vec_IntClear( vLits );
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Mini_LutForEachFanin( p, i, Fan, k )
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Vec_IntPush( vLits, Vec_IntEntry(vCopies, Fan) );
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iGiaLit = Dsm_ManTruthToGia( pGia, &Truth, vLits, vCover );
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iGiaLit = Dsm_ManTruthToGia( pGia, pTruth, vLits, vCover );
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}
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else assert( 0 );
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Vec_IntPush( vCopies, iGiaLit );
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@ -301,14 +301,15 @@ Vec_Bit_t * Gia_ManFindComplLuts( Gia_Man_t * pGia )
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Mini_Lut_t * Gia_ManToMiniLut( Gia_Man_t * pGia )
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{
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Mini_Lut_t * p;
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Vec_Wrd_t * vTruths;
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Vec_Bit_t * vMarks;
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Gia_Obj_t * pObj, * pFanin;
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int i, k, iFanin, LutSize, pVars[16];
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word Truth;
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Vec_Int_t * vLeaves = Vec_IntAlloc( 16 );
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int i, k, iFanin, LutSize, nWords, Count = 0, pVars[16];
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word * pTruth;
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assert( Gia_ManHasMapping(pGia) );
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LutSize = Gia_ManLutSizeMax( pGia );
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LutSize = Abc_MaxInt( LutSize, 2 );
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nWords = Abc_Truth6WordNum( LutSize );
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assert( LutSize >= 2 );
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// create the manager
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p = Mini_LutStart( LutSize );
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@ -317,21 +318,39 @@ Mini_Lut_t * Gia_ManToMiniLut( Gia_Man_t * pGia )
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Gia_ManForEachCi( pGia, pObj, i )
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pObj->Value = Mini_LutCreatePi(p);
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// create internal nodes
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vTruths = Vec_WrdStart( Gia_ManObjNum(pGia) );
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vMarks = Gia_ManFindComplLuts( pGia );
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Gia_ObjComputeTruthTableStart( pGia, LutSize );
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Gia_ManForEachLut( pGia, i )
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{
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pObj = Gia_ManObj( pGia, i );
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Gia_LutForEachFaninObj( pGia, i, pFanin, k )
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pVars[k] = pFanin->Value;
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Truth = Gia_LutComputeTruth6( pGia, i, vTruths );
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Truth = Vec_BitEntry(vMarks, i) ? ~Truth : Truth;
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Vec_IntClear( vLeaves );
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Gia_LutForEachFanin( pGia, i, iFanin, k )
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Vec_IntPush( vLeaves, iFanin );
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if ( Vec_IntSize(vLeaves) > 6 )
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{
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int Extra = Vec_IntSize(vLeaves) - 7;
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for ( k = Extra; k >= 0; k-- )
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Vec_IntPush( vLeaves, Vec_IntEntry(vLeaves, k) );
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for ( k = Extra; k >= 0; k-- )
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Vec_IntDrop( vLeaves, k );
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assert( Vec_IntSize(vLeaves) == Gia_ObjLutSize(pGia, i) );
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}
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Gia_ManForEachObjVec( vLeaves, pGia, pFanin, k )
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pVars[k] = pFanin->Value;
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pObj = Gia_ManObj( pGia, i );
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pTruth = Gia_ObjComputeTruthTableCut( pGia, pObj, vLeaves );
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if ( Vec_BitEntry(vMarks, i) )
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Abc_TtNot( pTruth, nWords );
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Vec_IntForEachEntry( vLeaves, iFanin, k )
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if ( Vec_BitEntry(vMarks, iFanin) )
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Truth = Abc_Tt6Flip( Truth, k );
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pObj->Value = Mini_LutCreateNode( p, Gia_ObjLutSize(pGia, i), pVars, (unsigned *)&Truth );
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Abc_TtFlip( pTruth, nWords, k );
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pObj->Value = Mini_LutCreateNode( p, Gia_ObjLutSize(pGia, i), pVars, (unsigned *)pTruth );
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}
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Vec_WrdFree( vTruths );
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Vec_IntFree( vLeaves );
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// create inverter truth table
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Vec_WrdClear( pGia->vTtMemory );
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for ( i = 0; i < nWords; i++ )
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Vec_WrdPush( pGia->vTtMemory, ABC_CONST(0x5555555555555555) );
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pTruth = Vec_WrdArray( pGia->vTtMemory );
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// create primary outputs
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Gia_ManForEachCo( pGia, pObj, i )
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{
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@ -341,16 +360,18 @@ Mini_Lut_t * Gia_ManToMiniLut( Gia_Man_t * pGia )
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pObj->Value = Mini_LutCreatePo( p, Gia_ObjFanin0(pObj)->Value );
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else // add inverter LUT
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{
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word TruthInv = ABC_CONST(0x5555555555555555);
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int Fanin = Gia_ObjFanin0(pObj)->Value;
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int LutInv = Mini_LutCreateNode( p, 1, &Fanin, (unsigned *)&TruthInv );
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int LutInv = Mini_LutCreateNode( p, 1, &Fanin, (unsigned *)pTruth );
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pObj->Value = Mini_LutCreatePo( p, LutInv );
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Count++;
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}
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}
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Vec_BitFree( vMarks );
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Gia_ObjComputeTruthTableStop( pGia );
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// set registers
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Mini_LutSetRegNum( p, Gia_ManRegNum(pGia) );
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//Mini_LutPrintStats( p );
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//printf( "Added %d inverters.\n", Count );
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return p;
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}
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