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Enable command 'pipe' for pipelining.

This commit is contained in:
Alan Mishchenko 2021-09-13 09:44:28 -07:00
parent 2f993e583d
commit c557272241
3 changed files with 15 additions and 15 deletions
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15
src/base/abc/abcLatch.c
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@ -148,7 +148,7 @@ int Abc_NtkRemoveSelfFeedLatches( Abc_Ntk_t * pNtk )
void Abc_NtkLatchPipe( Abc_Ntk_t * pNtk, int nLatches ) void Abc_NtkLatchPipe( Abc_Ntk_t * pNtk, int nLatches )
{ {
Vec_Ptr_t * vNodes; Vec_Ptr_t * vNodes;
Abc_Obj_t * pObj, * pLatch, * pFanin, * pFanout; Abc_Obj_t * pObj, * pFanin, * pFanout;
int i, k, nTotal, nDigits; int i, k, nTotal, nDigits;
if ( nLatches < 1 ) if ( nLatches < 1 )
return; return;
@ -157,18 +157,9 @@ void Abc_NtkLatchPipe( Abc_Ntk_t * pNtk, int nLatches )
vNodes = Vec_PtrAlloc( 100 ); vNodes = Vec_PtrAlloc( 100 );
Abc_NtkForEachPi( pNtk, pObj, i ) Abc_NtkForEachPi( pNtk, pObj, i )
{ {
// remember current fanins of the PI
Abc_NodeCollectFanouts( pObj, vNodes ); Abc_NodeCollectFanouts( pObj, vNodes );
// create the latches for ( pFanin = pObj, k = 0; k < nLatches; k++ )
for ( pFanin = pObj, k = 0; k < nLatches; k++, pFanin = pLatch ) pFanin = Abc_NtkAddLatch( pNtk, pFanin, ABC_INIT_ZERO );
{
pLatch = Abc_NtkCreateLatch( pNtk );
Abc_ObjAddFanin( pLatch, pFanin );
Abc_LatchSetInitDc( pLatch );
// create the name of the new latch
Abc_ObjAssignName( pLatch, Abc_ObjNameDummy("LL", i*nLatches + k, nDigits), NULL );
}
// patch the PI fanouts
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pFanout, k ) Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pFanout, k )
Abc_ObjPatchFanin( pFanout, pObj, pFanin ); Abc_ObjPatchFanin( pFanout, pObj, pFanin );
} }

12
src/base/abci/abc.c
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@ -1039,7 +1039,7 @@ void Abc_Init( Abc_Frame_t * pAbc )
Cmd_CommandAdd( pAbc, "Sequential", "zero", Abc_CommandZero, 1 ); Cmd_CommandAdd( pAbc, "Sequential", "zero", Abc_CommandZero, 1 );
Cmd_CommandAdd( pAbc, "Sequential", "undc", Abc_CommandUndc, 1 ); Cmd_CommandAdd( pAbc, "Sequential", "undc", Abc_CommandUndc, 1 );
Cmd_CommandAdd( pAbc, "Sequential", "onehot", Abc_CommandOneHot, 1 ); Cmd_CommandAdd( pAbc, "Sequential", "onehot", Abc_CommandOneHot, 1 );
// Cmd_CommandAdd( pAbc, "Sequential", "pipe", Abc_CommandPipe, 1 ); Cmd_CommandAdd( pAbc, "Sequential", "pipe", Abc_CommandPipe, 1 );
Cmd_CommandAdd( pAbc, "Sequential", "retime", Abc_CommandRetime, 1 ); Cmd_CommandAdd( pAbc, "Sequential", "retime", Abc_CommandRetime, 1 );
Cmd_CommandAdd( pAbc, "Sequential", "dretime", Abc_CommandDRetime, 1 ); Cmd_CommandAdd( pAbc, "Sequential", "dretime", Abc_CommandDRetime, 1 );
Cmd_CommandAdd( pAbc, "Sequential", "fretime", Abc_CommandFlowRetime, 1 ); Cmd_CommandAdd( pAbc, "Sequential", "fretime", Abc_CommandFlowRetime, 1 );
@ -20530,9 +20530,15 @@ int Abc_CommandPipe( Abc_Frame_t * pAbc, int argc, char ** argv )
return 1; return 1;
} }
if ( Abc_NtkIsComb(pNtk) ) if ( !Abc_NtkIsLogic(pNtk) )
{ {
Abc_Print( 0, "The current network is combinational.\n" ); Abc_Print( 0, "Abc_CommandPipe(): Expecting a logic network (run command \"logic\").\n" );
return 0;
}
if ( !Abc_NtkIsComb(pNtk) )
{
Abc_Print( 0, "Abc_CommandPipe(): Expecting a combinational network.\n" );
return 0; return 0;
} }

3
src/base/abci/abcVerify.c
View File

@ -781,6 +781,8 @@ void Abc_NtkVerifyReportError( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int * pMode
Abc_NtkForEachCi( pNtk1, pNode, i ) Abc_NtkForEachCi( pNtk1, pNode, i )
pNode->pCopy = (Abc_Obj_t *)(ABC_PTRINT_T)i; pNode->pCopy = (Abc_Obj_t *)(ABC_PTRINT_T)i;
// print the model // print the model
if ( Vec_PtrSize(vNodes) )
{
pNode = (Abc_Obj_t *)Vec_PtrEntry( vNodes, 0 ); pNode = (Abc_Obj_t *)Vec_PtrEntry( vNodes, 0 );
if ( Abc_ObjIsCi(pNode) ) if ( Abc_ObjIsCi(pNode) )
{ {
@ -790,6 +792,7 @@ void Abc_NtkVerifyReportError( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int * pMode
printf( " %s=%d", Abc_ObjName(pNode), pModel[(int)(ABC_PTRINT_T)pNode->pCopy] ); printf( " %s=%d", Abc_ObjName(pNode), pModel[(int)(ABC_PTRINT_T)pNode->pCopy] );
} }
} }
}
printf( "\n" ); printf( "\n" );
Vec_PtrFree( vNodes ); Vec_PtrFree( vNodes );
} }