mirror of https://github.com/YosysHQ/abc.git
Enable command 'pipe' for pipelining.
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2f993e583d
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@ -148,7 +148,7 @@ int Abc_NtkRemoveSelfFeedLatches( Abc_Ntk_t * pNtk )
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void Abc_NtkLatchPipe( Abc_Ntk_t * pNtk, int nLatches )
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{
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Vec_Ptr_t * vNodes;
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Abc_Obj_t * pObj, * pLatch, * pFanin, * pFanout;
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Abc_Obj_t * pObj, * pFanin, * pFanout;
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int i, k, nTotal, nDigits;
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if ( nLatches < 1 )
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return;
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@ -157,18 +157,9 @@ void Abc_NtkLatchPipe( Abc_Ntk_t * pNtk, int nLatches )
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vNodes = Vec_PtrAlloc( 100 );
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Abc_NtkForEachPi( pNtk, pObj, i )
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{
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// remember current fanins of the PI
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Abc_NodeCollectFanouts( pObj, vNodes );
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// create the latches
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for ( pFanin = pObj, k = 0; k < nLatches; k++, pFanin = pLatch )
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{
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pLatch = Abc_NtkCreateLatch( pNtk );
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Abc_ObjAddFanin( pLatch, pFanin );
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Abc_LatchSetInitDc( pLatch );
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// create the name of the new latch
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Abc_ObjAssignName( pLatch, Abc_ObjNameDummy("LL", i*nLatches + k, nDigits), NULL );
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}
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// patch the PI fanouts
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for ( pFanin = pObj, k = 0; k < nLatches; k++ )
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pFanin = Abc_NtkAddLatch( pNtk, pFanin, ABC_INIT_ZERO );
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Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pFanout, k )
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Abc_ObjPatchFanin( pFanout, pObj, pFanin );
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}
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@ -1039,7 +1039,7 @@ void Abc_Init( Abc_Frame_t * pAbc )
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Cmd_CommandAdd( pAbc, "Sequential", "zero", Abc_CommandZero, 1 );
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Cmd_CommandAdd( pAbc, "Sequential", "undc", Abc_CommandUndc, 1 );
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Cmd_CommandAdd( pAbc, "Sequential", "onehot", Abc_CommandOneHot, 1 );
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// Cmd_CommandAdd( pAbc, "Sequential", "pipe", Abc_CommandPipe, 1 );
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Cmd_CommandAdd( pAbc, "Sequential", "pipe", Abc_CommandPipe, 1 );
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Cmd_CommandAdd( pAbc, "Sequential", "retime", Abc_CommandRetime, 1 );
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Cmd_CommandAdd( pAbc, "Sequential", "dretime", Abc_CommandDRetime, 1 );
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Cmd_CommandAdd( pAbc, "Sequential", "fretime", Abc_CommandFlowRetime, 1 );
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@ -20530,9 +20530,15 @@ int Abc_CommandPipe( Abc_Frame_t * pAbc, int argc, char ** argv )
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return 1;
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}
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if ( Abc_NtkIsComb(pNtk) )
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if ( !Abc_NtkIsLogic(pNtk) )
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{
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Abc_Print( 0, "The current network is combinational.\n" );
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Abc_Print( 0, "Abc_CommandPipe(): Expecting a logic network (run command \"logic\").\n" );
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return 0;
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}
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if ( !Abc_NtkIsComb(pNtk) )
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{
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Abc_Print( 0, "Abc_CommandPipe(): Expecting a combinational network.\n" );
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return 0;
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}
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@ -781,6 +781,8 @@ void Abc_NtkVerifyReportError( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int * pMode
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Abc_NtkForEachCi( pNtk1, pNode, i )
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pNode->pCopy = (Abc_Obj_t *)(ABC_PTRINT_T)i;
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// print the model
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if ( Vec_PtrSize(vNodes) )
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{
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pNode = (Abc_Obj_t *)Vec_PtrEntry( vNodes, 0 );
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if ( Abc_ObjIsCi(pNode) )
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{
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@ -790,6 +792,7 @@ void Abc_NtkVerifyReportError( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int * pMode
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printf( " %s=%d", Abc_ObjName(pNode), pModel[(int)(ABC_PTRINT_T)pNode->pCopy] );
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}
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}
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}
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printf( "\n" );
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Vec_PtrFree( vNodes );
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}
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