mirror of https://github.com/YosysHQ/abc.git
Fixing a bug and adding verification of minimized counter-example.
This commit is contained in:
Alan Mishchenko
parent
f7c7cb5c65
commit
abde9fe948
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@ -407,7 +407,7 @@ Aig_Man_t * Saig_ManCbaUnrollWithCex( Aig_Man_t * pAig, Abc_Cex_t * pCex, int nI
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int i, f;
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// sanity checks
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assert( Saig_ManPiNum(pAig) == pCex->nPis );
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assert( Saig_ManRegNum(pAig) == pCex->nRegs );
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// assert( Saig_ManRegNum(pAig) == pCex->nRegs );
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assert( pCex->iPo >= 0 && pCex->iPo < Saig_ManPoNum(pAig) );
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// map PIs of the unrolled frames into PIs of the original design
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@ -428,17 +428,23 @@ Aig_Man_t * Saig_ManCbaUnrollWithCex( Aig_Man_t * pAig, Abc_Cex_t * pCex, int nI
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Saig_ManCbaUnrollCollect_rec( pAig, pObj,
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Vec_VecEntryInt(vFrameObjs, f),
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(Vec_Int_t *)(f ? Vec_VecEntry(vFrameCos, f-1) : NULL) );
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//printf( "%d ", Vec_VecLevelSize(vFrameCos, f) );
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}
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//printf( "\n" );
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// derive unrolled timeframes
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pFrames = Aig_ManStart( 10000 );
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pFrames->pName = Abc_UtilStrsav( pAig->pName );
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pFrames->pSpec = Abc_UtilStrsav( pAig->pSpec );
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// initialize the flops
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Saig_ManForEachLo( pAig, pObj, i )
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pObj->pData = Aig_NotCond( Aig_ManConst1(pFrames), !Abc_InfoHasBit(pCex->pData, i) );
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if ( Saig_ManRegNum(pAig) == pCex->nRegs )
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{
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Saig_ManForEachLo( pAig, pObj, i )
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pObj->pData = Aig_NotCond( Aig_ManConst1(pFrames), !Abc_InfoHasBit(pCex->pData, i) );
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}
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else // this is the case when synthesis was applied, assume all-0 init state
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{
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Saig_ManForEachLo( pAig, pObj, i )
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pObj->pData = Aig_NotCond( Aig_ManConst1(pFrames), 1 );
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}
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// iterate through the frames
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for ( f = 0; f <= pCex->iFrame; f++ )
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{
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@ -580,6 +586,123 @@ void Saig_ManCbaShrink( Saig_ManCba_t * p )
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Aig_ManStop( pManNew );
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}
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static inline void Saig_ObjCexMinSet0( Aig_Obj_t * pObj ) { pObj->fMarkA = 1; pObj->fMarkB = 0; }
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static inline void Saig_ObjCexMinSet1( Aig_Obj_t * pObj ) { pObj->fMarkA = 0; pObj->fMarkB = 1; }
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static inline void Saig_ObjCexMinSetX( Aig_Obj_t * pObj ) { pObj->fMarkA = 1; pObj->fMarkB = 1; }
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static inline int Saig_ObjCexMinGet0( Aig_Obj_t * pObj ) { return pObj->fMarkA && !pObj->fMarkB; }
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static inline int Saig_ObjCexMinGet1( Aig_Obj_t * pObj ) { return !pObj->fMarkA && pObj->fMarkB; }
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static inline int Saig_ObjCexMinGetX( Aig_Obj_t * pObj ) { return pObj->fMarkA && pObj->fMarkB; }
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static inline int Saig_ObjCexMinGet0Fanin0( Aig_Obj_t * pObj ) { return (Saig_ObjCexMinGet1(Aig_ObjFanin0(pObj)) && Aig_ObjFaninC0(pObj)) || (Saig_ObjCexMinGet0(Aig_ObjFanin0(pObj)) && !Aig_ObjFaninC0(pObj)); }
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static inline int Saig_ObjCexMinGet1Fanin0( Aig_Obj_t * pObj ) { return (Saig_ObjCexMinGet0(Aig_ObjFanin0(pObj)) && Aig_ObjFaninC0(pObj)) || (Saig_ObjCexMinGet1(Aig_ObjFanin0(pObj)) && !Aig_ObjFaninC0(pObj)); }
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static inline int Saig_ObjCexMinGet0Fanin1( Aig_Obj_t * pObj ) { return (Saig_ObjCexMinGet1(Aig_ObjFanin1(pObj)) && Aig_ObjFaninC1(pObj)) || (Saig_ObjCexMinGet0(Aig_ObjFanin1(pObj)) && !Aig_ObjFaninC1(pObj)); }
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static inline int Saig_ObjCexMinGet1Fanin1( Aig_Obj_t * pObj ) { return (Saig_ObjCexMinGet0(Aig_ObjFanin1(pObj)) && Aig_ObjFaninC1(pObj)) || (Saig_ObjCexMinGet1(Aig_ObjFanin1(pObj)) && !Aig_ObjFaninC1(pObj)); }
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static inline void Saig_ObjCexMinSim( Aig_Obj_t * pObj )
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{
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if ( Aig_ObjIsAnd(pObj) )
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{
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if ( Saig_ObjCexMinGet0Fanin0(pObj) || Saig_ObjCexMinGet0Fanin1(pObj) )
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Saig_ObjCexMinSet0( pObj );
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else if ( Saig_ObjCexMinGet1Fanin0(pObj) && Saig_ObjCexMinGet1Fanin1(pObj) )
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Saig_ObjCexMinSet1( pObj );
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else
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Saig_ObjCexMinSetX( pObj );
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}
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else if ( Aig_ObjIsPo(pObj) )
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{
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if ( Saig_ObjCexMinGet0Fanin0(pObj) )
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Saig_ObjCexMinSet0( pObj );
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else if ( Saig_ObjCexMinGet1Fanin0(pObj) )
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Saig_ObjCexMinSet1( pObj );
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else
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Saig_ObjCexMinSetX( pObj );
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}
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else assert( 0 );
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}
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static inline void Saig_ObjCexMinPrint( Aig_Obj_t * pObj )
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{
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if ( Saig_ObjCexMinGet0(pObj) )
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printf( "0" );
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else if ( Saig_ObjCexMinGet1(pObj) )
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printf( "1" );
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else if ( Saig_ObjCexMinGetX(pObj) )
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printf( "X" );
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Saig_ManCexVerifyUsingTernary( Aig_Man_t * pAig, Abc_Cex_t * pCex, Abc_Cex_t * pCare )
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{
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Aig_Obj_t * pObj, * pObjRi, * pObjRo;
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int i, f, iBit = 0;
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assert( pCex->iFrame == pCare->iFrame );
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assert( pCex->nBits == pCare->nBits );
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assert( pCex->iPo < Saig_ManPoNum(pAig) );
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Saig_ObjCexMinSet1( Aig_ManConst1(pAig) );
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// set flops to the init state
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Saig_ManForEachLo( pAig, pObj, i )
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{
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assert( !Abc_InfoHasBit(pCex->pData, iBit) );
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assert( !Abc_InfoHasBit(pCare->pData, iBit) );
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// if ( Abc_InfoHasBit(pCare->pData, iBit++) )
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Saig_ObjCexMinSet0( pObj );
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// else
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// Saig_ObjCexMinSetX( pObj );
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}
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iBit = pCex->nRegs;
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for ( f = 0; f <= pCex->iFrame; f++ )
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{
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// init inputs
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Saig_ManForEachPi( pAig, pObj, i )
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{
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if ( Abc_InfoHasBit(pCare->pData, iBit++) )
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{
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if ( Abc_InfoHasBit(pCex->pData, iBit-1) )
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Saig_ObjCexMinSet1( pObj );
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else
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Saig_ObjCexMinSet0( pObj );
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}
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else
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Saig_ObjCexMinSetX( pObj );
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}
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// simulate internal nodes
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Aig_ManForEachNode( pAig, pObj, i )
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Saig_ObjCexMinSim( pObj );
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// simulate COs
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Aig_ManForEachPo( pAig, pObj, i )
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Saig_ObjCexMinSim( pObj );
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/*
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Aig_ManForEachObj( pAig, pObj, i )
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{
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Aig_ObjPrint(pAig, pObj);
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printf( " Value = " );
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Saig_ObjCexMinPrint( pObj );
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printf( "\n" );
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}
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*/
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// transfer
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Saig_ManForEachLiLo( pAig, pObjRi, pObjRo, i )
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pObjRo->fMarkA = pObjRi->fMarkA,
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pObjRo->fMarkB = pObjRi->fMarkB;
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}
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assert( iBit == pCex->nBits );
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return Saig_ObjCexMinGet1( Aig_ManPo( pAig, pCex->iPo ) );
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}
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/**Function*************************************************************
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Synopsis [SAT-based refinement of the counter-example.]
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@ -638,7 +761,12 @@ if ( fVerbose )
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printf( "Care " );
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Abc_CexPrintStats( pCare );
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}
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// verify the reduced counter-example using ternary simulation
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if ( !Saig_ManCexVerifyUsingTernary( pAig, pCex, pCare ) )
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printf( "Saig_ManCbaFindCexCareBits(): Counter-example verification has failed!!!\n" );
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else if ( fVerbose )
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printf( "Saig_ManCbaFindCexCareBits(): Counter-example verification is successful.\n" );
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Aig_ManCleanMarkAB( pAig );
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return pCare;
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}
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