mirror of https://github.com/YosysHQ/abc.git
Renaming Cba into Bac.
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@ -64,7 +64,7 @@ static void Psr_ManWriteVerilogSignal( FILE * pFile, Psr_Ntk_t * p, int Sig )
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Psr_ManWriteVerilogConcat( pFile, p, Value );
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else assert( 0 );
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}
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static void Psr_ManWriteVerilogArray( FILE * pFile, Psr_Ntk_t * p, Vec_Int_t * vSigs, int Start, int Stop, int fOdd )
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void Psr_ManWriteVerilogArray( FILE * pFile, Psr_Ntk_t * p, Vec_Int_t * vSigs, int Start, int Stop, int fOdd )
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{
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int i, Sig;
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assert( Vec_IntSize(vSigs) > 0 );
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