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support primitive gates with names in Verilog netlist

This commit is contained in:
tklam 2025-05-12 10:20:13 -04:00
parent c85f007f75
commit 9545b79e0e
1 changed files with 18 additions and 4 deletions
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22
src/base/ver/verCore.c
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@ -1339,12 +1339,26 @@ int Ver_ParseGateStandard( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Ver_GateType_t Ga
return 0; return 0;
Ver_StreamMove( p ); Ver_StreamMove( p );
// this is gate name - throw it away // assume there is a gate name if the current char is not '(', e.g. xor g1 (z, a, b);
if ( Ver_StreamPopChar(p) != '(' ) if ( Ver_StreamPopChar(p) != '(' )
{ {
sprintf( pMan->sError, "Cannot parse a standard gate (expected opening parenthesis)." ); // this is gate name - throw it away
Ver_ParsePrintErrorMessage( pMan ); pWord = Ver_ParseGetName( pMan );
return 0; if (pWord == NULL)
{
sprintf( pMan->sError, "Cannot parse a standard gate (expected a name before an opening parenthesis)." );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
else
{
if ( Ver_StreamPopChar(p) != '(' )
{
sprintf( pMan->sError, "Cannot parse a standard gate (expected opening parenthesis)." );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
}
} }
Ver_ParseSkipComments( pMan ); Ver_ParseSkipComments( pMan );