mirror of https://github.com/YosysHQ/abc.git
Trying to add BMC to random simulation.
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@ -168,6 +168,7 @@ extern Aig_Man_t * Saig_ManCreateEquivMiter( Aig_Man_t * pAig, Vec_Int_t *
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extern Aig_Man_t * Saig_ManDupAbstraction( Aig_Man_t * pAig, Vec_Int_t * vFlops );
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extern int Saig_ManVerifyCex( Aig_Man_t * pAig, Abc_Cex_t * p );
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extern int Saig_ManFindFailedPoCex( Aig_Man_t * pAig, Abc_Cex_t * p );
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extern Aig_Man_t * Saig_ManDupWithPhase( Aig_Man_t * pAig, Vec_Int_t * vInit );
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/*=== saigHaig.c ==========================================================*/
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extern Aig_Man_t * Saig_ManHaigRecord( Aig_Man_t * p, int nIters, int nSteps, int fRetimingOnly, int fAddBugs, int fUseCnf, int fVerbose );
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/*=== saigInd.c ==========================================================*/
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@ -350,6 +350,50 @@ int Saig_ManFindFailedPoCex( Aig_Man_t * pAig, Abc_Cex_t * p )
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return RetValue;
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}
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/**Function*************************************************************
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Synopsis [Duplicates while ORing the POs of sequential circuit.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Aig_Man_t * Saig_ManDupWithPhase( Aig_Man_t * pAig, Vec_Int_t * vInit )
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{
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Aig_Man_t * pAigNew;
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Aig_Obj_t * pObj;
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int i;
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assert( Aig_ManRegNum(pAig) <= Vec_IntSize(vInit) );
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// start the new manager
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pAigNew = Aig_ManStart( Aig_ManNodeNum(pAig) );
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pAigNew->pName = Aig_UtilStrsav( pAig->pName );
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pAigNew->nConstrs = pAig->nConstrs;
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// map the constant node
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Aig_ManConst1(pAig)->pData = Aig_ManConst1( pAigNew );
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// create variables for PIs
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Aig_ManForEachPi( pAig, pObj, i )
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pObj->pData = Aig_ObjCreatePi( pAigNew );
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// update the flop variables
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Saig_ManForEachLo( pAig, pObj, i )
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pObj->pData = Aig_NotCond( pObj->pData, Vec_IntEntry(vInit, i) );
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// add internal nodes of this frame
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Aig_ManForEachNode( pAig, pObj, i )
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pObj->pData = Aig_And( pAigNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
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// transfer to register outputs
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Saig_ManForEachPo( pAig, pObj, i )
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Aig_ObjCreatePo( pAigNew, Aig_ObjChild0Copy(pObj) );
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// update the flop variables
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Saig_ManForEachLi( pAig, pObj, i )
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Aig_ObjCreatePo( pAigNew, Aig_NotCond(Aig_ObjChild0Copy(pObj), Vec_IntEntry(vInit, i)) );
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// finalize
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Aig_ManCleanup( pAigNew );
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Aig_ManSetRegNum( pAigNew, Aig_ManRegNum(pAig) );
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return pAigNew;
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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@ -892,11 +892,13 @@ int Ssw_RarCheckTrivial( Aig_Man_t * pAig, int fVerbose )
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***********************************************************************/
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int Ssw_RarSimulate( Aig_Man_t * pAig, int nFrames, int nWords, int nBinSize, int nRounds, int nRandSeed, int TimeOut, int fVerbose )
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{
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int fTryBmc = 1;
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int fMiter = 1;
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Ssw_RarMan_t * p;
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int r, f, clk, clkTotal = clock();
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int nTimeToStop = time(NULL) + TimeOut;
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int RetValue = -1;
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int iFrameFail = -1;
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assert( Aig_ManRegNum(pAig) > 0 );
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assert( Aig_ManConstrNum(pAig) == 0 );
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// consider the case of empty AIG
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@ -919,6 +921,14 @@ int Ssw_RarSimulate( Aig_Man_t * pAig, int nFrames, int nWords, int nBinSize, in
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for ( r = 0; r < nRounds; r++ )
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{
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clk = clock();
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if ( fTryBmc )
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{
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Aig_Man_t * pNewAig = Saig_ManDupWithPhase( pAig, p->vInits );
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Saig_BmcPerform( pNewAig, 0, 100, 2000, 3, 0, 0, 1 /*fVerbose*/, 0, &iFrameFail );
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// if ( pNewAig->pSeqModel != NULL )
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// printf( "BMC has found a counter-example in frame %d.\n", iFrameFail );
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Aig_ManStop( pNewAig );
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}
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// simulate
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for ( f = 0; f < nFrames; f++ )
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{
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