luke
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abc
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Version abc70110

This commit is contained in:
Alan Mishchenko 2007-01-10 08:01:00 -08:00
parent be6a484a99
commit 8dfe404863
98 changed files with 6813 additions and 2417 deletions
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2
Makefile
View File

@ -22,7 +22,7 @@ OPTFLAGS := -g -O
CFLAGS += -Wall -Wno-unused-function $(OPTFLAGS) $(patsubst %, -I%, $(MODULES))
CXXFLAGS += $(CFLAGS)
LIBS := -ldl -rdynamic
LIBS := -ldl -rdynamic -lreadline -ltermcap
SRC :=
GARBAGE := core core.* *.stackdump ./tags $(PROG)

28
abc.dsp
View File

@ -206,6 +206,10 @@ SOURCE=.\src\base\abci\abcDebug.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcDress.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcDsd.c
# End Source File
# Begin Source File
@ -406,10 +410,6 @@ SOURCE=.\src\base\io\ioInt.h
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioRead.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioReadAiger.c
# End Source File
# Begin Source File
@ -426,6 +426,14 @@ SOURCE=.\src\base\io\ioReadBlif.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioReadBlifAig.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioReadBlifMv.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioReadEdif.c
# End Source File
# Begin Source File
@ -458,6 +466,10 @@ SOURCE=.\src\base\io\ioWriteBlif.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioWriteBlifMv.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioWriteCnf.c
# End Source File
# Begin Source File
@ -545,6 +557,10 @@ SOURCE=.\src\base\ver\verParse.c
SOURCE=.\src\base\ver\verStream.c
# End Source File
# End Group
# Begin Group "func"
# PROP Default_Filter ""
# End Group
# End Group
# Begin Group "aig"
@ -1038,6 +1054,10 @@ SOURCE=.\src\bdd\parse\parseCore.c
# End Source File
# Begin Source File
SOURCE=.\src\bdd\parse\parseEqn.c
# End Source File
# Begin Source File
SOURCE=.\src\bdd\parse\parseInt.h
# End Source File
# Begin Source File

8
abc.rc
View File

@ -51,6 +51,7 @@ alias rl read_blif
alias rb read_bench
alias ret retime
alias rp read_pla
alias rt read_truth
alias rv read_ver
alias rvl read_verlib
alias rsup read_super mcnc5_old.super
@ -73,16 +74,15 @@ alias tr0 trace_start
alias tr1 trace_check
alias trt "r c.blif; st; tr0; b; tr1"
alias u undo
alias w write
alias wb write_blif
alias wl write_blif
alias wp write_pla
alias wv write_verilog
# standard scripts
alias opt "b; ren; b"
alias share "b; ren; fx; b"
alias sharem "b; ren -m; fx; b"
alias sharedsd "b; ren; dsd -g; sw; fx; b"
alias share "b; ren -s; fx; b"
alias sharedsd "b; ren -b; dsd -g; sw; fx; b"
alias resyn "b; rw; rwz; b; rwz; b"
alias resyn2 "b; rw; rf; b; rw; rwz; b; rfz; rwz; b"
alias resyn2a "b; rw; b; rw; rwz; b; rwz; b"

636
abclib.dsp
View File

@ -41,7 +41,7 @@ RSC=rc.exe
# PROP Intermediate_Dir "abclib\ReleaseLib"
# PROP Target_Dir ""
# ADD BASE CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_MBCS" /D "_LIB" /YX /FD /c
# ADD CPP /nologo /W3 /GX /O2 /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\aig" /I "src\sat\asat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /I "src\misc\espresso" /D "WIN32" /D "NDEBUG" /D "_MBCS" /D "_LIB" /D "__STDC__" /D "HAVE_ASSERT_H" /FR /YX /FD /c
# ADD CPP /nologo /W3 /GX /O2 /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\bsat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\opt\kit" /I "src\map\fpga" /I "src\map\if" /I "src\map\mapper" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /I "src\misc\espresso" /I "src\misc\nm" /I "src\misc\hash" /I "src\aig\ivy" /I "src\aig\hop" /I "src\aig\rwt" /I "src\aig\deco" /I "src\aig\mem" /I "src\temp\esop" /D "WIN32" /D "NDEBUG" /D "_MBCS" /D "_LIB" /D "__STDC__" /D "HAVE_ASSERT_H" /FR /YX /FD /c
# ADD BASE RSC /l 0x409 /d "NDEBUG"
# ADD RSC /l 0x409 /d "NDEBUG"
BSC32=bscmake.exe
@ -64,7 +64,7 @@ LIB32=link.exe -lib
# PROP Intermediate_Dir "abclib\DebugLib"
# PROP Target_Dir ""
# ADD BASE CPP /nologo /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_MBCS" /D "_LIB" /YX /FD /GZ /c
# ADD CPP /nologo /W3 /Gm /GX /ZI /Od /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\aig" /I "src\sat\asat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /I "src\misc\espresso" /D "WIN32" /D "_DEBUG" /D "_MBCS" /D "_LIB" /D "__STDC__" /D "HAVE_ASSERT_H" /FR /YX /FD /GZ /c
# ADD CPP /nologo /W3 /Gm /GX /ZI /Od /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\bsat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\opt\kit" /I "src\map\fpga" /I "src\map\if" /I "src\map\mapper" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /I "src\misc\espresso" /I "src\misc\nm" /I "src\misc\hash" /I "src\aig\ivy" /I "src\aig\hop" /I "src\aig\rwt" /I "src\aig\deco" /I "src\aig\mem" /I "src\temp\esop" /D "WIN32" /D "_DEBUG" /D "_MBCS" /D "_LIB" /D "__STDC__" /D "HAVE_ASSERT_H" /FR /YX /FD /GZ /c
# ADD BASE RSC /l 0x409 /d "_DEBUG"
# ADD RSC /l 0x409 /d "_DEBUG"
BSC32=bscmake.exe
@ -123,6 +123,10 @@ SOURCE=.\src\base\abc\abcLatch.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abc\abcLib.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abc\abcMinBase.c
# End Source File
# Begin Source File
@ -179,7 +183,15 @@ SOURCE=.\src\base\abci\abcBalance.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcCollapse.c
SOURCE=.\src\base\abci\abcBmc.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcClpBdd.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcClpSop.c
# End Source File
# Begin Source File
@ -187,6 +199,14 @@ SOURCE=.\src\base\abci\abcCut.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcDebug.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcDress.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcDsd.c
# End Source File
# Begin Source File
@ -195,10 +215,18 @@ SOURCE=.\src\base\abci\abcEspresso.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcExtract.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcFpga.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcFpgaFast.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcFraig.c
# End Source File
# Begin Source File
@ -207,15 +235,39 @@ SOURCE=.\src\base\abci\abcFxu.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcGen.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcIf.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcIvy.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcLut.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcMap.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcMini.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcMiter.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcNewAig.c
SOURCE=.\src\base\abci\abcMulti.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcMv.c
# End Source File
# Begin Source File
@ -223,7 +275,7 @@ SOURCE=.\src\base\abci\abcNtbdd.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcPga.c
SOURCE=.\src\base\abci\abcOrder.c
# End Source File
# Begin Source File
@ -247,10 +299,26 @@ SOURCE=.\src\base\abci\abcRenode.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcReorder.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcRestruct.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcResub.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcRewrite.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcRr.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcSat.c
# End Source File
# Begin Source File
@ -279,79 +347,11 @@ SOURCE=.\src\base\abci\abcUnreach.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcVanEijk.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcVanImp.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcVerify.c
# End Source File
# End Group
# Begin Group "seq"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\base\seq\seq.h
# End Source File
# Begin Source File
SOURCE=.\src\base\seq\seqAigCore.c
# End Source File
# Begin Source File
SOURCE=.\src\base\seq\seqAigIter.c
# End Source File
# Begin Source File
SOURCE=.\src\base\seq\seqCreate.c
# End Source File
# Begin Source File
SOURCE=.\src\base\seq\seqFpgaCore.c
# End Source File
# Begin Source File
SOURCE=.\src\base\seq\seqFpgaIter.c
# End Source File
# Begin Source File
SOURCE=.\src\base\seq\seqInt.h
# End Source File
# Begin Source File
SOURCE=.\src\base\seq\seqLatch.c
# End Source File
# Begin Source File
SOURCE=.\src\base\seq\seqMan.c
# End Source File
# Begin Source File
SOURCE=.\src\base\seq\seqMapCore.c
# End Source File
# Begin Source File
SOURCE=.\src\base\seq\seqMapIter.c
# End Source File
# Begin Source File
SOURCE=.\src\base\seq\seqRetCore.c
# End Source File
# Begin Source File
SOURCE=.\src\base\seq\seqRetIter.c
# End Source File
# Begin Source File
SOURCE=.\src\base\seq\seqShare.c
# End Source File
# Begin Source File
SOURCE=.\src\base\seq\seqUtil.c
SOURCE=.\src\base\abci\abcXsim.c
# End Source File
# End Group
# Begin Group "cmd"
@ -407,7 +407,7 @@ SOURCE=.\src\base\io\ioInt.h
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioRead.c
SOURCE=.\src\base\io\ioReadAiger.c
# End Source File
# Begin Source File
@ -423,6 +423,10 @@ SOURCE=.\src\base\io\ioReadBlif.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioReadBlifAig.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioReadEdif.c
# End Source File
# Begin Source File
@ -435,11 +439,11 @@ SOURCE=.\src\base\io\ioReadPla.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioReadVerilog.c
SOURCE=.\src\base\io\ioUtil.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioUtil.c
SOURCE=.\src\base\io\ioWriteAiger.c
# End Source File
# Begin Source File
@ -479,7 +483,11 @@ SOURCE=.\src\base\io\ioWritePla.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioWriteVerilog.c
SOURCE=.\src\base\io\ioWriteVer.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioWriteVerAux.c
# End Source File
# End Group
# Begin Group "main"
@ -514,6 +522,34 @@ SOURCE=.\src\base\main\mainInt.h
SOURCE=.\src\base\main\mainUtils.c
# End Source File
# End Group
# Begin Group "ver"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\base\ver\ver.h
# End Source File
# Begin Source File
SOURCE=.\src\base\ver\verCore.c
# End Source File
# Begin Source File
SOURCE=.\src\base\ver\verFormula.c
# End Source File
# Begin Source File
SOURCE=.\src\base\ver\verParse.c
# End Source File
# Begin Source File
SOURCE=.\src\base\ver\verStream.c
# End Source File
# Begin Source File
SOURCE=.\src\base\ver\verWords.c
# End Source File
# End Group
# End Group
# Begin Group "bdd"
@ -819,6 +855,10 @@ SOURCE=.\src\bdd\parse\parseCore.c
# End Source File
# Begin Source File
SOURCE=.\src\bdd\parse\parseEqn.c
# End Source File
# Begin Source File
SOURCE=.\src\bdd\parse\parseInt.h
# End Source File
# Begin Source File
@ -923,6 +963,10 @@ SOURCE=.\src\sat\asat\asatmem.h
# End Source File
# Begin Source File
SOURCE=.\src\sat\asat\jfront.c
# End Source File
# Begin Source File
SOURCE=.\src\sat\asat\solver.c
# End Source File
# Begin Source File
@ -963,7 +1007,7 @@ SOURCE=.\src\sat\msat\msatMem.c
# End Source File
# Begin Source File
SOURCE=.\src\sat\msat\msatOrderJ.c
SOURCE=.\src\sat\msat\msatOrderH.c
# End Source File
# Begin Source File
@ -1015,6 +1059,10 @@ SOURCE=.\src\sat\fraig\fraigCanon.c
# End Source File
# Begin Source File
SOURCE=.\src\sat\fraig\fraigChoice.c
# End Source File
# Begin Source File
SOURCE=.\src\sat\fraig\fraigFanout.c
# End Source File
# Begin Source File
@ -1070,6 +1118,34 @@ SOURCE=.\src\sat\csat\csat_apis.c
SOURCE=.\src\sat\csat\csat_apis.h
# End Source File
# End Group
# Begin Group "bsat"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\sat\bsat\satMem.c
# End Source File
# Begin Source File
SOURCE=.\src\sat\bsat\satMem.h
# End Source File
# Begin Source File
SOURCE=.\src\sat\bsat\satSolver.c
# End Source File
# Begin Source File
SOURCE=.\src\sat\bsat\satSolver.h
# End Source File
# Begin Source File
SOURCE=.\src\sat\bsat\satUtil.c
# End Source File
# Begin Source File
SOURCE=.\src\sat\bsat\satVec.h
# End Source File
# End Group
# End Group
# Begin Group "opt"
@ -1167,6 +1243,10 @@ SOURCE=.\src\opt\rwr\rwrPrint.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\rwr\rwrTemp.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\rwr\rwrUtil.c
# End Source File
# End Group
@ -1187,6 +1267,10 @@ SOURCE=.\src\opt\cut\cutCut.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\cut\cutExpand.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\cut\cutInt.h
# End Source File
# Begin Source File
@ -1211,6 +1295,10 @@ SOURCE=.\src\opt\cut\cutOracle.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\cut\cutPre22.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\cut\cutSeq.c
# End Source File
# Begin Source File
@ -1294,6 +1382,78 @@ SOURCE=.\src\opt\sim\simSymStr.c
SOURCE=.\src\opt\sim\simUtils.c
# End Source File
# End Group
# Begin Group "ret"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\opt\ret\retArea.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\ret\retCore.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\ret\retDelay.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\ret\retFlow.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\ret\retIncrem.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\ret\retInit.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\ret\retInt.h
# End Source File
# Begin Source File
SOURCE=.\src\opt\ret\retLvalue.c
# End Source File
# End Group
# Begin Group "kit"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\opt\kit\kit.h
# End Source File
# Begin Source File
SOURCE=.\src\opt\kit\kitBdd.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\kit\kitFactor.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\kit\kitGraph.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\kit\kitHop.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\kit\kitIsop.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\kit\kitSop.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\kit\kitTruth.c
# End Source File
# End Group
# End Group
# Begin Group "map"
@ -1506,32 +1666,52 @@ SOURCE=.\src\map\super\superInt.h
SOURCE=.\src\map\super\superWrite.c
# End Source File
# End Group
# Begin Group "pga"
# Begin Group "if"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\map\pga\pga.h
SOURCE=.\src\map\if\if.h
# End Source File
# Begin Source File
SOURCE=.\src\map\pga\pgaCore.c
SOURCE=.\src\map\if\ifCore.c
# End Source File
# Begin Source File
SOURCE=.\src\map\pga\pgaInt.h
SOURCE=.\src\map\if\ifCut.c
# End Source File
# Begin Source File
SOURCE=.\src\map\pga\pgaMan.c
SOURCE=.\src\map\if\ifMan.c
# End Source File
# Begin Source File
SOURCE=.\src\map\pga\pgaMatch.c
SOURCE=.\src\map\if\ifMap.c
# End Source File
# Begin Source File
SOURCE=.\src\map\pga\pgaUtil.c
SOURCE=.\src\map\if\ifPrepro.c
# End Source File
# Begin Source File
SOURCE=.\src\map\if\ifReduce.c
# End Source File
# Begin Source File
SOURCE=.\src\map\if\ifSeq.c
# End Source File
# Begin Source File
SOURCE=.\src\map\if\ifTime.c
# End Source File
# Begin Source File
SOURCE=.\src\map\if\ifTruth.c
# End Source File
# Begin Source File
SOURCE=.\src\map\if\ifUtil.c
# End Source File
# End Group
# End Group
@ -1595,6 +1775,10 @@ SOURCE=.\src\misc\extra\extraUtilReader.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\extra\extraUtilTruth.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\extra\extraUtilUtil.c
# End Source File
# End Group
@ -1623,51 +1807,7 @@ SOURCE=.\src\misc\st\stmm.h
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\misc\util\cpu_stats.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\util\cpu_time.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\util\datalimit.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\util\getopt.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\util\leaks.h
# End Source File
# Begin Source File
SOURCE=.\src\misc\util\pathsearch.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\util\prtime.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\util\safe_mem.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\util\stdlib_hack.h
# End Source File
# Begin Source File
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SOURCE=.\src\misc\util\util_hack.h
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@ -1751,7 +1891,11 @@ SOURCE=.\src\misc\vec\vec.h
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SOURCE=.\src\misc\vec\vecAtt.h
# End Source File
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@ -1954,6 +2098,234 @@ SOURCE=.\src\misc\espresso\util_old.h
SOURCE=.\src\misc\espresso\verify.c
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27
regtest.script
View File

@ -1,11 +1,18 @@
r examples/apex4.pla; resyn; sharem; fpga; cec; ps; clp; share; resyn; map; cec; ps
r examples/C2670.blif; resyn; fpga; cec; ps; u; map; cec; ps
r examples/frg2.blif; dsd; muxes; cec; clp; share; resyn; map; cec; ps
r examples/pj1.blif; resyn; fpga; cec; ps; u; map; cec; ps
r examples/s38584.bench; resyn; fpga; cec; ps; u; map; cec; ps
r examples/s444.blif; b; esd -v; dsd; cec; ps
r examples/i10.blif; fpga; cec; ps; u; map; cec; ps
r examples/i10.blif; choice; fpga; cec; ps; u; map; cec; ps
#r examples/s6669.blif; fpga; ps; sec; u; sfpga; ps; sec; u; fpga; ret; ps; sec
#r examples/s5378.blif; map -s; ps; sec; u; smap; ps; sec; u; map; ret; ps; sec
r examples/apex4.pla; resyn; if; cec; ps; clp; resyn; map; cec; ps
r examples/C2670.blif; st; w 1.aig; cec 1.aig
r examples/C2670.blif; st; short_names; w 1.bench; cec 1.bench
r examples/C2670.blif; st; short_names; ren -s; w 1.eqn; cec 1.eqn
r examples/C2670.blif; resyn2; if -K 8; cec; ps; u; map; cec; ps
r examples/frg2.blif; dsd; muxes; cec; ps; clp; share; resyn; map; cec; ps
r examples/frg2.blif; bdd; muxes; cec; ps; clp; st; ren -b; muxes; cec; ps
r examples/i10.blif; resyn2; fpga; cec; ps; u; map; cec; ps
r examples/i10.blif; choice; fpga; cec; ps; u; map; cec; ps
r examples/pj1.blif; st; if; cec; ps; u; map; cec; ps
r examples/s38417.blif; comb; w 1.blif; resyn; if; cec 1.blif; ps
r examples/s38417.blif; resyn; if; cec; ps; u; map; cec; ps
r examples/s38584.bench; resyn; ren -s; fx; if; cec; ps; u; map; cec; ps
r examples/s444.blif; b; esd -v; print_exdc; dsd; cec; ps
r examples/s444.blif; double; frames -F 5; w 1.blif; ffpga -K 8; cec 1.blif
r examples/s5378.blif; frames -F 5; cycle; w 1.blif; ps; ret; ps; sec 1.blif
r examples/s6669.blif; cycle; w 1.blif; ps; ret -M 3; resyn; ps; sec 1.blif
time

171
regtest_output.txt
View File

@ -1,39 +1,75 @@
UC Berkeley, ABC 1.01 (compiled Feb 3 2006 10:48:34)
UC Berkeley, ABC 1.01 (compiled Dec 25 2006 17:15:00)
abc 01> so regtest.script
abc - > r examples/apex4.pla; resyn; sharem; fpga; cec; ps; clp; share; resyn; map; cec; ps
Networks are equivalent after fraiging.
examples/apex4: i/o = 9/ 19 lat = 0 nd = 1185 cube = 2200 lev = 7
The shared BDD size is 900 nodes.
abc - > r examples/apex4.pla; resyn; if; cec; ps; clp; resyn; map; cec; ps
Networks are equivalent.
examples/apex4: i/o = 9/ 19 lat = 0 nd = 1172 aig = 4365 lev = 7
The shared BDD size is 917 nodes. BDD construction time = 0.04 sec
A simple supergate library is derived from gate library "mcnc_temp.genlib".
Loaded 20 unique 5-input supergates from "mcnc_temp.super". Time = 0.03 sec
Networks are equivalent after fraiging.
examples/apex4: i/o = 9/ 19 lat = 0 nd = 1837 area = 4560.00 delay = 11.70 lev = 11
abc - > r examples/C2670.blif; resyn; fpga; cec; ps; u; map; cec; ps
Networks are equivalent after fraiging.
C2670.iscas : i/o = 233/ 140 lat = 0 nd = 218 cube = 444 lev = 7
Networks are equivalent after fraiging.
C2670.iscas : i/o = 233/ 140 lat = 0 nd = 466 area = 1160.00 delay = 15.50 lev = 14
abc - > r examples/frg2.blif; dsd; muxes; cec; clp; share; resyn; map; cec; ps
Networks are equivalent after fraiging.
The shared BDD size is 1111 nodes.
Networks are equivalent after fraiging.
frg2 : i/o = 143/ 139 lat = 0 nd = 547 area = 1381.00 delay = 9.70 lev = 9
abc - > r examples/pj1.blif; resyn; fpga; cec; ps; u; map; cec; ps
Networks are equivalent after fraiging.
exCombCkt : i/o = 1769/1063 lat = 0 nd = 5609 cube = 10395 lev = 15
Networks are equivalent after fraiging.
exCombCkt : i/o = 1769/1063 lat = 0 nd = 10317 area = 24980.00 delay = 29.80 lev = 27
abc - > r examples/s38584.bench; resyn; fpga; cec; ps; u; map; cec; ps
Networks are equivalent after fraiging.
examples/s38584: i/o = 12/ 278 lat = 1452 nd = 4405 cube = 7515 lev = 9
Networks are equivalent after fraiging.
examples/s38584: i/o = 12/ 278 lat = 1452 nd = 8509 area = 19316.00 delay = 20.60 lev = 17
abc - > r examples/ac.v; resyn; fpga; cec; ps; u; map; cec; ps
Networks are equivalent after fraiging.
ac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 4085 cube = 7780 lev = 4
Networks are equivalent after fraiging.
ac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 8278 area = 19714.00 delay = 8.10 lev = 8
abc - > r examples/s444.blif; b; esd -v; dsd; cec; ps
Loaded 20 unique 5-input supergates from "mcnc_temp.super". Time = 0.02 sec
Networks are equivalent.
examples/apex4: i/o = 9/ 19 lat = 0 nd = 1734 aig = 2576 lev = 12
abc - > r examples/C2670.blif; st; w 1.aig; cec 1.aig
Networks are equivalent after structural hashing.
abc - > r examples/C2670.blif; st; short_names; w 1.bench; cec 1.bench
Networks are equivalent after structural hashing.
abc - > r examples/C2670.blif; st; short_names; ren -s; w 1.eqn; cec 1.eqn
Networks are equivalent.
abc - > r examples/C2670.blif; resyn2; if -K 8; cec; ps; u; map; cec; ps
Networks are equivalent.
C2670.iscas : i/o = 233/ 140 lat = 0 nd = 120 aig = 1056 lev = 4
Networks are equivalent.
C2670.iscas : i/o = 233/ 140 lat = 0 nd = 467 aig = 651 lev = 14
abc - > r examples/frg2.blif; dsd; muxes; cec; ps; clp; share; resyn; map; cec; ps
Networks are equivalent.
frg2 : i/o = 143/ 139 lat = 0 nd = 1648 aig = 2268 lev = 18
The shared BDD size is 1672 nodes. BDD construction time = 0.14 sec
Networks are equivalent.
frg2 : i/o = 143/ 139 lat = 0 nd = 533 aig = 778 lev = 8
abc - > r examples/frg2.blif; bdd; muxes; cec; ps; clp; st; ren -b; muxes; cec; ps
Networks are equivalent.
frg2 : i/o = 143/ 139 lat = 0 nd = 2868 aig = 4221 lev = 38
The shared BDD size is 1684 nodes. BDD construction time = 0.14 sec
Networks are equivalent.
frg2 : i/o = 143/ 139 lat = 0 nd = 2331 aig = 3180 lev = 20
abc - > r examples/i10.blif; resyn2; fpga; cec; ps; u; map; cec; ps
Networks are equivalent.
i10 : i/o = 257/ 224 lat = 0 nd = 808 aig = 2630 lev = 12
Networks are equivalent.
i10 : i/o = 257/ 224 lat = 0 nd = 1555 aig = 1980 lev = 24
abc - > r examples/i10.blif; choice; fpga; cec; ps; u; map; cec; ps
Currently stored 3 networks with 5801 nodes will be fraiged.
Total fraiging time = 0.39 sec
Performing FPGA mapping with choices.
Networks are equivalent.
i10 : i/o = 257/ 224 lat = 0 nd = 798 aig = 2543 lev = 12
Performing mapping with choices.
Networks are equivalent.
i10 : i/o = 257/ 224 lat = 0 nd = 1463 aig = 1993 lev = 23
abc - > r examples/pj1.blif; st; if; cec; ps; u; map; cec; ps
Networks are equivalent after structural hashing.
exCombCkt : i/o = 1769/1063 lat = 0 nd = 5984 aig = 23156 lev = 52
Networks are equivalent.
exCombCkt : i/o = 1769/1063 lat = 0 nd = 11474 aig = 16032 lev = 80
abc - > r examples/s38417.blif; comb; w 1.blif; resyn; if; cec 1.blif; ps
examples/s38417.blif (line 14): Skipping directive ".wire_load_slope".
Networks are equivalent.
s38417 : i/o = 1664/1742 lat = 0 nd = 3479 aig = 10120 lev = 9
abc - > r examples/s38417.blif; resyn; if; cec; ps; u; map; cec; ps
examples/s38417.blif (line 14): Skipping directive ".wire_load_slope".
examples/s38417.blif (line 14): Skipping directive ".wire_load_slope".
Networks are equivalent.
s38417 : i/o = 28/ 106 lat = 1636 nd = 3479 aig = 10120 lev = 9
examples/s38417.blif (line 14): Skipping directive ".wire_load_slope".
Networks are equivalent.
s38417 : i/o = 28/ 106 lat = 1636 nd = 7189 aig = 8689 lev = 17
abc - > r examples/s38584.bench; resyn; ren -s; fx; if; cec; ps; u; map; cec; ps
The network was strashed and balanced before FPGA mapping.
Networks are equivalent.
examples/s38584: i/o = 12/ 278 lat = 1452 nd = 4266 aig = 12569 lev = 10
The network was strashed and balanced before mapping.
Networks are equivalent.
examples/s38584: i/o = 12/ 278 lat = 1452 nd = 8135 aig = 10674 lev = 18
abc - > r examples/s444.blif; b; esd -v; print_exdc; dsd; cec; ps
The shared BDD size is 181 nodes.
BDD nodes in the transition relation before reordering 557.
BDD nodes in the transition relation after reordering 456.
@ -41,57 +77,20 @@ Reachability analysis completed in 151 iterations.
The number of minterms in the reachable state set = 8865.
BDD nodes in the unreachable states before reordering 124.
BDD nodes in the unreachable states after reordering 113.
Networks are equivalent after fraiging.
s444 : i/o = 3/ 6 lat = 21 nd = 81 cube = 119 lev = 7
abc - > r examples/i10.blif; fpga; cec; ps; u; map; cec; ps
The network was strashed and balanced before FPGA mapping.
Networks are equivalent after fraiging.
i10 : i/o = 257/ 224 lat = 0 nd = 899 cube = 1604 lev = 13
The network was strashed and balanced before mapping.
Networks are equivalent after fraiging.
i10 : i/o = 257/ 224 lat = 0 nd = 1676 area = 4219.00 delay = 30.80 lev = 29
abc - > r examples/i10.blif; choice; fpga; cec; ps; u; map; cec; ps
The number of AIG nodes added to storage = 2675.
The number of AIG nodes added to storage = 1744.
The number of AIG nodes added to storage = 1431.
Currently stored 3 networks with 5850 nodes will be fraiged.
Performing FPGA mapping with choices.
Networks are equivalent after fraiging.
i10 : i/o = 257/ 224 lat = 0 nd = 792 cube = 1459 lev = 12
Performing mapping with choices.
Networks are equivalent after fraiging.
i10 : i/o = 257/ 224 lat = 0 nd = 1484 area = 3518.00 delay = 25.60 lev = 23
abc - > r examples/s6669.blif; fpga; ps; sec; u; sfpga; ps; sec; u; fpga; ret; ps; sec
The network was strashed and balanced before FPGA mapping.
s6669 : i/o = 83/ 55 lat = 239 nd = 679 bdd = 3046 lev = 20
Networks are equivalent after fraiging.
The network was strashed and balanced before FPGA mapping/retiming.
The number of MUXes detected = 120 (34.25 % of logic). Creating solver = 0.00 sec
SAT solver time = 0.00 sec
The number of LUTs with incompatible edges = 24.
The number of LUTs with more than 4 inputs = 18.
s6669 : i/o = 83/ 55 lat = 404 nd = 818 bdd = 3829 lev = 6
Networks are equivalent after fraiging.
The network was strashed and balanced before FPGA mapping.
The number of MUXes detected = 69 (37.03 % of logic). Creating solver = 0.00 sec
SAT solver time = 0.00 sec
s6669 : i/o = 83/ 55 lat = 346 nd = 772 bdd = 3254 lev = 9
Networks are equivalent after fraiging.
abc - > r examples/s5378.blif; map -s; ps; sec; u; smap; ps; sec; u; map; ret; ps; sec
The network was strashed and balanced before mapping.
s5378 : i/o = 35/ 49 lat = 164 nd = 1015 area = 2384.00 delay = 12.40 lev = 10
Networks are equivalent after fraiging.
The number of nodes with equal fanins = 5.
The network was strashed and balanced before SC mapping/retiming.
The mininum clock period computed is 10.00.
The resulting network is derived as BDD logic network (this is temporary).
The number of MUXes detected = 0 ( 0.00 % of logic). Creating solver = 0.00 sec
SAT solver time = 0.00 sec
s5378 : i/o = 35/ 49 lat = 396 nd = 1252 bdd = 4612 lev = 7
Networks are equivalent after fraiging.
The network was strashed and balanced before mapping.
s5378 : i/o = 35/ 49 lat = 360 nd = 1087 area = 2454.00 delay = 12.10 lev = 11
EXDC network statistics:
exdc : i/o = 21/ 21 lat = 0 nd = 21 cube = 86 lev = 2
Networks are equivalent.
s444 : i/o = 3/ 6 lat = 21 nd = 82 aig = 176 lev = 7
abc - > r examples/s444.blif; double; frames -F 5; w 1.blif; ffpga -K 8; cec 1.blif
Networks are equivalent after structural hashing.
abc - > r examples/s5378.blif; frames -F 5; cycle; w 1.blif; ps; ret; ps; sec 1.blif
s5378_5_frames: i/o = 175/ 245 lat = 164 and = 6629 (exor = 115) lev = 59
s5378_5_frames: i/o = 175/ 245 lat = 182 nd = 6957 cube = 6956 lev = 50
Networks are equivalent after framing.
abc - > r examples/s6669.blif; cycle; w 1.blif; ps; ret -M 3; resyn; ps; sec 1.blif
s6669 : i/o = 83/ 55 lat = 239 nd = 3080 cube = 3080 lev = 93
s6669 : i/o = 83/ 55 lat = 183 and = 1915 (exor = 371) lev = 97
Networks are equivalent after fraiging.
abc - > time
elapse: 39.54 seconds, total: 39.54 seconds
abc 122>
elapse: 44.07 seconds, total: 44.07 seconds
abc 150>

97
regtest_output2.txt
View File

@ -1,97 +0,0 @@
UC Berkeley, ABC 1.01 (compiled May 9 2006 09:22:13)
abc 02> so regtest.script
abc - > r examples/apex4.pla; resyn; sharem; fpga; cec; ps; clp; share; resyn; map; cec; ps
Networks are equivalent.
examples/apex4: i/o = 9/ 19 lat = 0 nd = 1183 cube = 2195 lev = 7
The shared BDD size is 900 nodes.
A simple supergate library is derived from gate library "mcnc_temp.genlib".
Loaded 20 unique 5-input supergates from "mcnc_temp.super". Time = 0.03 sec
Networks are equivalent.
examples/apex4: i/o = 9/ 19 lat = 0 nd = 1789 area = 4554.00 delay = 11.50 lev = 11
abc - > r examples/C2670.blif; resyn; fpga; cec; ps; u; map; cec; ps
Networks are equivalent.
C2670.iscas : i/o = 233/ 140 lat = 0 nd = 218 cube = 444 lev = 7
Networks are equivalent.
C2670.iscas : i/o = 233/ 140 lat = 0 nd = 471 area = 1166.00 delay = 15.50 lev = 14
abc - > r examples/frg2.blif; dsd; muxes; cec; clp; share; resyn; map; cec; ps
Networks are equivalent.
The shared BDD size is 1111 nodes.
Networks are equivalent.
frg2 : i/o = 143/ 139 lat = 0 nd = 540 area = 1373.00 delay = 9.70 lev = 9
abc - > r examples/pj1.blif; resyn; fpga; cec; ps; u; map; cec; ps
Networks are equivalent.
exCombCkt : i/o = 1769/1063 lat = 0 nd = 5582 cube = 10389 lev = 15
Networks are equivalent.
exCombCkt : i/o = 1769/1063 lat = 0 nd = 10291 area = 24781.00 delay = 29.80 lev = 27
abc - > r examples/s38584.bench; resyn; fpga; cec; ps; u; map; cec; ps
Networks are equivalent.
examples/s38584: i/o = 12/ 278 lat = 1452 nd = 4404 cube = 7515 lev = 9
Networks are equivalent.
examples/s38584: i/o = 12/ 278 lat = 1452 nd = 8506 area = 19313.00 delay = 20.60 lev = 17
abc - > r examples/ac.v; resyn; fpga; cec; ps; u; map; cec; ps
Networks are equivalent.
ac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 4082 cube = 7776 lev = 4
Networks are equivalent.
ac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 8274 area = 19707.00 delay = 8.10 lev = 8
abc - > r examples/s444.blif; b; esd -v; dsd; cec; ps
The shared BDD size is 181 nodes.
BDD nodes in the transition relation before reordering 557.
BDD nodes in the transition relation after reordering 456.
Reachability analysis completed in 151 iterations.
The number of minterms in the reachable state set = 8865.
BDD nodes in the unreachable states before reordering 124.
BDD nodes in the unreachable states after reordering 113.
Networks are equivalent.
s444 : i/o = 3/ 6 lat = 21 nd = 81 cube = 119 lev = 7
abc - > r examples/i10.blif; fpga; cec; ps; u; map; cec; ps
The network was strashed and balanced before FPGA mapping.
Networks are equivalent.
i10 : i/o = 257/ 224 lat = 0 nd = 890 cube = 1593 lev = 13
The network was strashed and balanced before mapping.
Networks are equivalent.
i10 : i/o = 257/ 224 lat = 0 nd = 1700 area = 4245.00 delay = 30.80 lev = 28
abc - > r examples/i10.blif; choice; fpga; cec; ps; u; map; cec; ps
Currently stored 3 networks with 5794 nodes will be fraiged.
Total fraiging time = 0.74 sec
Performing FPGA mapping with choices.
Networks are equivalent.
i10 : i/o = 257/ 224 lat = 0 nd = 799 cube = 1484 lev = 12
Performing mapping with choices.
Networks are equivalent.
i10 : i/o = 257/ 224 lat = 0 nd = 1485 area = 3528.00 delay = 25.40 lev = 23
abc - > r examples/s6669.blif; fpga; ps; sec; u; sfpga; ps; sec; u; fpga; ret; ps; sec
The network was strashed and balanced before FPGA mapping.
s6669 : i/o = 83/ 55 lat = 239 nd = 679 bdd = 3060 lev = 20
Networks are equivalent after fraiging.
The network was strashed and balanced before FPGA mapping/retiming.
The number of LUTs with incompatible edges = 25.
The number of LUTs with more than 4 inputs = 18.
s6669 : i/o = 83/ 55 lat = 404 nd = 829 bdd = 3867 lev = 6
Networks are equivalent after fraiging.
The network was strashed and balanced before FPGA mapping.
s6669 : i/o = 83/ 55 lat = 347 nd = 773 bdd = 3262 lev = 9
Networks are equivalent after fraiging.
abc - > r examples/s5378.blif; map -s; ps; sec; u; smap; ps; sec; u; map; ret; ps; sec
The network was strashed and balanced before mapping.
s5378 : i/o = 35/ 49 lat = 164 nd = 1009 area = 2352.00 delay = 12.40 lev = 11
Networks are equivalent after fraiging.
The number of nodes with equal fanins = 5.
The network was strashed and balanced before SC mapping/retiming.
The mininum clock period computed is 10.00.
The resulting network is derived as BDD logic network (this is temporary).
s5378 : i/o = 35/ 49 lat = 399 nd = 1230 bdd = 4548 lev = 7
Networks are equivalent after fraiging.
The network was strashed and balanced before mapping.
s5378 : i/o = 35/ 49 lat = 359 nd = 1083 area = 2426.00 delay = 13.00 lev = 11
Networks are equivalent after fraiging.
abc - > time
elapse: 188.97 seconds, total: 188.97 seconds
abc 123>

1
src/aig/hop/hop.h
View File

@ -304,6 +304,7 @@ extern void Hop_ObjCollectMulti( Hop_Obj_t * pFunc, Vec_Ptr_t * vSupe
extern int Hop_ObjIsMuxType( Hop_Obj_t * pObj );
extern int Hop_ObjRecognizeExor( Hop_Obj_t * pObj, Hop_Obj_t ** ppFan0, Hop_Obj_t ** ppFan1 );
extern Hop_Obj_t * Hop_ObjRecognizeMux( Hop_Obj_t * pObj, Hop_Obj_t ** ppObjT, Hop_Obj_t ** ppObjE );
extern void Hop_ObjPrintEqn( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, int Level );
extern void Hop_ObjPrintVerilog( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, int Level );
extern void Hop_ObjPrintVerbose( Hop_Obj_t * pObj, int fHaig );
extern void Hop_ManPrintVerbose( Hop_Man_t * p, int fHaig );

47
src/aig/hop/hopUtil.c
View File

@ -281,6 +281,53 @@ Hop_Obj_t * Hop_ObjRecognizeMux( Hop_Obj_t * pNode, Hop_Obj_t ** ppNodeT, Hop_Ob
}
/**Function*************************************************************
Synopsis [Prints Eqn formula for the AIG rooted at this node.]
Description [The formula is in terms of PIs, which should have
their names assigned in pObj->pData fields.]
SideEffects []
SeeAlso []
***********************************************************************/
void Hop_ObjPrintEqn( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, int Level )
{
Vec_Ptr_t * vSuper;
Hop_Obj_t * pFanin;
int fCompl, i;
// store the complemented attribute
fCompl = Hop_IsComplement(pObj);
pObj = Hop_Regular(pObj);
// constant case
if ( Hop_ObjIsConst1(pObj) )
{
fprintf( pFile, "%d", !fCompl );
return;
}
// PI case
if ( Hop_ObjIsPi(pObj) )
{
fprintf( pFile, "%s%s", fCompl? "!" : "", pObj->pData );
return;
}
// AND case
Vec_VecExpand( vLevels, Level );
vSuper = Vec_VecEntry(vLevels, Level);
Hop_ObjCollectMulti( pObj, vSuper );
fprintf( pFile, "%s", (Level==0? "" : "(") );
Vec_PtrForEachEntry( vSuper, pFanin, i )
{
Hop_ObjPrintEqn( pFile, Hop_NotCond(pFanin, fCompl), vLevels, Level+1 );
if ( i < Vec_PtrSize(vSuper) - 1 )
fprintf( pFile, " %s ", fCompl? "+" : "*" );
}
fprintf( pFile, "%s", (Level==0? "" : ")") );
return;
}
/**Function*************************************************************
Synopsis [Prints Verilog formula for the AIG rooted at this node.]

2
src/aig/ivy/attr.h
View File

@ -193,7 +193,7 @@ static inline void Attr_ManStop( Attr_Man_t * p )
p->pFuncFreeMan( p->pManAttr );
// free the memory manager
if ( p->pManMem )
Extra_MmFixedStop( p->pManMem, 0 );
Extra_MmFixedStop( p->pManMem);
// free the attribute manager
FREE( p->pAttrs );
free( p );

1
src/aig/ivy/ivy.h
View File

@ -268,6 +268,7 @@ static inline Ivy_Obj_t * Ivy_ObjChild0( Ivy_Obj_t * pObj ) { return pObj-
static inline Ivy_Obj_t * Ivy_ObjChild1( Ivy_Obj_t * pObj ) { return pObj->pFanin1; }
static inline Ivy_Obj_t * Ivy_ObjChild0Equiv( Ivy_Obj_t * pObj ) { assert( !Ivy_IsComplement(pObj) ); return Ivy_ObjFanin0(pObj)? Ivy_NotCond(Ivy_ObjFanin0(pObj)->pEquiv, Ivy_ObjFaninC0(pObj)) : NULL; }
static inline Ivy_Obj_t * Ivy_ObjChild1Equiv( Ivy_Obj_t * pObj ) { assert( !Ivy_IsComplement(pObj) ); return Ivy_ObjFanin1(pObj)? Ivy_NotCond(Ivy_ObjFanin1(pObj)->pEquiv, Ivy_ObjFaninC1(pObj)) : NULL; }
static inline Ivy_Obj_t * Ivy_ObjEquiv( Ivy_Obj_t * pObj ) { return Ivy_Regular(pObj)->pEquiv? Ivy_NotCond(Ivy_Regular(pObj)->pEquiv, Ivy_IsComplement(pObj)) : NULL; }
static inline int Ivy_ObjLevel( Ivy_Obj_t * pObj ) { return pObj->Level; }
static inline int Ivy_ObjLevelNew( Ivy_Obj_t * pObj ) { return 1 + Ivy_ObjIsExor(pObj) + IVY_MAX(Ivy_ObjFanin0(pObj)->Level, Ivy_ObjFanin1(pObj)->Level); }
static inline int Ivy_ObjFaninPhase( Ivy_Obj_t * pObj ) { return Ivy_IsComplement(pObj)? !Ivy_Regular(pObj)->fPhase : pObj->fPhase; }

43
src/aig/ivy/ivyFraig.c
View File

@ -750,6 +750,26 @@ int Ivy_NodeHasZeroSim( Ivy_FraigMan_t * p, Ivy_Obj_t * pObj )
return 1;
}
/**Function*************************************************************
Synopsis [Returns 1 if simulation info is composed of all zeros.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Ivy_NodeComplementSim( Ivy_FraigMan_t * p, Ivy_Obj_t * pObj )
{
Ivy_FraigSim_t * pSims;
int i;
pSims = Ivy_ObjSim(pObj);
for ( i = 0; i < p->nSimWords; i++ )
pSims->pData[i] = ~pSims->pData[i];
}
/**Function*************************************************************
Synopsis [Returns 1 if simulation infos are equal.]
@ -1277,7 +1297,11 @@ void Ivy_FraigCheckOutputSimsSavePattern( Ivy_FraigMan_t * p, Ivy_Obj_t * pObj )
// fill in the counter-example data
pModel = ALLOC( int, Ivy_ManPiNum(p->pManFraig) );
Ivy_ManForEachPi( p->pManAig, pObj, i )
{
pModel[i] = Ivy_InfoHasBit(Ivy_ObjSim(pObj)->pData, BestPat);
// printf( "%d", pModel[i] );
}
// printf( "\n" );
// set the model
assert( p->pManFraig->pData == NULL );
p->pManFraig->pData = pModel;
@ -1299,13 +1323,25 @@ int Ivy_FraigCheckOutputSims( Ivy_FraigMan_t * p )
{
Ivy_Obj_t * pObj;
int i;
// make sure the reference simulation pattern does not detect the bug
pObj = Ivy_ManPo( p->pManAig, 0 );
assert( Ivy_ObjFanin0(pObj)->fPhase == (unsigned)Ivy_ObjFaninC0(pObj) ); // Ivy_ObjFaninPhase(Ivy_ObjChild0(pObj)) == 0
Ivy_ManForEachPo( p->pManAig, pObj, i )
{
// complement simulation info
// if ( Ivy_ObjFanin0(pObj)->fPhase ^ Ivy_ObjFaninC0(pObj) ) // Ivy_ObjFaninPhase(Ivy_ObjChild0(pObj))
// Ivy_NodeComplementSim( p, Ivy_ObjFanin0(pObj) );
// check
if ( !Ivy_NodeHasZeroSim( p, Ivy_ObjFanin0(pObj) ) )
{
// create the counter-example from this pattern
Ivy_FraigCheckOutputSimsSavePattern( p, Ivy_ObjFanin0(pObj) );
return 1;
}
// complement simulation info
// if ( Ivy_ObjFanin0(pObj)->fPhase ^ Ivy_ObjFaninC0(pObj) )
// Ivy_NodeComplementSim( p, Ivy_ObjFanin0(pObj) );
}
return 0;
}
@ -1819,6 +1855,9 @@ void Ivy_FraigMiterProve( Ivy_FraigMan_t * p )
{
if ( fVerbose )
printf( "Output %2d (out of %2d) is constant 1. ", i, Ivy_ManPoNum(p->pManAig) );
// assing constant 0 model
p->pManFraig->pData = ALLOC( int, Ivy_ManPiNum(p->pManFraig) );
memset( p->pManFraig->pData, 0, sizeof(int) * Ivy_ManPiNum(p->pManFraig) );
break;
}
// check if the output is constant 0
@ -1957,10 +1996,6 @@ Ivy_Obj_t * Ivy_FraigAnd( Ivy_FraigMan_t * p, Ivy_Obj_t * pObjOld )
if ( Ivy_ObjClassNodeRepr(pObjOld) == NULL || // this is a unique node
(!p->pParams->fDoSparse && Ivy_ObjClassNodeRepr(pObjOld) == p->pManAig->pConst1) ) // this is a sparse node
{
// if ( Ivy_ObjClassNodeRepr(pObjOld) == p->pManAig->pConst1 )
// {
// int x = 0;
// }
assert( Ivy_Regular(pFanin0New) != Ivy_Regular(pFanin1New) );
assert( pObjNew != Ivy_Regular(pFanin0New) );
assert( pObjNew != Ivy_Regular(pFanin1New) );

64
src/base/abc/abc.h
View File

@ -53,8 +53,7 @@ typedef enum {
ABC_NTK_NETLIST, // 1: network with PIs/POs, latches, nodes, and nets
ABC_NTK_LOGIC, // 2: network with PIs/POs, latches, and nodes
ABC_NTK_STRASH, // 3: structurally hashed AIG (two input AND gates with c-attributes on edges)
ABC_NTK_SEQ, // 4: sequential AIG (two input AND gates with c- and latch-attributes on edges)
ABC_NTK_OTHER // 6: unused
ABC_NTK_OTHER // 4: unused
} Abc_NtkType_t;
// network functionality
@ -64,8 +63,9 @@ typedef enum {
ABC_FUNC_BDD, // 2: binary decision diagrams
ABC_FUNC_AIG, // 3: and-inverter graphs
ABC_FUNC_MAP, // 4: standard cell library
ABC_FUNC_BLACKBOX, // 5: black box about which nothing is known
ABC_FUNC_OTHER // 6: unused
ABC_FUNC_BLIFMV, // 5: BLIF-MV node functions
ABC_FUNC_BLACKBOX, // 6: black box about which nothing is known
ABC_FUNC_OTHER // 7: unused
} Abc_NtkFunc_t;
// Supported type/functionality combinations:
@ -77,8 +77,6 @@ typedef enum {
| Logic | x | x | x | x |
|-----------|-------|-------|-------|-------|
| Strash | | | x | |
|-----------|-------|-------|-------|-------|
| Seq | | | x | |
--------------------------------------------|*/
// object types
@ -211,6 +209,7 @@ struct Abc_Lib_t_
{
char * pName; // the name of the library
void * pManFunc; // functionality manager for the nodes
Vec_Ptr_t * vTops; // the array of top-level modules
Vec_Ptr_t * vModules; // the array of modules
st_table * tModules; // the table hashing module names into their networks
Abc_Lib_t * pLibrary; // the library used to map this design
@ -238,17 +237,18 @@ static inline void Abc_InfoXorBit( unsigned * p, int i ) { p[(i)>>5]
static inline bool Abc_NtkIsNetlist( Abc_Ntk_t * pNtk ) { return pNtk->ntkType == ABC_NTK_NETLIST; }
static inline bool Abc_NtkIsLogic( Abc_Ntk_t * pNtk ) { return pNtk->ntkType == ABC_NTK_LOGIC; }
static inline bool Abc_NtkIsStrash( Abc_Ntk_t * pNtk ) { return pNtk->ntkType == ABC_NTK_STRASH; }
static inline bool Abc_NtkIsSeq( Abc_Ntk_t * pNtk ) { return pNtk->ntkType == ABC_NTK_SEQ; }
static inline bool Abc_NtkHasSop( Abc_Ntk_t * pNtk ) { return pNtk->ntkFunc == ABC_FUNC_SOP; }
static inline bool Abc_NtkHasBdd( Abc_Ntk_t * pNtk ) { return pNtk->ntkFunc == ABC_FUNC_BDD; }
static inline bool Abc_NtkHasAig( Abc_Ntk_t * pNtk ) { return pNtk->ntkFunc == ABC_FUNC_AIG; }
static inline bool Abc_NtkHasMapping( Abc_Ntk_t * pNtk ) { return pNtk->ntkFunc == ABC_FUNC_MAP; }
static inline bool Abc_NtkHasBlifMv( Abc_Ntk_t * pNtk ) { return pNtk->ntkFunc == ABC_FUNC_BLIFMV; }
static inline bool Abc_NtkHasBlackbox( Abc_Ntk_t * pNtk ) { return pNtk->ntkFunc == ABC_FUNC_BLACKBOX; }
static inline bool Abc_NtkIsSopNetlist( Abc_Ntk_t * pNtk ) { return pNtk->ntkFunc == ABC_FUNC_SOP && pNtk->ntkType == ABC_NTK_NETLIST; }
static inline bool Abc_NtkIsAigNetlist( Abc_Ntk_t * pNtk ) { return pNtk->ntkFunc == ABC_FUNC_AIG && pNtk->ntkType == ABC_NTK_NETLIST; }
static inline bool Abc_NtkIsMappedNetlist( Abc_Ntk_t * pNtk ) { return pNtk->ntkFunc == ABC_FUNC_MAP && pNtk->ntkType == ABC_NTK_NETLIST; }
static inline bool Abc_NtkIsBlifMvNetlist( Abc_Ntk_t * pNtk ) { return pNtk->ntkFunc == ABC_FUNC_BLIFMV && pNtk->ntkType == ABC_NTK_NETLIST; }
static inline bool Abc_NtkIsSopLogic( Abc_Ntk_t * pNtk ) { return pNtk->ntkFunc == ABC_FUNC_SOP && pNtk->ntkType == ABC_NTK_LOGIC ; }
static inline bool Abc_NtkIsBddLogic( Abc_Ntk_t * pNtk ) { return pNtk->ntkFunc == ABC_FUNC_BDD && pNtk->ntkType == ABC_NTK_LOGIC ; }
static inline bool Abc_NtkIsAigLogic( Abc_Ntk_t * pNtk ) { return pNtk->ntkFunc == ABC_FUNC_AIG && pNtk->ntkType == ABC_NTK_LOGIC ; }
@ -294,7 +294,7 @@ static inline Abc_Obj_t * Abc_NtkCreatePi( Abc_Ntk_t * pNtk ) { return Ab
static inline Abc_Obj_t * Abc_NtkCreatePo( Abc_Ntk_t * pNtk ) { return Abc_NtkCreateObj( pNtk, ABC_OBJ_PO ); }
static inline Abc_Obj_t * Abc_NtkCreateBi( Abc_Ntk_t * pNtk ) { return Abc_NtkCreateObj( pNtk, ABC_OBJ_BI ); }
static inline Abc_Obj_t * Abc_NtkCreateBo( Abc_Ntk_t * pNtk ) { return Abc_NtkCreateObj( pNtk, ABC_OBJ_BO ); }
static Abc_Obj_t * Abc_NtkCreateAssert( Abc_Ntk_t * pNtk ) { return Abc_NtkCreateObj( pNtk, ABC_OBJ_ASSERT ); }
static inline Abc_Obj_t * Abc_NtkCreateAssert( Abc_Ntk_t * pNtk ) { return Abc_NtkCreateObj( pNtk, ABC_OBJ_ASSERT ); }
static inline Abc_Obj_t * Abc_NtkCreateNode( Abc_Ntk_t * pNtk ) { return Abc_NtkCreateObj( pNtk, ABC_OBJ_NODE ); }
static inline Abc_Obj_t * Abc_NtkCreateLatch( Abc_Ntk_t * pNtk ) { return Abc_NtkCreateObj( pNtk, ABC_OBJ_LATCH ); }
static inline Abc_Obj_t * Abc_NtkCreateGate( Abc_Ntk_t * pNtk ) { return Abc_NtkCreateObj( pNtk, ABC_OBJ_GATE ); }
@ -310,6 +310,12 @@ static inline Abc_Obj_t * Abc_NtkCo( Abc_Ntk_t * pNtk, int i ) { return (A
static inline Abc_Obj_t * Abc_NtkAssert( Abc_Ntk_t * pNtk, int i ) { return (Abc_Obj_t *)Vec_PtrEntry( pNtk->vAsserts, i );}
static inline Abc_Obj_t * Abc_NtkBox( Abc_Ntk_t * pNtk, int i ) { return (Abc_Obj_t *)Vec_PtrEntry( pNtk->vBoxes, i ); }
// working with complemented attributes of objects
static inline bool Abc_ObjIsComplement( Abc_Obj_t * p ) { return (bool)((unsigned long)p & (unsigned long)01); }
static inline Abc_Obj_t * Abc_ObjRegular( Abc_Obj_t * p ) { return (Abc_Obj_t *)((unsigned long)p & ~(unsigned long)01); }
static inline Abc_Obj_t * Abc_ObjNot( Abc_Obj_t * p ) { return (Abc_Obj_t *)((unsigned long)p ^ (unsigned long)01); }
static inline Abc_Obj_t * Abc_ObjNotCond( Abc_Obj_t * p, int c ) { return (Abc_Obj_t *)((unsigned long)p ^ (unsigned long)(c!=0)); }
// reading data members of the object
static inline unsigned Abc_ObjType( Abc_Obj_t * pObj ) { return pObj->Type; }
static inline unsigned Abc_ObjId( Abc_Obj_t * pObj ) { return pObj->Id; }
@ -319,17 +325,12 @@ static inline Vec_Int_t * Abc_ObjFanoutVec( Abc_Obj_t * pObj ) { return &p
static inline Abc_Obj_t * Abc_ObjCopy( Abc_Obj_t * pObj ) { return pObj->pCopy; }
static inline Abc_Ntk_t * Abc_ObjNtk( Abc_Obj_t * pObj ) { return pObj->pNtk; }
static inline void * Abc_ObjData( Abc_Obj_t * pObj ) { return pObj->pData; }
static inline Abc_Obj_t * Abc_ObjEquiv( Abc_Obj_t * pObj ) { return Abc_ObjRegular(pObj)->pCopy? Abc_ObjNotCond(Abc_ObjRegular(pObj)->pCopy, Abc_ObjIsComplement(pObj)) : NULL; }
// setting data members of the network
static inline void Abc_ObjSetCopy( Abc_Obj_t * pObj, Abc_Obj_t * pCopy ) { pObj->pCopy = pCopy; }
static inline void Abc_ObjSetData( Abc_Obj_t * pObj, void * pData ) { pObj->pData = pData; }
// working with complemented attributes of objects
static inline bool Abc_ObjIsComplement( Abc_Obj_t * p ) { return (bool)((unsigned long)p & (unsigned long)01); }
static inline Abc_Obj_t * Abc_ObjRegular( Abc_Obj_t * p ) { return (Abc_Obj_t *)((unsigned long)p & ~(unsigned long)01); }
static inline Abc_Obj_t * Abc_ObjNot( Abc_Obj_t * p ) { return (Abc_Obj_t *)((unsigned long)p ^ (unsigned long)01); }
static inline Abc_Obj_t * Abc_ObjNotCond( Abc_Obj_t * p, int c ) { return (Abc_Obj_t *)((unsigned long)p ^ (unsigned long)(c!=0)); }
// checking the object type
static inline bool Abc_ObjIsPio( Abc_Obj_t * pObj ) { return pObj->Type == ABC_OBJ_PIO; }
static inline bool Abc_ObjIsPi( Abc_Obj_t * pObj ) { return pObj->Type == ABC_OBJ_PI; }
@ -375,9 +376,9 @@ static inline Abc_Obj_t * Abc_ObjChild0Copy( Abc_Obj_t * pObj ) { return Ab
static inline Abc_Obj_t * Abc_ObjChild1Copy( Abc_Obj_t * pObj ) { return Abc_ObjNotCond( Abc_ObjFanin1(pObj)->pCopy, Abc_ObjFaninC1(pObj) ); }
// checking the AIG node types
static inline bool Abc_AigNodeIsConst( Abc_Obj_t * pNode ) { assert(Abc_NtkIsStrash(Abc_ObjRegular(pNode)->pNtk)||Abc_NtkIsSeq(Abc_ObjRegular(pNode)->pNtk)); return Abc_ObjRegular(pNode)->Type == ABC_OBJ_CONST1; }
static inline bool Abc_AigNodeIsAnd( Abc_Obj_t * pNode ) { assert(!Abc_ObjIsComplement(pNode)); assert(Abc_NtkIsStrash(pNode->pNtk)||Abc_NtkIsSeq(pNode->pNtk)); return Abc_ObjFaninNum(pNode) == 2; }
static inline bool Abc_AigNodeIsChoice( Abc_Obj_t * pNode ) { assert(!Abc_ObjIsComplement(pNode)); assert(Abc_NtkIsStrash(pNode->pNtk)||Abc_NtkIsSeq(pNode->pNtk)); return pNode->pData != NULL && Abc_ObjFanoutNum(pNode) > 0; }
static inline bool Abc_AigNodeIsConst( Abc_Obj_t * pNode ) { assert(Abc_NtkIsStrash(Abc_ObjRegular(pNode)->pNtk)); return Abc_ObjRegular(pNode)->Type == ABC_OBJ_CONST1; }
static inline bool Abc_AigNodeIsAnd( Abc_Obj_t * pNode ) { assert(!Abc_ObjIsComplement(pNode)); assert(Abc_NtkIsStrash(pNode->pNtk)); return Abc_ObjFaninNum(pNode) == 2; }
static inline bool Abc_AigNodeIsChoice( Abc_Obj_t * pNode ) { assert(!Abc_ObjIsComplement(pNode)); assert(Abc_NtkIsStrash(pNode->pNtk)); return pNode->pData != NULL && Abc_ObjFanoutNum(pNode) > 0; }
// handling persistent nodes
static inline int Abc_NodeIsPersistant( Abc_Obj_t * pNode ) { assert( Abc_AigNodeIsAnd(pNode) ); return pNode->fPersist; }
@ -400,14 +401,21 @@ static inline bool Abc_LatchIsInitNone( Abc_Obj_t * pLatch ) { assert(Ab
static inline bool Abc_LatchIsInit0( Abc_Obj_t * pLatch ) { assert(Abc_ObjIsLatch(pLatch)); return pLatch->pData == (void *)ABC_INIT_ZERO; }
static inline bool Abc_LatchIsInit1( Abc_Obj_t * pLatch ) { assert(Abc_ObjIsLatch(pLatch)); return pLatch->pData == (void *)ABC_INIT_ONE; }
static inline bool Abc_LatchIsInitDc( Abc_Obj_t * pLatch ) { assert(Abc_ObjIsLatch(pLatch)); return pLatch->pData == (void *)ABC_INIT_DC; }
static inline int Abc_LatchInit( Abc_Obj_t * pLatch ) { assert(Abc_ObjIsLatch(pLatch)); return (int)pLatch->pData; }
static inline int Abc_LatchInit( Abc_Obj_t * pLatch ) { assert(Abc_ObjIsLatch(pLatch)); return (int)pLatch->pData; }
// global BDDs of the nodes
static inline void * Abc_NtkGlobalBdds( Abc_Ntk_t * pNtk ) { return (void *)Vec_PtrEntry(pNtk->vAttrs, VEC_ATTR_GLOBAL_BDD); }
static inline DdManager * Abc_NtkGlobalBddMan( Abc_Ntk_t * pNtk ) { return (DdManager *)Vec_AttMan( Abc_NtkGlobalBdds(pNtk) ); }
static inline DdNode ** Abc_NtkGlobalBddArray( Abc_Ntk_t * pNtk ) { return (DdNode **)Vec_AttArray( Abc_NtkGlobalBdds(pNtk) ); }
static inline DdNode * Abc_ObjGlobalBdd( Abc_Obj_t * pObj ) { return (DdNode *)Vec_AttEntry( Abc_NtkGlobalBdds(pObj->pNtk), pObj->Id ); }
static inline void Abc_ObjSetGlobalBdd( Abc_Obj_t * pObj, DdNode * bF ) { Vec_AttWriteEntry( Abc_NtkGlobalBdds(pObj->pNtk), pObj->Id, bF ); }
static inline void * Abc_NtkGlobalBdd( Abc_Ntk_t * pNtk ) { return (void *)Vec_PtrEntry(pNtk->vAttrs, VEC_ATTR_GLOBAL_BDD); }
static inline DdManager * Abc_NtkGlobalBddMan( Abc_Ntk_t * pNtk ) { return (DdManager *)Vec_AttMan( Abc_NtkGlobalBdd(pNtk) ); }
static inline DdNode ** Abc_NtkGlobalBddArray( Abc_Ntk_t * pNtk ) { return (DdNode **)Vec_AttArray( Abc_NtkGlobalBdd(pNtk) ); }
static inline DdNode * Abc_ObjGlobalBdd( Abc_Obj_t * pObj ) { return (DdNode *)Vec_AttEntry( Abc_NtkGlobalBdd(pObj->pNtk), pObj->Id ); }
static inline void Abc_ObjSetGlobalBdd( Abc_Obj_t * pObj, DdNode * bF ) { Vec_AttWriteEntry( Abc_NtkGlobalBdd(pObj->pNtk), pObj->Id, bF ); }
// MV variables of the nodes
static inline void * Abc_NtkMvVar( Abc_Ntk_t * pNtk ) { return Vec_PtrEntry(pNtk->vAttrs, VEC_ATTR_MVVAR); }
static inline void * Abc_NtkMvVarMan( Abc_Ntk_t * pNtk ) { return Abc_NtkMvVar(pNtk)? Vec_AttMan( Abc_NtkMvVar(pNtk) ) : NULL; }
static inline void * Abc_ObjMvVar( Abc_Obj_t * pObj ) { return Abc_NtkMvVar(pObj->pNtk)? Vec_AttEntry( Abc_NtkMvVar(pObj->pNtk), pObj->Id ) : NULL; }
static inline int Abc_ObjMvVarNum( Abc_Obj_t * pObj ) { return (Abc_NtkMvVar(pObj->pNtk) && Abc_ObjMvVar(pObj))? *((int*)Abc_ObjMvVar(pObj)) : 2; }
static inline void Abc_ObjSetMvVar( Abc_Obj_t * pObj, void * pV) { Vec_AttWriteEntry( Abc_NtkMvVar(pObj->pNtk), pObj->Id, pV ); }
// outputs the runtime in seconds
#define PRT(a,t) printf("%s = ", (a)); printf("%6.2f sec\n", (float)(t)/(float)(CLOCKS_PER_SEC))
@ -572,6 +580,9 @@ extern void Abc_NtkInsertLatchValues( Abc_Ntk_t * pNtk, Vec_Int_t
/*=== abcLib.c ==========================================================*/
extern Abc_Lib_t * Abc_LibCreate( char * pName );
extern void Abc_LibFree( Abc_Lib_t * pLib );
extern void Abc_LibPrint( Abc_Lib_t * pLib );
extern int Abc_LibAddModel( Abc_Lib_t * pLib, Abc_Ntk_t * pNtk );
extern Abc_Ntk_t * Abc_LibFindModelByName( Abc_Lib_t * pLib, char * pName );
extern Abc_Ntk_t * Abc_LibDeriveRoot( Abc_Lib_t * pLib );
/*=== abcMiter.c ==========================================================*/
extern int Abc_NtkMinimumBase( Abc_Ntk_t * pNtk );
@ -664,6 +675,7 @@ extern Abc_Ntk_t * Abc_NtkCreateFromNode( Abc_Ntk_t * pNtk, Abc_Obj_t * p
extern Abc_Ntk_t * Abc_NtkCreateWithNode( char * pSop );
extern void Abc_NtkDelete( Abc_Ntk_t * pNtk );
extern void Abc_NtkFixNonDrivenNets( Abc_Ntk_t * pNtk );
extern void Abc_NtkMakeComb( Abc_Ntk_t * pNtk );
/*=== abcPrint.c ==========================================================*/
extern void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored );
extern void Abc_NtkPrintIo( FILE * pFile, Abc_Ntk_t * pNtk );
@ -701,7 +713,7 @@ extern int Abc_NodeRef_rec( Abc_Obj_t * pNode );
/*=== abcRefactor.c ==========================================================*/
extern int Abc_NtkRefactor( Abc_Ntk_t * pNtk, int nNodeSizeMax, int nConeSizeMax, bool fUpdateLevel, bool fUseZeros, bool fUseDcs, bool fVerbose );
/*=== abcRewrite.c ==========================================================*/
extern int Abc_NtkRewrite( Abc_Ntk_t * pNtk, int fUpdateLevel, int fUseZeros, int fVerbose );
extern int Abc_NtkRewrite( Abc_Ntk_t * pNtk, int fUpdateLevel, int fUseZeros, int fVerbose, int fVeryVerbose );
/*=== abcSat.c ==========================================================*/
extern int Abc_NtkMiterSat( Abc_Ntk_t * pNtk, sint64 nConfLimit, sint64 nInsLimit, int fJFront, int fVerbose, sint64 * pNumConfs, sint64 * pNumInspects );
extern solver * Abc_NtkMiterSatCreate( Abc_Ntk_t * pNtk, int fJFront );
@ -789,6 +801,9 @@ extern int Abc_NtkGetMuxNum( Abc_Ntk_t * pNtk );
extern int Abc_NtkGetChoiceNum( Abc_Ntk_t * pNtk );
extern int Abc_NtkGetFaninMax( Abc_Ntk_t * pNtk );
extern void Abc_NtkCleanCopy( Abc_Ntk_t * pNtk );
extern int Abc_NtkCountCopy( Abc_Ntk_t * pNtk );
extern Vec_Ptr_t * Abc_NtkSaveCopy( Abc_Ntk_t * pNtk );
extern void Abc_NtkLoadCopy( Abc_Ntk_t * pNtk, Vec_Ptr_t * vCopies );
extern void Abc_NtkCleanNext( Abc_Ntk_t * pNtk );
extern void Abc_NtkCleanMarkA( Abc_Ntk_t * pNtk );
extern Abc_Obj_t * Abc_NodeFindCoFanout( Abc_Obj_t * pNode );
@ -812,6 +827,7 @@ extern Vec_Ptr_t * Abc_NtkCollectObjects( Abc_Ntk_t * pNtk );
extern Vec_Int_t * Abc_NtkGetCiIds( Abc_Ntk_t * pNtk );
extern void Abc_NtkReassignIds( Abc_Ntk_t * pNtk );
extern int Abc_ObjPointerCompare( void ** pp1, void ** pp2 );
extern void Abc_NtkTransferCopy( Abc_Ntk_t * pNtk );
/*=== abcVerify.c ==========================================================*/
extern int * Abc_NtkVerifyGetCleanModel( Abc_Ntk_t * pNtk, int nFrames );
extern int * Abc_NtkVerifySimulatePattern( Abc_Ntk_t * pNtk, int * pModel );

7
src/base/abc/abcAig.c
View File

@ -309,8 +309,9 @@ Abc_Obj_t * Abc_AigAndCreate( Abc_Aig_t * pMan, Abc_Obj_t * p0, Abc_Obj_t * p1 )
Abc_ObjAddFanin( pAnd, p0 );
Abc_ObjAddFanin( pAnd, p1 );
// set the level of the new node
pAnd->Level = 1 + ABC_MAX( Abc_ObjRegular(p0)->Level, Abc_ObjRegular(p1)->Level );
pAnd->fExor = Abc_NodeIsExorType(pAnd);
pAnd->Level = 1 + ABC_MAX( Abc_ObjRegular(p0)->Level, Abc_ObjRegular(p1)->Level );
pAnd->fExor = Abc_NodeIsExorType(pAnd);
pAnd->fPhase = (Abc_ObjIsComplement(p0) ^ Abc_ObjRegular(p0)->fPhase) & (Abc_ObjIsComplement(p1) ^ Abc_ObjRegular(p1)->fPhase);
// add the node to the corresponding linked list in the table
Key = Abc_HashKey2( p0, p1, pMan->nBins );
pAnd->pNext = pMan->pBins[Key];
@ -650,7 +651,7 @@ void Abc_AigRehash( Abc_Aig_t * pMan )
***********************************************************************/
Abc_Obj_t * Abc_AigConst1( Abc_Ntk_t * pNtk )
{
assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsSeq(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
return ((Abc_Aig_t *)pNtk->pManFunc)->pConst1;
}

44
src/base/abc/abcCheck.c
View File

@ -93,12 +93,12 @@ bool Abc_NtkDoCheck( Abc_Ntk_t * pNtk )
int i;
// check network types
if ( !Abc_NtkIsNetlist(pNtk) && !Abc_NtkIsLogic(pNtk) && !Abc_NtkIsStrash(pNtk) && !Abc_NtkIsSeq(pNtk) )
if ( !Abc_NtkIsNetlist(pNtk) && !Abc_NtkIsLogic(pNtk) && !Abc_NtkIsStrash(pNtk) )
{
fprintf( stdout, "NetworkCheck: Unknown network type.\n" );
return 0;
}
if ( !Abc_NtkHasSop(pNtk) && !Abc_NtkHasBdd(pNtk) && !Abc_NtkHasAig(pNtk) && !Abc_NtkHasMapping(pNtk) && !Abc_NtkHasBlackbox(pNtk) )
if ( !Abc_NtkHasSop(pNtk) && !Abc_NtkHasBdd(pNtk) && !Abc_NtkHasAig(pNtk) && !Abc_NtkHasMapping(pNtk) && !Abc_NtkHasBlifMv(pNtk) && !Abc_NtkHasBlackbox(pNtk) )
{
fprintf( stdout, "NetworkCheck: Unknown functionality type.\n" );
return 0;
@ -112,20 +112,23 @@ bool Abc_NtkDoCheck( Abc_Ntk_t * pNtk )
}
}
// check CI/CO numbers
if ( Abc_NtkPiNum(pNtk) + Abc_NtkLatchNum(pNtk) != Abc_NtkCiNum(pNtk) )
if ( !Abc_NtkBlackboxNum(pNtk) )
{
fprintf( stdout, "NetworkCheck: Number of CIs does not match number of PIs and latches.\n" );
fprintf( stdout, "One possible reason is that latches are added twice:\n" );
fprintf( stdout, "in procedure Abc_NtkCreateObj() and in the user's code.\n" );
return 0;
}
if ( Abc_NtkPoNum(pNtk) + Abc_NtkAssertNum(pNtk) + Abc_NtkLatchNum(pNtk) != Abc_NtkCoNum(pNtk) )
{
fprintf( stdout, "NetworkCheck: Number of COs does not match number of POs, asserts, and latches.\n" );
fprintf( stdout, "One possible reason is that latches are added twice:\n" );
fprintf( stdout, "in procedure Abc_NtkCreateObj() and in the user's code.\n" );
return 0;
// check CI/CO numbers
if ( Abc_NtkPiNum(pNtk) + Abc_NtkLatchNum(pNtk) != Abc_NtkCiNum(pNtk) )
{
fprintf( stdout, "NetworkCheck: Number of CIs does not match number of PIs and latches.\n" );
fprintf( stdout, "One possible reason is that latches are added twice:\n" );
fprintf( stdout, "in procedure Abc_NtkCreateObj() and in the user's code.\n" );
return 0;
}
if ( Abc_NtkPoNum(pNtk) + Abc_NtkAssertNum(pNtk) + Abc_NtkLatchNum(pNtk) != Abc_NtkCoNum(pNtk) )
{
fprintf( stdout, "NetworkCheck: Number of COs does not match number of POs, asserts, and latches.\n" );
fprintf( stdout, "One possible reason is that latches are added twice:\n" );
fprintf( stdout, "in procedure Abc_NtkCreateObj() and in the user's code.\n" );
return 0;
}
}
// check the names
@ -177,14 +180,13 @@ bool Abc_NtkDoCheck( Abc_Ntk_t * pNtk )
}
// check the latches
if ( !Abc_NtkIsSeq(pNtk) )
Abc_NtkForEachLatch( pNtk, pNode, i )
if ( !Abc_NtkCheckLatch( pNtk, pNode ) )
return 0;
Abc_NtkForEachLatch( pNtk, pNode, i )
if ( !Abc_NtkCheckLatch( pNtk, pNode ) )
return 0;
// finally, check for combinational loops
// clk = clock();
if ( !Abc_NtkIsSeq( pNtk ) && !Abc_NtkIsAcyclic( pNtk ) )
if ( !Abc_NtkIsAcyclic( pNtk ) )
{
fprintf( stdout, "NetworkCheck: Network contains a combinational loop.\n" );
return 0;
@ -541,7 +543,7 @@ bool Abc_NtkCheckNode( Abc_Ntk_t * pNtk, Abc_Obj_t * pNode )
return 0;
}
}
else if ( !Abc_NtkHasMapping(pNtk) && !Abc_NtkHasAig(pNtk) )
else if ( !Abc_NtkHasMapping(pNtk) && !Abc_NtkHasBlifMv(pNtk) && !Abc_NtkHasAig(pNtk) )
{
assert( 0 );
}

1
src/base/abc/abcDfs.c
View File

@ -429,7 +429,6 @@ bool Abc_NtkIsDfsOrdered( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode, * pFanin;
int i, k;
assert( !Abc_NtkIsSeq(pNtk) );
// set the traversal ID
Abc_NtkIncrementTravId( pNtk );
// mark the CIs

1
src/base/abc/abcFanio.c
View File

@ -19,7 +19,6 @@
***********************************************************************/
#include "abc.h"
//#include "seqInt.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///

15
src/base/abc/abcFunc.c
View File

@ -75,7 +75,7 @@ int Abc_NtkSopToBdd( Abc_Ntk_t * pNtk )
Cudd_Ref( pNode->pData );
}
Extra_MmFlexStop( pNtk->pManFunc, 0 );
Extra_MmFlexStop( pNtk->pManFunc );
pNtk->pManFunc = dd;
// update the network type
@ -235,7 +235,7 @@ int Abc_NtkBddToSop( Abc_Ntk_t * pNtk, int fDirect )
pNode->pNext = (Abc_Obj_t *)Abc_ConvertBddToSop( pManNew, dd, bFunc, bFunc, Abc_ObjFaninNum(pNode), vCube, fMode );
if ( pNode->pNext == NULL )
{
Extra_MmFlexStop( pManNew, 0 );
Extra_MmFlexStop( pManNew );
Abc_NtkCleanNext( pNtk );
// printf( "Converting from BDDs to SOPs has failed.\n" );
Vec_StrFree( vCube );
@ -552,7 +552,7 @@ int Abc_NtkSopToAig( Abc_Ntk_t * pNtk )
return 0;
}
}
Extra_MmFlexStop( pNtk->pManFunc, 0 );
Extra_MmFlexStop( pNtk->pManFunc );
pNtk->pManFunc = pMan;
// update the network type
@ -655,11 +655,14 @@ int Abc_NtkAigToBdd( Abc_Ntk_t * pNtk )
dd = Cudd_Init( nFaninsMax, 0, CUDD_UNIQUE_SLOTS, CUDD_CACHE_SLOTS, 0 );
// set the mapping of AIG nodes into the BDD nodes
// set the mapping of elementary AIG nodes into the elementary BDD nodes
pMan = pNtk->pManFunc;
assert( Hop_ManPiNum(pMan) >= nFaninsMax );
for ( i = 0; i < nFaninsMax; i++ )
{
Hop_ManPi(pMan, i)->pData = Cudd_bddIthVar(dd, i);
Cudd_Ref( Hop_ManPi(pMan, i)->pData );
}
// convert each node from SOP to BDD
Abc_NtkForEachNode( pNtk, pNode, i )
@ -674,6 +677,10 @@ int Abc_NtkAigToBdd( Abc_Ntk_t * pNtk )
Cudd_Ref( pNode->pData );
}
// dereference intermediate BDD nodes
for ( i = 0; i < nFaninsMax; i++ )
Cudd_RecursiveDeref( dd, Hop_ManPi(pMan, i)->pData );
Hop_ManStop( pNtk->pManFunc );
pNtk->pManFunc = dd;

55
src/base/abc/abcHie.c Normal file
View File

@ -0,0 +1,55 @@
/**CFile****************************************************************
FileName [abcHie.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Network and node package.]
Synopsis [Hierarchy manager.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: abcHie.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "abc.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
typedef struct Abc_Hie_t_ Abc_Hie_t;
struct Abc_Hie_t_
{
Vec_Ptr_t * vTops;
Vec_Ptr_t * vModels;
stmm_table * vNameToModel;
};
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

75
src/base/abc/abcLib.c
View File

@ -46,6 +46,7 @@ Abc_Lib_t * Abc_LibCreate( char * pName )
memset( p, 0, sizeof(Abc_Lib_t) );
p->pName = Extra_UtilStrsav( pName );
p->tModules = st_init_table( strcmp, st_strhash );
p->vTops = Vec_PtrAlloc( 100 );
p->vModules = Vec_PtrAlloc( 100 );
p->pManFunc = Hop_ManStart();
p->pLibrary = NULL;
@ -77,14 +78,84 @@ void Abc_LibFree( Abc_Lib_t * pLib )
{
Vec_PtrForEachEntry( pLib->vModules, pNtk, i )
{
pNtk->pManFunc = NULL;
// pNtk->pManFunc = NULL;
Abc_NtkDelete( pNtk );
}
Vec_PtrFree( pLib->vModules );
}
if ( pLib->vTops )
Vec_PtrFree( pLib->vTops );
free( pLib );
}
/**Function*************************************************************
Synopsis [Prints the library.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_LibPrint( Abc_Lib_t * pLib )
{
Abc_Ntk_t * pNtk;
Abc_Obj_t * pObj;
int i, k;
printf( "Models of design %s:\n", pLib->pName );
Vec_PtrForEachEntry( pLib->vModules, pNtk, i )
{
printf( "%2d : %20s ", i+1, pNtk->pName );
printf( "nd = %6d lat = %6d box = %3d\n", Abc_NtkNodeNum(pNtk), Abc_NtkLatchNum(pNtk), Abc_NtkBlackboxNum(pNtk) );
if ( Abc_NtkBlackboxNum(pNtk) == 0 )
continue;
Abc_NtkForEachBlackbox( pNtk, pObj, k )
printf( " %20s (submodel)\n", Abc_NtkName(pObj->pData) );
}
}
/**Function*************************************************************
Synopsis [Create the library.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_LibAddModel( Abc_Lib_t * pLib, Abc_Ntk_t * pNtk )
{
if ( st_is_member( pLib->tModules, (char *)pNtk->pName ) )
return 0;
st_insert( pLib->tModules, (char *)pNtk->pName, (char *)pNtk );
Vec_PtrPush( pLib->vModules, pNtk );
return 1;
}
/**Function*************************************************************
Synopsis [Create the library.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_LibFindModelByName( Abc_Lib_t * pLib, char * pName )
{
Abc_Ntk_t * pNtk;
if ( !st_is_member( pLib->tModules, (char *)pName ) )
return NULL;
st_lookup( pLib->tModules, (char *)pName, (char **)&pNtk );
return pNtk;
}
/**Function*************************************************************
Synopsis [Frees the library.]
@ -279,7 +350,7 @@ Abc_Ntk_t * Abc_LibDeriveAig( Abc_Ntk_t * pNtk, Abc_Lib_t * pLib )
// deallocate memory manager, which remembers the phase
if ( pNtk->pData )
{
Extra_MmFlexStop( pNtk->pData, 0 );
Extra_MmFlexStop( pNtk->pData );
pNtk->pData = NULL;
}
// set the COs

2
src/base/abc/abcNetlist.c
View File

@ -244,7 +244,7 @@ void Abc_NtkNetlistToLogicHie_rec( Abc_Ntk_t * pNtkNew, Abc_Ntk_t * pNtkOld, int
Abc_Ntk_t * Abc_NtkLogicToNetlist( Abc_Ntk_t * pNtk, int fDirect )
{
Abc_Ntk_t * pNtkNew, * pNtkTemp;
assert( Abc_NtkIsLogic(pNtk) || Abc_NtkIsStrash(pNtk) || Abc_NtkIsSeq(pNtk) );
assert( Abc_NtkIsLogic(pNtk) || Abc_NtkIsStrash(pNtk) );
if ( Abc_NtkIsStrash(pNtk) )
{
pNtkTemp = Abc_NtkAigToLogicSop(pNtk);

104
src/base/abc/abcNtk.c
View File

@ -22,7 +22,6 @@
#include "abcInt.h"
#include "main.h"
#include "mio.h"
//#include "seqInt.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
@ -67,9 +66,7 @@ Abc_Ntk_t * Abc_NtkAlloc( Abc_NtkType_t Type, Abc_NtkFunc_t Func, int fUseMemMan
// start the functionality manager
if ( Abc_NtkIsStrash(pNtk) )
pNtk->pManFunc = Abc_AigAlloc( pNtk );
// else if ( Abc_NtkIsSeq(pNtk) )
// pNtk->pManFunc = Seq_Create( pNtk );
else if ( Abc_NtkHasSop(pNtk) )
else if ( Abc_NtkHasSop(pNtk) || Abc_NtkHasBlifMv(pNtk) )
pNtk->pManFunc = Extra_MmFlexStart();
else if ( Abc_NtkHasBdd(pNtk) )
pNtk->pManFunc = Cudd_Init( 20, 0, CUDD_UNIQUE_SLOTS, CUDD_CACHE_SLOTS, 0 );
@ -342,7 +339,7 @@ Abc_Ntk_t * Abc_NtkDouble( Abc_Ntk_t * pNtk )
// start the network
pNtkNew = Abc_NtkAlloc( pNtk->ntkType, pNtk->ntkFunc, 1 );
sprintf( Buffer, "%s%s", pNtk->pName, "_doubled" );
sprintf( Buffer, "%s%s", pNtk->pName, "_2x" );
pNtkNew->pName = Extra_UtilStrsav(Buffer);
// clean the node copy fields
@ -821,9 +818,9 @@ void Abc_NtkDelete( Abc_Ntk_t * pNtk )
// fprintf( stdout, "The total memory allocated internally by the network = %0.2f Mb.\n", ((double)TotalMemory)/(1<<20) );
// free the storage
if ( pNtk->pMmObj )
Extra_MmFixedStop( pNtk->pMmObj, 0 );
Extra_MmFixedStop( pNtk->pMmObj );
if ( pNtk->pMmStep )
Extra_MmStepStop ( pNtk->pMmStep, 0 );
Extra_MmStepStop ( pNtk->pMmStep );
// name manager
Nm_ManFree( pNtk->pManName );
// free the timing manager
@ -832,10 +829,8 @@ void Abc_NtkDelete( Abc_Ntk_t * pNtk )
// start the functionality manager
if ( Abc_NtkIsStrash(pNtk) )
Abc_AigFree( pNtk->pManFunc );
// else if ( Abc_NtkIsSeq(pNtk) )
// Seq_Delete( pNtk->pManFunc );
else if ( Abc_NtkHasSop(pNtk) )
Extra_MmFlexStop( pNtk->pManFunc, 0 );
else if ( Abc_NtkHasSop(pNtk) || Abc_NtkHasBlifMv(pNtk) )
Extra_MmFlexStop( pNtk->pManFunc );
else if ( Abc_NtkHasBdd(pNtk) )
Extra_StopManager( pNtk->pManFunc );
else if ( Abc_NtkHasAig(pNtk) )
@ -877,6 +872,7 @@ void Abc_NtkDelete( Abc_Ntk_t * pNtk )
***********************************************************************/
void Abc_NtkFixNonDrivenNets( Abc_Ntk_t * pNtk )
{
char Buffer[10];
Vec_Ptr_t * vNets;
Abc_Obj_t * pNet, * pNode;
int i;
@ -894,26 +890,31 @@ void Abc_NtkFixNonDrivenNets( Abc_Ntk_t * pNtk )
if ( Abc_ObjFaninNum(pNet) > 0 )
continue;
// add the constant 0 driver
pNode = Abc_NtkCreateNodeConst0( pNtk );
if ( Abc_NtkHasBlifMv(pNtk) )
{
pNode = Abc_NtkCreateNode( pNtk );
sprintf( Buffer, "%d\n0\n", Abc_ObjMvVarNum(pNet) );
pNode->pData = Abc_SopRegister( pNtk->pManFunc, Buffer );
}
else
pNode = Abc_NtkCreateNodeConst0( pNtk );
// add the fanout net
Abc_ObjAddFanin( pNet, pNode );
// add the net to those for which the warning will be printed
Vec_PtrPush( vNets, pNet->pData );
Vec_PtrPush( vNets, pNet );
}
// print the warning
if ( vNets->nSize > 0 )
{
printf( "Constant-zero drivers were added to %d non-driven nets in network %s:\n", vNets->nSize, pNtk->pName );
for ( i = 0; i < vNets->nSize; i++ )
printf( "Constant-0 drivers added to %d non-driven nets in network \"%s\":\n", Vec_PtrSize(vNets), pNtk->pName );
Vec_PtrForEachEntry( vNets, pNet, i )
{
if ( i == 0 )
printf( "%s", vNets->pArray[i] );
else if ( i == 1 )
printf( ", %s", vNets->pArray[i] );
else if ( i == 2 )
printf( "%s%s", (i? ", ": ""), Abc_ObjName(pNet) );
if ( i == 3 )
{
printf( ", %s, etc.", vNets->pArray[i] );
if ( Vec_PtrSize(vNets) > 3 )
printf( " ..." );
break;
}
}
@ -923,6 +924,67 @@ void Abc_NtkFixNonDrivenNets( Abc_Ntk_t * pNtk )
}
/**Function*************************************************************
Synopsis [Converts the network to combinational.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkMakeComb( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pObj;
int i;
if ( Abc_NtkIsComb(pNtk) )
return;
assert( !Abc_NtkIsNetlist(pNtk) );
assert( Abc_NtkHasOnlyLatchBoxes(pNtk) );
// detach the latches
// Abc_NtkForEachLatch( pNtk, pObj, i )
Vec_PtrForEachEntryReverse( pNtk->vBoxes, pObj, i )
Abc_NtkDeleteObj( pObj );
assert( Abc_NtkLatchNum(pNtk) == 0 );
assert( Abc_NtkBoxNum(pNtk) == 0 );
// move CIs to become PIs
Vec_PtrClear( pNtk->vPis );
Abc_NtkForEachCi( pNtk, pObj, i )
{
if ( Abc_ObjIsBo(pObj) )
{
pObj->Type = ABC_OBJ_PI;
pNtk->nObjCounts[ABC_OBJ_PI]++;
pNtk->nObjCounts[ABC_OBJ_BO]--;
}
Vec_PtrPush( pNtk->vPis, pObj );
}
assert( Abc_NtkBoNum(pNtk) == 0 );
// move COs to become POs
Vec_PtrClear( pNtk->vPos );
Abc_NtkForEachCo( pNtk, pObj, i )
{
if ( Abc_ObjIsBi(pObj) )
{
pObj->Type = ABC_OBJ_PO;
pNtk->nObjCounts[ABC_OBJ_PO]++;
pNtk->nObjCounts[ABC_OBJ_BI]--;
}
Vec_PtrPush( pNtk->vPos, pObj );
}
assert( Abc_NtkBiNum(pNtk) == 0 );
if ( !Abc_NtkCheck( pNtk ) )
fprintf( stdout, "Abc_NtkMakeComb(): Network check has failed.\n" );
}
////////////////////////////////////////////////////////////////////////

4
src/base/abc/abcObj.c
View File

@ -335,7 +335,7 @@ Abc_Obj_t * Abc_NtkDupObj( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pObj, int fCopyName
{
if ( pNtkNew->ntkFunc == pObj->pNtk->ntkFunc )
{
if ( Abc_NtkIsStrash(pNtkNew) || Abc_NtkIsSeq(pNtkNew) )
if ( Abc_NtkIsStrash(pNtkNew) )
{}
else if ( Abc_NtkHasSop(pNtkNew) )
pObjNew->pData = Abc_SopRegister( pNtkNew->pManFunc, pObj->pData );
@ -436,7 +436,7 @@ Abc_Obj_t * Abc_NtkFindNode( Abc_Ntk_t * pNtk, char * pName )
// find the internal node
if ( pName[0] != '[' || pName[strlen(pName)-1] != ']' )
{
printf( "Name \"%s\" is not found among CIs/COs (internal name looks like this: \"[integer]\").\n", pName );
printf( "Name \"%s\" is not found among CIs/COs (internal names often look as \"[integer]\").\n", pName );
return NULL;
}
Num = atoi( pName + 1 );

2
src/base/abc/abcSop.c
View File

@ -28,7 +28,7 @@
01- 1
1-1 1
is the string: "01- 1/n1-1 1/n" where '/n' is a single char.
is the string: "01- 1\n1-1 1\n" where '\n' is a single char.
*/
////////////////////////////////////////////////////////////////////////

154
src/base/abc/abcUtil.c
View File

@ -53,6 +53,43 @@ void * Abc_NtkAttrFree( Abc_Ntk_t * pNtk, int Attr, int fFreeMan )
return pUserMan;
}
/**Function*************************************************************
Synopsis [Starts the Mv-Var manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkStartMvVars( Abc_Ntk_t * pNtk )
{
Vec_Att_t * pAttMan;
assert( Abc_NtkMvVar(pNtk) == NULL );
pAttMan = Vec_AttAlloc( 0, Abc_NtkObjNumMax(pNtk) + 1, Extra_MmFlexStart(), Extra_MmFlexStop, NULL, NULL );
Vec_PtrWriteEntry( pNtk->vAttrs, VEC_ATTR_MVVAR, pAttMan );
}
/**Function*************************************************************
Synopsis [Stops the Mv-Var manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkFreeMvVars( Abc_Ntk_t * pNtk )
{
void * pUserMan;
pUserMan = Abc_NtkAttrFree( pNtk, VEC_ATTR_GLOBAL_BDD, 0 );
Extra_MmFlexStop( pUserMan );
}
/**Function*************************************************************
Synopsis [Increments the current traversal ID of the network.]
@ -422,11 +459,75 @@ int Abc_NtkGetFaninMax( Abc_Ntk_t * pNtk )
void Abc_NtkCleanCopy( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pObj;
int i = 0;
int i;
Abc_NtkForEachObj( pNtk, pObj, i )
pObj->pCopy = NULL;
}
/**Function*************************************************************
Synopsis [Counts the number of nodes having non-trivial copies.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkCountCopy( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pObj;
int i, Counter = 0;
Abc_NtkForEachObj( pNtk, pObj, i )
{
if ( Abc_ObjIsNode(pObj) )
Counter += (pObj->pCopy != NULL);
}
return Counter;
}
/**Function*************************************************************
Synopsis [Saves copy field of the objects.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Abc_NtkSaveCopy( Abc_Ntk_t * pNtk )
{
Vec_Ptr_t * vCopies;
Abc_Obj_t * pObj;
int i;
vCopies = Vec_PtrStart( Abc_NtkObjNumMax(pNtk) );
Abc_NtkForEachObj( pNtk, pObj, i )
Vec_PtrWriteEntry( vCopies, i, pObj->pCopy );
return vCopies;
}
/**Function*************************************************************
Synopsis [Loads copy field of the objects.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkLoadCopy( Abc_Ntk_t * pNtk, Vec_Ptr_t * vCopies )
{
Abc_Obj_t * pObj;
int i;
Abc_NtkForEachObj( pNtk, pObj, i )
pObj->pCopy = Vec_PtrEntry( vCopies, i );
}
/**Function*************************************************************
Synopsis [Cleans the copy field of all objects.]
@ -957,16 +1058,8 @@ int Abc_NtkPrepareTwoNtks( FILE * pErr, Abc_Ntk_t * pNtk, char ** argv, int argc
}
else
fclose( pFile );
/*
if ( Abc_NtkIsSeq(pNtk) )
{
pNtk1 = Abc_NtkSeqToLogicSop(pNtk);
*pfDelete1 = 1;
}
else
*/
pNtk1 = pNtk;
pNtk2 = Io_Read( pNtk->pSpec, fCheck );
pNtk1 = pNtk;
pNtk2 = Io_Read( pNtk->pSpec, Io_ReadFileType(pNtk->pSpec), fCheck );
if ( pNtk2 == NULL )
return 0;
*pfDelete2 = 1;
@ -978,26 +1071,18 @@ int Abc_NtkPrepareTwoNtks( FILE * pErr, Abc_Ntk_t * pNtk, char ** argv, int argc
fprintf( pErr, "Empty current network.\n" );
return 0;
}
/*
if ( Abc_NtkIsSeq(pNtk) )
{
pNtk1 = Abc_NtkSeqToLogicSop(pNtk);
*pfDelete1 = 1;
}
else
*/
pNtk1 = pNtk;
pNtk2 = Io_Read( argv[util_optind], fCheck );
pNtk1 = pNtk;
pNtk2 = Io_Read( argv[util_optind], Io_ReadFileType(argv[util_optind]), fCheck );
if ( pNtk2 == NULL )
return 0;
*pfDelete2 = 1;
}
else if ( argc == util_optind + 2 )
{
pNtk1 = Io_Read( argv[util_optind], fCheck );
pNtk1 = Io_Read( argv[util_optind], Io_ReadFileType(argv[util_optind]), fCheck );
if ( pNtk1 == NULL )
return 0;
pNtk2 = Io_Read( argv[util_optind+1], fCheck );
pNtk2 = Io_Read( argv[util_optind+1], Io_ReadFileType(argv[util_optind+1]), fCheck );
if ( pNtk2 == NULL )
{
Abc_NtkDelete( pNtk1 );
@ -1342,6 +1427,29 @@ int Abc_ObjPointerCompare( void ** pp1, void ** pp2 )
return 0;
}
/**Function*************************************************************
Synopsis [Adjusts the copy pointers.]
Description [This procedure assumes that the network was transformed
into another network, which was in turn transformed into yet another
network. It makes the pCopy pointers of the original network point to
the objects of the yet another network.]
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkTransferCopy( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pObj;
int i;
Abc_NtkForEachObj( pNtk, pObj, i )
if ( !Abc_ObjIsNet(pObj) )
pObj->pCopy = pObj->pCopy? Abc_ObjEquiv(pObj->pCopy) : NULL;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

665
src/base/abci/abc.c
View File

File diff suppressed because it is too large Load Diff

2
src/base/abci/abcAttach.c
View File

@ -142,7 +142,7 @@ int Abc_NtkAttach( Abc_Ntk_t * pNtk )
Abc_NtkForEachNode( pNtk, pNode, i )
pNode->pData = pNode->pCopy, pNode->pCopy = NULL;
pNtk->ntkFunc = ABC_FUNC_MAP;
Extra_MmFlexStop( pNtk->pManFunc, 0 );
Extra_MmFlexStop( pNtk->pManFunc );
pNtk->pManFunc = pGenlib;
printf( "Library gates are successfully attached to the nodes.\n" );

1
src/base/abci/abcCut.c
View File

@ -20,7 +20,6 @@
#include "abc.h"
#include "cut.h"
//#include "seqInt.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///

209
src/base/abci/abcDress.c Normal file
View File

@ -0,0 +1,209 @@
/**CFile****************************************************************
FileName [abcDress.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Network and node package.]
Synopsis [Transfers names from one netlist to the other.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: abcDress.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "abc.h"
#include "io.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
static stmm_table * Abc_NtkDressDeriveMapping( Abc_Ntk_t * pNtk );
static void Abc_NtkDressTransferNames( Abc_Ntk_t * pNtk, stmm_table * tMapping, int fVerbose );
extern Abc_Ntk_t * Abc_NtkIvyFraig( Abc_Ntk_t * pNtk, int nConfLimit, int fDoSparse, int fProve, int fTransfer, int fVerbose );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Transfers names from one netlist to the other.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkDress( Abc_Ntk_t * pNtkLogic, char * pFileName, int fVerbose )
{
Abc_Ntk_t * pNtkOrig, * pNtkLogicOrig;
Abc_Ntk_t * pMiter, * pMiterFraig;
stmm_table * tMapping;
assert( Abc_NtkIsLogic(pNtkLogic) );
// get the original netlist
pNtkOrig = Io_ReadNetlist( pFileName, Io_ReadFileType(pFileName), 1 );
if ( pNtkOrig == NULL )
return;
assert( Abc_NtkIsNetlist(pNtkOrig) );
Abc_NtkCleanCopy(pNtkLogic);
Abc_NtkCleanCopy(pNtkOrig);
// convert it into the logic network
pNtkLogicOrig = Abc_NtkNetlistToLogic( pNtkOrig );
// check that the networks have the same PIs/POs/latches
if ( !Abc_NtkCompareSignals( pNtkLogic, pNtkLogicOrig, 1, 1 ) )
{
Abc_NtkDelete( pNtkOrig );
Abc_NtkDelete( pNtkLogicOrig );
return;
}
// convert the current logic network into an AIG
pMiter = Abc_NtkStrash( pNtkLogic, 1, 0 );
// convert it into the AIG and make the netlist point to the AIG
Abc_NtkAppend( pMiter, pNtkLogicOrig, 1 );
Abc_NtkTransferCopy( pNtkOrig );
Abc_NtkDelete( pNtkLogicOrig );
if ( fVerbose )
{
printf( "After mitering:\n" );
printf( "Logic: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkLogic), Abc_NtkCountCopy(pNtkLogic) );
printf( "Orig: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkOrig), Abc_NtkCountCopy(pNtkOrig) );
}
// fraig the miter (miter nodes point to the fraiged miter)
pMiterFraig = Abc_NtkIvyFraig( pMiter, 100, 1, 0, 1, 0 );
// make netlists point to the fraiged miter
Abc_NtkTransferCopy( pNtkLogic );
Abc_NtkTransferCopy( pNtkOrig );
Abc_NtkDelete( pMiter );
if ( fVerbose )
{
printf( "After fraiging:\n" );
printf( "Logic: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkLogic), Abc_NtkCountCopy(pNtkLogic) );
printf( "Orig: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkOrig), Abc_NtkCountCopy(pNtkOrig) );
}
// derive mapping from the fraiged nodes into their prototype nodes in the original netlist
tMapping = Abc_NtkDressDeriveMapping( pNtkOrig );
// transfer the names to the new netlist
Abc_NtkDressTransferNames( pNtkLogic, tMapping, fVerbose );
// clean up
stmm_free_table( tMapping );
Abc_NtkDelete( pMiterFraig );
Abc_NtkDelete( pNtkOrig );
}
/**Function*************************************************************
Synopsis [Returns the mapping from the fraig nodes point into the nodes of the netlist.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
stmm_table * Abc_NtkDressDeriveMapping( Abc_Ntk_t * pNtk )
{
stmm_table * tResult;
Abc_Obj_t * pNode, * pNodeMap, * pNodeFraig;
int i;
assert( Abc_NtkIsNetlist(pNtk) );
tResult = stmm_init_table(stmm_ptrcmp,stmm_ptrhash);
Abc_NtkForEachNode( pNtk, pNode, i )
{
// get the fraiged node
pNodeFraig = Abc_ObjRegular(pNode->pCopy);
// if this node is already mapped, skip
if ( stmm_is_member( tResult, (char *)pNodeFraig ) )
continue;
// get the mapping of this node
pNodeMap = Abc_ObjNotCond( pNode, Abc_ObjIsComplement(pNode->pCopy) );
// add the mapping
stmm_insert( tResult, (char *)pNodeFraig, (char *)pNodeMap );
}
return tResult;
}
/**Function*************************************************************
Synopsis [Attaches the names of to the new netlist.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkDressTransferNames( Abc_Ntk_t * pNtk, stmm_table * tMapping, int fVerbose )
{
Abc_Obj_t * pNet, * pNode, * pNodeMap, * pNodeFraig;
char * pName;
int i, Counter = 0, CounterInv = 0, CounterInit = stmm_count(tMapping);
assert( Abc_NtkIsLogic(pNtk) );
Abc_NtkForEachNode( pNtk, pNode, i )
{
// if the node already has a name, quit
pName = Nm_ManFindNameById( pNtk->pManName, pNode->Id );
if ( pName != NULL )
continue;
// get the fraiged node
pNodeFraig = Abc_ObjRegular(pNode->pCopy);
// find the matching node of the original netlist
if ( !stmm_lookup( tMapping, (char *)pNodeFraig, (char **)&pNodeMap ) )
continue;
// find the true match
pNodeMap = Abc_ObjNotCond( pNodeMap, Abc_ObjIsComplement(pNode->pCopy) );
// get the name
pNet = Abc_ObjFanout0(Abc_ObjRegular(pNodeMap));
pName = Nm_ManFindNameById( pNet->pNtk->pManName, pNet->Id );
assert( pName != NULL );
// set the name
if ( Abc_ObjIsComplement(pNodeMap) )
{
Abc_ObjAssignName( pNode, pName, "_inv" );
CounterInv++;
}
else
{
Abc_ObjAssignName( pNode, pName, NULL );
Counter++;
}
// remove the name
stmm_delete( tMapping, (char **)&pNodeFraig, (char **)&pNodeMap );
}
if ( fVerbose )
{
printf( "Total number of names collected = %5d.\n", CounterInit );
printf( "Total number of names assigned = %5d. (Dir = %5d. Compl = %5d.)\n",
Counter + CounterInv, Counter, CounterInv );
}
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

74
src/base/abci/abcIvy.c
View File

@ -76,7 +76,6 @@ Ivy_Man_t * Abc_NtkIvyBefore( Abc_Ntk_t * pNtk, int fSeq, int fUseDc )
int fCleanup = 1;
//timeRetime = clock();
assert( !Abc_NtkIsNetlist(pNtk) );
assert( !Abc_NtkIsSeq(pNtk) );
if ( Abc_NtkIsBddLogic(pNtk) )
{
if ( !Abc_NtkBddToSop(pNtk, 0) )
@ -371,6 +370,43 @@ Abc_Ntk_t * Abc_NtkIvySat( Abc_Ntk_t * pNtk, int nConfLimit, int fVerbose )
return pNtkAig;
}
/**Function*************************************************************
Synopsis [Sets the final nodes to point to the original nodes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkTransferPointers( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkAig )
{
Abc_Obj_t * pObj;
Ivy_Obj_t * pObjIvy, * pObjFraig;
int i;
pObj = Abc_AigConst1(pNtk);
pObj->pCopy = Abc_AigConst1(pNtkAig);
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->pCopy = Abc_NtkCi(pNtkAig, i);
Abc_NtkForEachCo( pNtk, pObj, i )
pObj->pCopy = Abc_NtkCo(pNtkAig, i);
Abc_NtkForEachLatch( pNtk, pObj, i )
pObj->pCopy = Abc_NtkBox(pNtkAig, i);
Abc_NtkForEachNode( pNtk, pObj, i )
{
pObjIvy = (Ivy_Obj_t *)pObj->pCopy;
if ( pObjIvy == NULL )
continue;
pObjFraig = Ivy_ObjEquiv( pObjIvy );
if ( pObjFraig == NULL )
continue;
pObj->pCopy = Abc_EdgeToNode( pNtkAig, Ivy_Regular(pObjFraig)->TravId );
pObj->pCopy = Abc_ObjNotCond( pObj->pCopy, Ivy_IsComplement(pObjFraig) );
}
}
/**Function*************************************************************
Synopsis [Gives the current ABC network to AIG manager for processing.]
@ -382,7 +418,7 @@ Abc_Ntk_t * Abc_NtkIvySat( Abc_Ntk_t * pNtk, int nConfLimit, int fVerbose )
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkIvyFraig( Abc_Ntk_t * pNtk, int nConfLimit, int fDoSparse, int fProve, int fVerbose )
Abc_Ntk_t * Abc_NtkIvyFraig( Abc_Ntk_t * pNtk, int nConfLimit, int fDoSparse, int fProve, int fTransfer, int fVerbose )
{
Ivy_FraigParams_t Params, * pParams = &Params;
Abc_Ntk_t * pNtkAig;
@ -396,8 +432,19 @@ Abc_Ntk_t * Abc_NtkIvyFraig( Abc_Ntk_t * pNtk, int nConfLimit, int fDoSparse, in
pParams->fProve = fProve;
pParams->fDoSparse = fDoSparse;
pMan = Ivy_FraigPerform( pTemp = pMan, pParams );
// transfer the pointers
if ( fTransfer == 1 )
{
Vec_Ptr_t * vCopies;
vCopies = Abc_NtkSaveCopy( pNtk );
pNtkAig = Abc_NtkIvyAfter( pNtk, pMan, 0, 0 );
Abc_NtkLoadCopy( pNtk, vCopies );
Vec_PtrFree( vCopies );
Abc_NtkTransferPointers( pNtk, pNtkAig );
}
else
pNtkAig = Abc_NtkIvyAfter( pNtk, pMan, 0, 0 );
Ivy_ManStop( pTemp );
pNtkAig = Abc_NtkIvyAfter( pNtk, pMan, 0, 0 );
Ivy_ManStop( pMan );
return pNtkAig;
}
@ -417,6 +464,7 @@ int Abc_NtkIvyProve( Abc_Ntk_t ** ppNtk, void * pPars )
{
Prove_Params_t * pParams = pPars;
Abc_Ntk_t * pNtk = *ppNtk, * pNtkTemp;
Abc_Obj_t * pObj, * pFanin;
Ivy_Man_t * pMan;
int RetValue;
assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) );
@ -432,6 +480,16 @@ int Abc_NtkIvyProve( Abc_Ntk_t ** ppNtk, void * pPars )
Abc_NtkDelete( pNtkTemp );
}
// check the case when the 0000 simulation pattern detect the bug
pObj = Abc_NtkPo(pNtk,0);
pFanin = Abc_ObjFanin0(pObj);
if ( Abc_ObjFanin0(pObj)->fPhase != (unsigned)Abc_ObjFaninC0(pObj) )
{
pNtk->pModel = ALLOC( int, Abc_NtkPiNum(pNtk) );
memset( pNtk->pModel, 0, sizeof(int) * Abc_NtkPiNum(pNtk) );
return 0;
}
// if SAT only, solve without iteration
RetValue = Abc_NtkMiterSat( pNtk, 2*(sint64)pParams->nMiteringLimitStart, (sint64)0, 0, 0, NULL, NULL );
if ( RetValue >= 0 )
@ -441,15 +499,16 @@ int Abc_NtkIvyProve( Abc_Ntk_t ** ppNtk, void * pPars )
if ( pParams->fUseRewriting && Abc_NtkNodeNum(pNtk) > 500 )
{
pParams->fUseRewriting = 0;
Abc_NtkRewrite( pNtk, 0, 0, 0 );
Abc_NtkRewrite( pNtk, 0, 0, 0, 0 );
pNtk = Abc_NtkBalance( pNtkTemp = pNtk, 0, 0, 0 );
Abc_NtkDelete( pNtkTemp );
Abc_NtkRewrite( pNtk, 0, 0, 0 );
Abc_NtkRewrite( pNtk, 0, 0, 0, 0 );
Abc_NtkRefactor( pNtk, 10, 16, 0, 0, 0, 0 );
}
// convert ABC network into IVY network
pMan = Abc_NtkIvyBefore( pNtk, 0, 0 );
// solve the CEC problem
RetValue = Ivy_FraigProve( &pMan, pParams );
// convert IVY network into ABC network
@ -503,7 +562,6 @@ Abc_Ntk_t * Abc_NtkIvy( Abc_Ntk_t * pNtk )
Vec_Int_t * vInit = Abc_NtkCollectLatchValuesIvy( pNtk, 0 );
assert( !Abc_NtkIsNetlist(pNtk) );
assert( !Abc_NtkIsSeq(pNtk) );
if ( Abc_NtkIsBddLogic(pNtk) )
{
if ( !Abc_NtkBddToSop(pNtk, 0) )
@ -624,14 +682,14 @@ Abc_Ntk_t * Abc_NtkFromAig( Abc_Ntk_t * pNtkOld, Ivy_Man_t * pMan )
vNodes = Ivy_ManDfs( pMan );
Ivy_ManForEachNodeVec( pMan, vNodes, pNode, i )
{
// add the first fanins
// add the first fanin
pFaninNew0 = Abc_ObjFanin0Ivy( pNtk, pNode );
if ( Ivy_ObjIsBuf(pNode) )
{
pNode->TravId = Abc_EdgeFromNode( pFaninNew0 );
continue;
}
// add the first second
// add the second fanin
pFaninNew1 = Abc_ObjFanin1Ivy( pNtk, pNode );
// create the new node
if ( Ivy_ObjIsExor(pNode) )

6
src/base/abci/abcMiter.c
View File

@ -1028,6 +1028,12 @@ int Abc_NtkDemiter( Abc_Ntk_t * pNtk )
printf( "First cone = %6d. Second cone = %6d. Common = %6d.\n", vNodes1->nSize, vNodes2->nSize, nCommon );
Vec_PtrFree( vNodes1 );
Vec_PtrFree( vNodes2 );
// reorder the latches
Abc_NtkOrderCisCos( pNtk );
// make sure that everything is okay
if ( !Abc_NtkCheck( pNtk ) )
printf( "Abc_NtkDemiter: The network check has failed.\n" );
return 1;
}

2
src/base/abci/abcNtbdd.c
View File

@ -256,7 +256,7 @@ DdManager * Abc_NtkBuildGlobalBdds( Abc_Ntk_t * pNtk, int nBddSizeMax, int fDrop
Abc_AigCleanup( pNtk->pManFunc );
// start the manager
assert( Abc_NtkGlobalBdds(pNtk) == NULL );
assert( Abc_NtkGlobalBdd(pNtk) == NULL );
dd = Cudd_Init( Abc_NtkCiNum(pNtk), 0, CUDD_UNIQUE_SLOTS, CUDD_CACHE_SLOTS, 0 );
pAttMan = Vec_AttAlloc( 0, Abc_NtkObjNumMax(pNtk) + 1, dd, Extra_StopManager, NULL, Cudd_RecursiveDeref );
Vec_PtrWriteEntry( pNtk->vAttrs, VEC_ATTR_GLOBAL_BDD, pAttMan );

154
src/base/abci/abcPga.c
View File

@ -1,154 +0,0 @@
/**CFile****************************************************************
FileName [abcPga.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Network and node package.]
Synopsis [Interface with the FPGA mapping package.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: abcPga.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "abc.h"
#include "fraig.h"
#include "fpga.h"
#include "pga.h"
#include "cut.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
static Abc_Ntk_t * Abc_NtkFromPga( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodeCuts );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Interface with the FPGA mapping package.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkPga( Pga_Params_t * pParams )
{
Abc_Ntk_t * pNtkNew, * pNtk = pParams->pNtk;
Pga_Man_t * pMan;
Vec_Ptr_t * vNodeCuts;
assert( Abc_NtkIsStrash(pNtk) );
// print a warning about choice nodes
if ( Abc_NtkGetChoiceNum( pNtk ) )
printf( "Performing FPGA mapping with choices.\n" );
// start the mapping manager
pMan = Pga_ManStart( pParams );
if ( pMan == NULL )
return NULL;
// perform mapping
vNodeCuts = Pga_DoMapping( pMan );
// transform the result of mapping into a BDD logic network
pNtkNew = Abc_NtkFromPga( pNtk, vNodeCuts );
if ( pNtkNew == NULL )
return NULL;
Pga_ManStop( pMan );
Vec_PtrFree( vNodeCuts );
// make the network minimum base
Abc_NtkMinimumBase( pNtkNew );
if ( pNtk->pExdc )
pNtkNew->pExdc = Abc_NtkDup( pNtk->pExdc );
// make sure that everything is okay
if ( !Abc_NtkCheck( pNtkNew ) )
{
printf( "Abc_NtkPga: The network check has failed.\n" );
Abc_NtkDelete( pNtkNew );
return NULL;
}
return pNtkNew;
}
/**Function*************************************************************
Synopsis [Creates the mapped network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkFromPga( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodeCuts )
{
ProgressBar * pProgress;
DdManager * dd;
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pNode, * pFanin, * pNodeNew;
Cut_Cut_t * pCut;
Vec_Ptr_t * vLeaves, * vVisited;
int i, k, nDupGates;
// create the new network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_BDD );
dd = pNtkNew->pManFunc;
// add new nodes in topologic order
vLeaves = Vec_PtrAlloc( 6 );
vVisited = Vec_PtrAlloc( 100 );
pProgress = Extra_ProgressBarStart( stdout, Vec_PtrSize(vNodeCuts) );
Vec_PtrForEachEntry( vNodeCuts, pCut, i )
{
Extra_ProgressBarUpdate( pProgress, i, NULL );
// create the new node
pNodeNew = Abc_NtkCreateNode( pNtkNew );
Vec_PtrClear( vLeaves );
for ( k = 0; k < (int)pCut->nLeaves; k++ )
{
// add the node representing the old fanin in the new network
pFanin = Abc_NtkObj( pNtk, pCut->pLeaves[k] );
Vec_PtrPush( vLeaves, pFanin );
Abc_ObjAddFanin( pNodeNew, pFanin->pCopy );
}
// set the new node at the old node
pNode = Abc_NtkObj( pNtk, pCut->uSign ); // pCut->uSign contains the ID of the root node
pNode->pCopy = pNodeNew;
// create the function of the new node
pNodeNew->pData = Abc_NodeConeBdd( dd, dd->vars, pNode, vLeaves, vVisited ); Cudd_Ref( pNodeNew->pData );
}
Extra_ProgressBarStop( pProgress );
Vec_PtrFree( vVisited );
Vec_PtrFree( vLeaves );
// finalize the new network
Abc_NtkFinalize( pNtk, pNtkNew );
// decouple the PO driver nodes to reduce the number of levels
nDupGates = Abc_NtkLogicMakeSimpleCos( pNtkNew, 1 );
// if ( nDupGates && Fpga_ManReadVerbose(pMan) )
// printf( "Duplicated %d gates to decouple the CO drivers.\n", nDupGates );
return pNtkNew;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

28
src/base/abci/abcPrint.c
View File

@ -51,28 +51,20 @@ int s_MappingMem = 0;
***********************************************************************/
void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
{
int Num;//, Num2;
// Abc_NtkDetectMatching( pNtk );
// return;
int Num;
fprintf( pFile, "%-13s:", pNtk->pName );
if ( Abc_NtkAssertNum(pNtk) )
fprintf( pFile, " i/o/a = %4d/%4d/%4d", Abc_NtkPiNum(pNtk), Abc_NtkPoNum(pNtk), Abc_NtkAssertNum(pNtk) );
else
fprintf( pFile, " i/o = %4d/%4d", Abc_NtkPiNum(pNtk), Abc_NtkPoNum(pNtk) );
// if ( !Abc_NtkIsSeq(pNtk) )
fprintf( pFile, " lat = %4d", Abc_NtkLatchNum(pNtk) );
// else
// fprintf( pFile, " lat = %4d(%d,%d)", Seq_NtkLatchNum(pNtk), Seq_NtkLatchNumShared(pNtk), Seq_NtkLatchNumMax(pNtk) );
fprintf( pFile, " lat = %4d", Abc_NtkLatchNum(pNtk) );
if ( Abc_NtkIsNetlist(pNtk) )
{
fprintf( pFile, " net = %5d", Abc_NtkNetNum(pNtk) );
fprintf( pFile, " nd = %5d", Abc_NtkNodeNum(pNtk) );
fprintf( pFile, " box = %5d", Abc_NtkBoxNum(pNtk) );
}
else if ( Abc_NtkIsStrash(pNtk) || Abc_NtkIsSeq(pNtk) )
else if ( Abc_NtkIsStrash(pNtk) )
{
fprintf( pFile, " and = %5d", Abc_NtkNodeNum(pNtk) );
if ( Num = Abc_NtkGetChoiceNum(pNtk) )
@ -87,7 +79,7 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
else
fprintf( pFile, " nd = %5d", Abc_NtkNodeNum(pNtk) );
if ( Abc_NtkIsStrash(pNtk) || Abc_NtkIsSeq(pNtk) || Abc_NtkIsNetlist(pNtk) )
if ( Abc_NtkIsStrash(pNtk) || Abc_NtkIsNetlist(pNtk) )
{
}
else if ( Abc_NtkHasSop(pNtk) )
@ -114,7 +106,7 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
if ( Abc_NtkIsStrash(pNtk) )
fprintf( pFile, " lev = %3d", Abc_AigLevel(pNtk) );
else if ( !Abc_NtkIsSeq(pNtk) )
else
fprintf( pFile, " lev = %3d", Abc_NtkLevel(pNtk) );
fprintf( pFile, "\n" );
@ -260,16 +252,6 @@ void Abc_NtkPrintLatch( FILE * pFile, Abc_Ntk_t * pNtk )
int InitNums[4], Init;
assert( !Abc_NtkIsNetlist(pNtk) );
/*
if ( Abc_NtkIsSeq(pNtk) )
{
Seq_NtkLatchGetInitNums( pNtk, InitNums );
fprintf( pFile, "%-15s: ", pNtk->pName );
fprintf( pFile, "Latch = %6d. No = %4d. Zero = %4d. One = %4d. DC = %4d.\n",
Abc_NtkLatchNum(pNtk), InitNums[0], InitNums[1], InitNums[2], InitNums[3] );
return;
}
*/
if ( Abc_NtkLatchNum(pNtk) == 0 )
{
fprintf( pFile, "The network is combinational.\n" );

9
src/base/abci/abcProve.c
View File

@ -26,7 +26,6 @@
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
extern int Abc_NtkRewrite( Abc_Ntk_t * pNtk, int fUpdateLevel, int fUseZeros, int fVerbose );
extern int Abc_NtkRefactor( Abc_Ntk_t * pNtk, int nNodeSizeMax, int nConeSizeMax, bool fUpdateLevel, bool fUseZeros, bool fUseDcs, bool fVerbose );
extern Abc_Ntk_t * Abc_NtkFromFraig( Fraig_Man_t * pMan, Abc_Ntk_t * pNtk );
@ -134,13 +133,13 @@ int Abc_NtkMiterProve( Abc_Ntk_t ** ppNtk, void * pPars )
break;
*/
/*
Abc_NtkRewrite( pNtk, 0, 0, 0 );
Abc_NtkRewrite( pNtk, 0, 0, 0, 0 );
if ( (RetValue = Abc_NtkMiterIsConstant(pNtk)) >= 0 )
break;
if ( --Counter == 0 )
break;
*/
Abc_NtkRewrite( pNtk, 0, 0, 0 );
Abc_NtkRewrite( pNtk, 0, 0, 0, 0 );
if ( (RetValue = Abc_NtkMiterIsConstant(pNtk)) >= 0 )
break;
if ( --Counter == 0 )
@ -329,9 +328,9 @@ void Abc_NtkMiterPrint( Abc_Ntk_t * pNtk, char * pString, int clk, int fVerbose
Abc_Ntk_t * Abc_NtkMiterRwsat( Abc_Ntk_t * pNtk )
{
Abc_Ntk_t * pNtkTemp;
Abc_NtkRewrite( pNtk, 0, 0, 0 );
Abc_NtkRewrite( pNtk, 0, 0, 0, 0 );
pNtk = Abc_NtkBalance( pNtkTemp = pNtk, 0, 0, 0 ); Abc_NtkDelete( pNtkTemp );
Abc_NtkRewrite( pNtk, 0, 0, 0 );
Abc_NtkRewrite( pNtk, 0, 0, 0, 0 );
Abc_NtkRefactor( pNtk, 10, 16, 0, 0, 0, 0 );
return pNtk;
}

7
src/base/abci/abcRewrite.c
View File

@ -51,7 +51,7 @@ static void Abc_ManShowCutCone( Abc_Obj_t * pNode, Vec_Ptr_t * vLeaves );
SeeAlso []
***********************************************************************/
int Abc_NtkRewrite( Abc_Ntk_t * pNtk, int fUpdateLevel, int fUseZeros, int fVerbose )
int Abc_NtkRewrite( Abc_Ntk_t * pNtk, int fUpdateLevel, int fUseZeros, int fVerbose, int fVeryVerbose )
{
ProgressBar * pProgress;
Cut_Man_t * pManCut;
@ -76,6 +76,9 @@ clk = clock();
Rwr_ManAddTimeCuts( pManRwr, clock() - clk );
pNtk->pManCut = pManCut;
if ( fVeryVerbose )
Rwr_ScoresClean( pManRwr );
// resynthesize each node once
nNodes = Abc_NtkObjNumMax(pNtk);
pProgress = Extra_ProgressBarStart( stdout, nNodes );
@ -147,6 +150,8 @@ Rwr_ManAddTimeTotal( pManRwr, clock() - clkStart );
if ( fVerbose )
Rwr_ManPrintStats( pManRwr );
// Rwr_ManPrintStatsFile( pManRwr );
if ( fVeryVerbose )
Rwr_ScoresReport( pManRwr );
// delete the managers
Rwr_ManStop( pManRwr );
Cut_ManStop( pManCut );

2
src/base/abci/abcStrash.c
View File

@ -285,7 +285,7 @@ Abc_Obj_t * Abc_NodeStrash( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld )
pMan = pNodeOld->pNtk->pManFunc;
pRoot = pNodeOld->pData;
// check the constant case
if ( Abc_NodeIsConst(pNodeOld) )
if ( Abc_NodeIsConst(pNodeOld) || Hop_Regular(pRoot) == Hop_ManConst1(pMan) )
return Abc_ObjNotCond( Abc_AigConst1(pNtkNew), Hop_IsComplement(pRoot) );
// set elementary variables
Abc_ObjForEachFanin( pNodeOld, pFanin, i )

14
src/base/abci/abcUnreach.c
View File

@ -280,7 +280,6 @@ DdNode * Abc_NtkComputeUnreachable( DdManager * dd, Abc_Ntk_t * pNtk, DdNode * b
***********************************************************************/
Abc_Ntk_t * Abc_NtkConstructExdc( DdManager * dd, Abc_Ntk_t * pNtk, DdNode * bUnreach )
{
/*
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pNode, * pNodeNew;
int * pPermute;
@ -292,14 +291,14 @@ Abc_Ntk_t * Abc_NtkConstructExdc( DdManager * dd, Abc_Ntk_t * pNtk, DdNode * bUn
pNtkNew->pSpec = NULL;
// create PIs corresponding to LOs
Abc_NtkForEachLatch( pNtk, pNode, i )
Abc_NtkForEachLatchOutput( pNtk, pNode, i )
Abc_ObjAssignName( pNode->pCopy = Abc_NtkCreatePi(pNtkNew), Abc_ObjName(pNode), NULL );
// cannot ADD POs here because pLatch->pCopy point to the PIs
// create a new node
pNodeNew = Abc_NtkCreateNode(pNtkNew);
// add the fanins corresponding to latch outputs
Abc_NtkForEachLatch( pNtk, pNode, i )
Abc_NtkForEachLatchOutput( pNtk, pNode, i )
Abc_ObjAddFanin( pNodeNew, pNode->pCopy );
// create the logic function
@ -317,14 +316,14 @@ Abc_Ntk_t * Abc_NtkConstructExdc( DdManager * dd, Abc_Ntk_t * pNtk, DdNode * bUn
Abc_NtkForEachPo( pNtk, pNode, i )
if ( !Abc_ObjIsCi(Abc_ObjFanin0(pNode)) )
Abc_ObjAssignName( pNode->pCopy = Abc_NtkCreatePo(pNtkNew), Abc_ObjName(pNode), NULL );
Abc_NtkForEachLatch( pNtk, pNode, i )
Abc_ObjAssignName( pNode->pCopy = Abc_NtkCreatePo(pNtkNew), Abc_ObjNameSuffix(pNode, "_in"), NULL );
Abc_NtkForEachLatchInput( pNtk, pNode, i )
Abc_ObjAssignName( pNode->pCopy = Abc_NtkCreatePo(pNtkNew), Abc_ObjName(pNode), NULL );
// link to the POs of the network
Abc_NtkForEachPo( pNtk, pNode, i )
if ( !Abc_ObjIsCi(Abc_ObjFanin0(pNode)) )
Abc_ObjAddFanin( pNode->pCopy, pNodeNew );
Abc_NtkForEachLatch( pNtk, pNode, i )
Abc_NtkForEachLatchInput( pNtk, pNode, i )
Abc_ObjAddFanin( pNode->pCopy, pNodeNew );
// remove the extra nodes
@ -340,8 +339,7 @@ Abc_Ntk_t * Abc_NtkConstructExdc( DdManager * dd, Abc_Ntk_t * pNtk, DdNode * bUn
return NULL;
}
return pNtkNew;
*/
return NULL;
// return NULL;
}
////////////////////////////////////////////////////////////////////////

1
src/base/abci/abcVerify.c
View File

@ -176,6 +176,7 @@ void Abc_NtkCecFraig( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int nSeconds, int fV
Prove_ParamsSetDefault( pParams );
pParams->nItersMax = 5;
// RetValue = Abc_NtkMiterProve( &pMiter, pParams );
// pParams->fVerbose = 1;
RetValue = Abc_NtkIvyProve( &pMiter, pParams );
if ( RetValue == -1 )
printf( "Networks are undecided (resource limits is reached).\n" );

1
src/base/abci/module.make
View File

@ -7,6 +7,7 @@ SRC += src/base/abci/abc.c \
src/base/abci/abcClpSop.c \
src/base/abci/abcCut.c \
src/base/abci/abcDebug.c \
src/base/abci/abcDress.c \
src/base/abci/abcDsd.c \
src/base/abci/abcEspresso.c \
src/base/abci/abcExtract.c \

23
src/base/cmd/cmd.c
View File

@ -518,25 +518,24 @@ int CmdCommandSource( Abc_Frame_t * pAbc, int argc, char **argv )
interactive = silent = prompt = echo = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "hipsx" ) ) != EOF )
while ( ( c = Extra_UtilGetopt( argc, argv, "ipsxh" ) ) != EOF )
{
switch ( c )
{
case 'h':
goto usage;
break;
case 'i': /* a hack to distinguish EOF from stdin */
interactive = 1;
break;
case 'p':
prompt = 1;
prompt ^= 1;
break;
case 's':
silent = 1;
silent ^= 1;
break;
case 'x':
echo ^= 1;
break;
case 'h':
goto usage;
default:
goto usage;
}
@ -664,11 +663,11 @@ int CmdCommandSource( Abc_Frame_t * pAbc, int argc, char **argv )
return status;
usage:
fprintf( pAbc->Err, "usage: source [-h] [-p] [-s] [-x] file_name\n" );
fprintf( pAbc->Err, "usage: source [-psxh] <file_name>\n" );
fprintf( pAbc->Err, "\t-p supply prompt before reading each line [default = %s]\n", prompt? "yes": "no" );
fprintf( pAbc->Err, "\t-s silently ignore nonexistant file [default = %s]\n", silent? "yes": "no" );
fprintf( pAbc->Err, "\t-x echo each line as it is executed [default = %s]\n", echo? "yes": "no" );
fprintf( pAbc->Err, "\t-h print the command usage\n" );
fprintf( pAbc->Err, "\t-p supply prompt before reading each line\n" );
fprintf( pAbc->Err, "\t-s silently ignore nonexistant file\n" );
fprintf( pAbc->Err, "\t-x echo each line as it is executed\n" );
return 1;
}
@ -1308,7 +1307,7 @@ int CmdCommandSis( Abc_Frame_t * pAbc, int argc, char **argv )
fclose( pFile );
// set the new network
pNtkNew = Io_Read( "_sis_out.blif", 1 );
pNtkNew = Io_Read( "_sis_out.blif", IO_FILE_BLIF, 1 );
// set the original spec of the new network
if ( pNtk->pSpec )
{
@ -1449,7 +1448,7 @@ int CmdCommandMvsis( Abc_Frame_t * pAbc, int argc, char **argv )
fclose( pFile );
// set the new network
pNtkNew = Io_Read( "_mvsis_out.blif", 1 );
pNtkNew = Io_Read( "_mvsis_out.blif", IO_FILE_BLIF, 1 );
// set the original spec of the new network
if ( pNtk->pSpec )
{

62
src/base/func/funcBlifMv.c Normal file
View File

@ -0,0 +1,62 @@
/**CFile****************************************************************
FileName [funcBlifMv.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Network and node package.]
Synopsis [Implementation of BLIF-MV representation of the nodes.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: funcBlifMv.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "abc.h"
/*
The BLIF-MV tables are represented using char * strings.
For example, the representation of the table
.table c d0 d1 x
.default 0
0 - - =d0
1 - 1 1
is the string: "2 2 2 2\n0\n0 - - =1\n1 - 1 1\n" where '\n' is a single char.
*/
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Hop_Obj_t * Abc_ConvertBlifMvToAig( Hop_Man_t * pMan, char * pSop )
{
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

1797
src/base/io/io.c
View File

File diff suppressed because it is too large Load Diff

84
src/base/io/io.h
View File

@ -39,6 +39,25 @@ extern "C" {
/// BASIC TYPES ///
////////////////////////////////////////////////////////////////////////
// network functionality
typedef enum {
IO_FILE_NONE = 0,
IO_FILE_AIGER,
IO_FILE_BAF,
IO_FILE_BLIF,
IO_FILE_BLIFMV,
IO_FILE_BENCH,
IO_FILE_CNF,
IO_FILE_DOT,
IO_FILE_EDIF,
IO_FILE_EQN,
IO_FILE_GML,
IO_FILE_LIST,
IO_FILE_PLA,
IO_FILE_VERILOG,
IO_FILE_UNKNOWN
} Io_FileType_t;
////////////////////////////////////////////////////////////////////////
/// MACRO DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
@ -49,59 +68,70 @@ extern "C" {
/// FUNCTION DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
/*=== abcRead.c ==========================================================*/
extern Abc_Ntk_t * Io_Read( char * pFileName, int fCheck );
/*=== abcReadAiger.c ==========================================================*/
extern Abc_Ntk_t * Io_ReadAiger( char * pFileName, int fCheck );
/*=== abcReadBaf.c ==========================================================*/
/*=== abcReadBaf.c ============================================================*/
extern Abc_Ntk_t * Io_ReadBaf( char * pFileName, int fCheck );
/*=== abcReadBlif.c ==========================================================*/
/*=== abcReadBlif.c ===========================================================*/
extern Abc_Ntk_t * Io_ReadBlif( char * pFileName, int fCheck );
/*=== abcReadBlifMv.c =========================================================*/
extern Abc_Lib_t * Io_ReadBlifMv( char * pFileName, int fBlifMv, int fCheck );
/*=== abcReadBench.c ==========================================================*/
extern Abc_Ntk_t * Io_ReadBench( char * pFileName, int fCheck );
/*=== abcReadEdif.c ==========================================================*/
/*=== abcReadEdif.c ===========================================================*/
extern Abc_Ntk_t * Io_ReadEdif( char * pFileName, int fCheck );
/*=== abcReadEqn.c ==========================================================*/
/*=== abcReadEqn.c ============================================================*/
extern Abc_Ntk_t * Io_ReadEqn( char * pFileName, int fCheck );
/*=== abcReadVerilog.c ==========================================================*/
/*=== abcReadVerilog.c ========================================================*/
extern Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck );
/*=== abcReadPla.c ==========================================================*/
/*=== abcReadPla.c ============================================================*/
extern Abc_Ntk_t * Io_ReadPla( char * pFileName, int fCheck );
/*=== abcUtil.c ==========================================================*/
extern Abc_Obj_t * Io_ReadCreatePi( Abc_Ntk_t * pNtk, char * pName );
extern Abc_Obj_t * Io_ReadCreatePo( Abc_Ntk_t * pNtk, char * pName );
extern Abc_Obj_t * Io_ReadCreateAssert( Abc_Ntk_t * pNtk, char * pName );
extern Abc_Obj_t * Io_ReadCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO );
extern Abc_Obj_t * Io_ReadCreateNode( Abc_Ntk_t * pNtk, char * pNameOut, char * pNamesIn[], int nInputs );
extern Abc_Obj_t * Io_ReadCreateConst( Abc_Ntk_t * pNtk, char * pName, bool fConst1 );
extern Abc_Obj_t * Io_ReadCreateInv( Abc_Ntk_t * pNtk, char * pNameIn, char * pNameOut );
extern Abc_Obj_t * Io_ReadCreateBuf( Abc_Ntk_t * pNtk, char * pNameIn, char * pNameOut );
extern FILE * Io_FileOpen( const char * FileName, const char * PathVar, const char * Mode, int fVerbose );
/*=== abcWriteAiger.c ==========================================================*/
/*=== abcWriteAiger.c =========================================================*/
extern void Io_WriteAiger( Abc_Ntk_t * pNtk, char * pFileName );
/*=== abcWriteBaf.c ==========================================================*/
/*=== abcWriteBaf.c ===========================================================*/
extern void Io_WriteBaf( Abc_Ntk_t * pNtk, char * pFileName );
/*=== abcWriteBlif.c ==========================================================*/
extern void Io_WriteBlifLogic( Abc_Ntk_t * pNtk, char * pFileName, int fWriteLatches );
extern void Io_WriteBlifNetlist( Abc_Ntk_t * pNtk, char * pFileName, int fWriteLatches );
extern void Io_WriteTimingInfo( FILE * pFile, Abc_Ntk_t * pNtk );
/*=== abcWriteBench.c ==========================================================*/
/*=== abcWriteBlifMv.c ==========================================================*/
extern void Io_WriteBlifMvDesign( Abc_Lib_t * pLib, char * FileName );
extern void Io_WriteBlifMvNetlist( Abc_Ntk_t * pNtk, char * FileName );
/*=== abcWriteBench.c =========================================================*/
extern int Io_WriteBench( Abc_Ntk_t * pNtk, char * FileName );
/*=== abcWriteCnf.c ==========================================================*/
/*=== abcWriteCnf.c ===========================================================*/
extern int Io_WriteCnf( Abc_Ntk_t * pNtk, char * FileName );
/*=== abcWriteDot.c ==========================================================*/
/*=== abcWriteDot.c ===========================================================*/
extern void Io_WriteDot( Abc_Ntk_t * pNtk, char * FileName );
extern void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesShow, char * pFileName, int fGateNames, int fUseReverse );
extern void Io_WriteDotSeq( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesShow, char * pFileName, int fGateNames, int fUseReverse );
/*=== abcWriteEqn.c ==========================================================*/
/*=== abcWriteEqn.c ===========================================================*/
extern void Io_WriteEqn( Abc_Ntk_t * pNtk, char * pFileName );
/*=== abcWriteGml.c ==========================================================*/
/*=== abcWriteGml.c ===========================================================*/
extern void Io_WriteGml( Abc_Ntk_t * pNtk, char * pFileName );
/*=== abcWriteList.c ==========================================================*/
extern void Io_WriteList( Abc_Ntk_t * pNtk, char * pFileName, int fUseHost );
/*=== abcWritePla.c ==========================================================*/
/*=== abcWritePla.c ===========================================================*/
extern int Io_WritePla( Abc_Ntk_t * pNtk, char * FileName );
/*=== abcWriteVerilog.c ==========================================================*/
/*=== abcWriteVerilog.c =======================================================*/
extern void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * FileName, int fVerLibStyle );
/*=== abcUtil.c ===============================================================*/
extern Io_FileType_t Io_ReadFileType( char * pFileName );
extern Abc_Ntk_t * Io_ReadNetlist( char * pFileName, Io_FileType_t FileType, int fCheck );
extern Abc_Ntk_t * Io_Read( char * pFileName, Io_FileType_t FileType, int fCheck );
extern void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType );
extern Abc_Obj_t * Io_ReadCreatePi( Abc_Ntk_t * pNtk, char * pName );
extern Abc_Obj_t * Io_ReadCreatePo( Abc_Ntk_t * pNtk, char * pName );
extern Abc_Obj_t * Io_ReadCreateAssert( Abc_Ntk_t * pNtk, char * pName );
extern Abc_Obj_t * Io_ReadCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO );
extern Abc_Obj_t * Io_ReadCreateResetLatch( Abc_Ntk_t * pNtk, int fBlifMv );
extern Abc_Obj_t * Io_ReadCreateResetMux( Abc_Ntk_t * pNtk, char * pResetLO, char * pDataLI, int fBlifMv );
extern Abc_Obj_t * Io_ReadCreateNode( Abc_Ntk_t * pNtk, char * pNameOut, char * pNamesIn[], int nInputs );
extern Abc_Obj_t * Io_ReadCreateConst( Abc_Ntk_t * pNtk, char * pName, bool fConst1 );
extern Abc_Obj_t * Io_ReadCreateInv( Abc_Ntk_t * pNtk, char * pNameIn, char * pNameOut );
extern Abc_Obj_t * Io_ReadCreateBuf( Abc_Ntk_t * pNtk, char * pNameIn, char * pNameOut );
extern FILE * Io_FileOpen( const char * FileName, const char * PathVar, const char * Mode, int fVerbose );
#ifdef __cplusplus
}

88
src/base/io/ioRead.c
View File

@ -1,88 +0,0 @@
/**CFile****************************************************************
FileName [ioRead.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Command processing package.]
Synopsis [Procedure to read network from file.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: ioRead.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "io.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Read the network from a file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Io_Read( char * pFileName, int fCheck )
{
Abc_Ntk_t * pNtk, * pTemp;
// extern int s_TotalNodes;
// extern int s_TotalChanges;
// s_TotalNodes = s_TotalChanges = 0;
// set the new network
if ( Extra_FileNameCheckExtension( pFileName, "blif" ) )
pNtk = Io_ReadBlif( pFileName, fCheck );
else if ( Extra_FileNameCheckExtension( pFileName, "v" ) )
pNtk = NULL; //Io_ReadVerilog( pFileName, fCheck );
else if ( Extra_FileNameCheckExtension( pFileName, "bench" ) )
pNtk = Io_ReadBench( pFileName, fCheck );
else if ( Extra_FileNameCheckExtension( pFileName, "edf" ) )
pNtk = Io_ReadEdif( pFileName, fCheck );
else if ( Extra_FileNameCheckExtension( pFileName, "pla" ) )
pNtk = Io_ReadPla( pFileName, fCheck );
else if ( Extra_FileNameCheckExtension( pFileName, "eqn" ) )
pNtk = Io_ReadEqn( pFileName, fCheck );
else if ( Extra_FileNameCheckExtension( pFileName, "baf" ) )
return Io_ReadBaf( pFileName, fCheck );
else if ( Extra_FileNameCheckExtension( pFileName, "aig" ) )
return Io_ReadAiger( pFileName, fCheck );
else
{
fprintf( stderr, "Unknown file format\n" );
return NULL;
}
if ( pNtk == NULL )
return NULL;
pNtk = Abc_NtkNetlistToLogic( pTemp = pNtk );
Abc_NtkDelete( pTemp );
if ( pNtk == NULL )
{
fprintf( stdout, "Converting to logic network after reading has failed.\n" );
return NULL;
}
return pNtk;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

8
src/base/io/ioReadAiger.c
View File

@ -63,7 +63,7 @@ Abc_Ntk_t * Io_ReadAiger( char * pFileName, int fCheck )
// check if the input file format is correct
if ( strncmp(pContents, "aig", 3) != 0 )
{
fprintf( stdout, "Wrong input file format." );
fprintf( stdout, "Wrong input file format.\n" );
return NULL;
}
@ -90,7 +90,7 @@ Abc_Ntk_t * Io_ReadAiger( char * pFileName, int fCheck )
// check the parameters
if ( nTotal != nInputs + nLatches + nAnds )
{
fprintf( stdout, "The paramters are wrong." );
fprintf( stdout, "The paramters are wrong.\n" );
return NULL;
}
@ -181,7 +181,7 @@ Abc_Ntk_t * Io_ReadAiger( char * pFileName, int fCheck )
vTerms = pNtkNew->vPos;
else
{
fprintf( stdout, "Wrong terminal type." );
fprintf( stdout, "Wrong terminal type.\n" );
return NULL;
}
// get the terminal number
@ -189,7 +189,7 @@ Abc_Ntk_t * Io_ReadAiger( char * pFileName, int fCheck )
// get the node
if ( iTerm >= Vec_PtrSize(vTerms) )
{
fprintf( stdout, "The number of terminal is out of bound." );
fprintf( stdout, "The number of terminal is out of bound.\n" );
return NULL;
}
pObj = Vec_PtrEntry( vTerms, iTerm );

16
src/base/io/ioReadBench.c
View File

@ -82,7 +82,7 @@ Abc_Ntk_t * Io_ReadBenchNetwork( Extra_FileReader_t * p )
ProgressBar * pProgress;
Vec_Ptr_t * vTokens;
Abc_Ntk_t * pNtk;
Abc_Obj_t * pNet, * pNode;
Abc_Obj_t * pNode;
Vec_Str_t * vString;
char * pType, ** ppNames;
int iLine, nNames;
@ -144,7 +144,11 @@ Abc_Ntk_t * Io_ReadBenchNetwork( Extra_FileReader_t * p )
Abc_ObjSetData( pNode, Abc_SopCreateInv(pNtk->pManFunc) );
else if ( strncmp(pType, "MUX", 3) == 0 )
Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, "1-0 1\n-11 1\n") );
else
else if ( strncmp(pType, "vdd", 3) == 0 )
Abc_ObjSetData( pNode, Abc_SopRegister( pNtk->pManFunc, " 1\n" ) );
else if ( strncmp(pType, "gnd", 3) == 0 )
Abc_ObjSetData( pNode, Abc_SopRegister( pNtk->pManFunc, " 0\n" ) );
else
{
printf( "Cannot determine gate type \"%s\" in line %d.\n", pType, Extra_FileReaderGetLineNumber(p, 0) );
Vec_StrFree( vString );
@ -158,10 +162,10 @@ Abc_Ntk_t * Io_ReadBenchNetwork( Extra_FileReader_t * p )
Vec_StrFree( vString );
// check if constant have been added
if ( pNet = Abc_NtkFindNet( pNtk, "vdd" ) )
Io_ReadCreateConst( pNtk, "vdd", 1 );
if ( pNet = Abc_NtkFindNet( pNtk, "gnd" ) )
Io_ReadCreateConst( pNtk, "gnd", 0 );
// if ( pNet = Abc_NtkFindNet( pNtk, "vdd" ) )
// Io_ReadCreateConst( pNtk, "vdd", 1 );
// if ( pNet = Abc_NtkFindNet( pNtk, "gnd" ) )
// Io_ReadCreateConst( pNtk, "gnd", 0 );
Abc_NtkFinalizeRead( pNtk );
return pNtk;

4
src/base/io/ioReadBlif.c
View File

@ -265,7 +265,7 @@ Abc_Ntk_t * Io_ReadBlifNetworkOne( Io_ReadBlif_t * p )
{
pNtk->ntkType = ABC_NTK_NETLIST;
pNtk->ntkFunc = ABC_FUNC_BLACKBOX;
Extra_MmFlexStop( pNtk->pManFunc, 0 );
Extra_MmFlexStop( pNtk->pManFunc );
pNtk->pManFunc = NULL;
}
else
@ -560,7 +560,7 @@ int Io_ReadBlifNetworkGate( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens )
{
assert( p->pNtkCur->ntkFunc == ABC_FUNC_SOP );
p->pNtkCur->ntkFunc = ABC_FUNC_MAP;
Extra_MmFlexStop( p->pNtkCur->pManFunc, 0 );
Extra_MmFlexStop( p->pNtkCur->pManFunc );
p->pNtkCur->pManFunc = pGenlib;
}

1013
src/base/io/ioReadBlifAig.c Normal file
View File

File diff suppressed because it is too large Load Diff

1469
src/base/io/ioReadBlifMv.c Normal file
View File

File diff suppressed because it is too large Load Diff

73
src/base/io/ioReadEqn.c
View File

@ -85,19 +85,20 @@ Abc_Ntk_t * Io_ReadEqnNetwork( Extra_FileReader_t * p )
{
ProgressBar * pProgress;
Vec_Ptr_t * vTokens;
Vec_Ptr_t * vCubes, * vLits, * vVars;
Vec_Ptr_t * vVars;
Abc_Ntk_t * pNtk;
Abc_Obj_t * pNode;
char * pCubesCopy, * pSopCube, * pVarName;
int iLine, iNum, i, k;
char * pNodeName, * pFormula, * pFormulaCopy, * pVarName;
int iLine, i;
// allocate the empty network
pNtk = Abc_NtkStartRead( Extra_FileReaderGetFileName(p) );
pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST, ABC_FUNC_AIG, 1 );
// set the specs
pNtk->pName = Extra_FileNameGeneric(Extra_FileReaderGetFileName(p));
pNtk->pSpec = Extra_UtilStrsav(Extra_FileReaderGetFileName(p));
// go through the lines of the file
vCubes = Vec_PtrAlloc( 100 );
vVars = Vec_PtrAlloc( 100 );
vLits = Vec_PtrAlloc( 100 );
pProgress = Extra_ProgressBarStart( stdout, Extra_FileReaderGetFileSize(p) );
for ( iLine = 0; vTokens = Extra_FileReaderGetTokens(p); iLine++ )
{
@ -131,52 +132,36 @@ Abc_Ntk_t * Io_ReadEqnNetwork( Extra_FileReader_t * p )
}
else
{
// remove spaces
pCubesCopy = vTokens->pArray[1];
Io_ReadEqnStrCompact( pCubesCopy );
extern Hop_Obj_t * Parse_FormulaParserEqn( FILE * pOutput, char * pFormInit, Vec_Ptr_t * vVarNames, Hop_Man_t * pMan );
// get hold of the node name and its formula
pNodeName = vTokens->pArray[0];
pFormula = vTokens->pArray[1];
// compact the formula
Io_ReadEqnStrCompact( pFormula );
// consider the case of the constant node
if ( (pCubesCopy[0] == '0' || pCubesCopy[0] == '1') && pCubesCopy[1] == 0 )
if ( pFormula[1] == 0 && (pFormula[0] == '0' || pFormula[0] == '1') )
{
pNode = Io_ReadCreateNode( pNtk, vTokens->pArray[0], NULL, 0 );
if ( pCubesCopy[0] == '0' )
pNode->pData = Abc_SopCreateConst0( pNtk->pManFunc );
else
pNode->pData = Abc_SopCreateConst1( pNtk->pManFunc );
continue;
pFormulaCopy = NULL;
Vec_PtrClear( vVars );
}
else
{
// make a copy of formula for names
pFormulaCopy = Extra_UtilStrsav( pFormula );
// find the names of the fanins of this node
Io_ReadEqnStrCutAt( pFormulaCopy, "!*+()", 1, vVars );
}
// determine unique variables
pCubesCopy = Extra_UtilStrsav( pCubesCopy );
// find the names of the fanins of this node
Io_ReadEqnStrCutAt( pCubesCopy, "!*+", 1, vVars );
// create the node
pNode = Io_ReadCreateNode( pNtk, vTokens->pArray[0], (char **)vVars->pArray, vVars->nSize );
// split the string into cubes
Io_ReadEqnStrCutAt( vTokens->pArray[1], "+", 0, vCubes );
// start the sop
pNode->pData = Abc_SopStart( pNtk->pManFunc, vCubes->nSize, vVars->nSize );
// read the cubes
i = 0;
Abc_SopForEachCube( pNode->pData, vVars->nSize, pSopCube )
{
// split this cube into lits
Io_ReadEqnStrCutAt( vCubes->pArray[i], "*", 0, vLits );
// read the literals
Vec_PtrForEachEntry( vLits, pVarName, k )
{
iNum = Io_ReadEqnStrFind( vVars, pVarName + (pVarName[0] == '!') );
assert( iNum >= 0 );
pSopCube[iNum] = '1' - (pVarName[0] == '!');
}
i++;
}
assert( i == vCubes->nSize );
pNode = Io_ReadCreateNode( pNtk, pNodeName, (char **)Vec_PtrArray(vVars), Vec_PtrSize(vVars) );
// derive the function
pNode->pData = Parse_FormulaParserEqn( stdout, pFormula, vVars, pNtk->pManFunc );
// remove the cubes
free( pCubesCopy );
FREE( pFormulaCopy );
}
}
Extra_ProgressBarStop( pProgress );
Vec_PtrFree( vCubes );
Vec_PtrFree( vLits );
Vec_PtrFree( vVars );
Abc_NtkFinalizeRead( pNtk );
return pNtk;

330
src/base/io/ioUtil.c
View File

@ -28,6 +28,269 @@
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Returns the file type.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Io_FileType_t Io_ReadFileType( char * pFileName )
{
char * pExt;
if ( pFileName == NULL )
return IO_FILE_NONE;
pExt = Extra_FileNameExtension( pFileName );
if ( pExt == NULL )
return IO_FILE_NONE;
if ( !strcmp( pExt, "aig" ) )
return IO_FILE_AIGER;
if ( !strcmp( pExt, "baf" ) )
return IO_FILE_BAF;
if ( !strcmp( pExt, "blif" ) )
return IO_FILE_BLIF;
if ( !strcmp( pExt, "bench" ) )
return IO_FILE_BENCH;
if ( !strcmp( pExt, "cnf" ) )
return IO_FILE_CNF;
if ( !strcmp( pExt, "dot" ) )
return IO_FILE_DOT;
if ( !strcmp( pExt, "edif" ) )
return IO_FILE_EDIF;
if ( !strcmp( pExt, "eqn" ) )
return IO_FILE_EQN;
if ( !strcmp( pExt, "gml" ) )
return IO_FILE_GML;
if ( !strcmp( pExt, "list" ) )
return IO_FILE_LIST;
if ( !strcmp( pExt, "mv" ) )
return IO_FILE_BLIFMV;
if ( !strcmp( pExt, "pla" ) )
return IO_FILE_PLA;
if ( !strcmp( pExt, "v" ) )
return IO_FILE_VERILOG;
return IO_FILE_UNKNOWN;
}
/**Function*************************************************************
Synopsis [Read the network from a file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Io_ReadNetlist( char * pFileName, Io_FileType_t FileType, int fCheck )
{
FILE * pFile;
Abc_Ntk_t * pNtk;
if ( FileType == IO_FILE_NONE || FileType == IO_FILE_UNKNOWN )
{
fprintf( stdout, "The generic file reader requires a known file extension.\n" );
return NULL;
}
// check if the file exists
pFile = fopen( pFileName, "r" );
if ( pFile == NULL )
{
fprintf( stdout, "Cannot open input file \"%s\". ", pFileName );
if ( pFileName = Extra_FileGetSimilarName( pFileName, ".blif", ".bench", ".pla", ".baf", ".aig" ) )
fprintf( stdout, "Did you mean \"%s\"?", pFileName );
fprintf( stdout, "\n" );
return NULL;
}
fclose( pFile );
// read the AIG
if ( FileType == IO_FILE_AIGER || FileType == IO_FILE_BAF )
{
if ( FileType == IO_FILE_AIGER )
pNtk = Io_ReadAiger( pFileName, fCheck );
else // if ( FileType == IO_FILE_BAF )
pNtk = Io_ReadBaf( pFileName, fCheck );
if ( pNtk == NULL )
{
fprintf( stdout, "Reading AIG from file has failed.\n" );
return NULL;
}
return pNtk;
}
// read the new netlist
if ( FileType == IO_FILE_BLIF )
pNtk = Io_ReadBlif( pFileName, fCheck );
else if ( FileType == IO_FILE_BENCH )
pNtk = Io_ReadBench( pFileName, fCheck );
else if ( FileType == IO_FILE_EDIF )
pNtk = Io_ReadEdif( pFileName, fCheck );
else if ( FileType == IO_FILE_EQN )
pNtk = Io_ReadEqn( pFileName, fCheck );
else if ( FileType == IO_FILE_PLA )
pNtk = Io_ReadPla( pFileName, fCheck );
else
{
fprintf( stderr, "Unknown file format.\n" );
return NULL;
}
if ( pNtk == NULL )
{
fprintf( stdout, "Reading network from file has failed.\n" );
return NULL;
}
return pNtk;
}
/**Function*************************************************************
Synopsis [Read the network from a file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Io_Read( char * pFileName, Io_FileType_t FileType, int fCheck )
{
Abc_Ntk_t * pNtk, * pTemp;
// get the netlist
pNtk = Io_ReadNetlist( pFileName, FileType, fCheck );
if ( pNtk == NULL )
return NULL;
if ( !Abc_NtkIsNetlist(pNtk) )
return pNtk;
// convert the netlist into the logic network
pNtk = Abc_NtkNetlistToLogic( pTemp = pNtk );
Abc_NtkDelete( pTemp );
if ( pNtk == NULL )
{
fprintf( stdout, "Converting netlist to logic network after reading has failed.\n" );
return NULL;
}
return pNtk;
}
/**Function*************************************************************
Synopsis [Write the network into file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType )
{
Abc_Ntk_t * pNtkTemp, * pNtkCopy;
// check if the current network is available
if ( pNtk == NULL )
{
fprintf( stdout, "Empty network.\n" );
return;
}
// check if the file extension if given
if ( FileType == IO_FILE_NONE || FileType == IO_FILE_UNKNOWN )
{
fprintf( stdout, "The generic file writer requires a known file extension.\n" );
return;
}
// write the AIG formats
if ( FileType == IO_FILE_AIGER || FileType == IO_FILE_BAF )
{
if ( !Abc_NtkIsStrash(pNtk) )
{
fprintf( stdout, "Writing this format is only possible for structurally hashed AIGs.\n" );
return;
}
if ( FileType == IO_FILE_AIGER )
Io_WriteAiger( pNtk, pFileName );
else // if ( FileType == IO_FILE_BAF )
Io_WriteBaf( pNtk, pFileName );
return;
}
// write non-netlist types
if ( FileType == IO_FILE_CNF )
{
Io_WriteCnf( pNtk, pFileName );
return;
}
if ( FileType == IO_FILE_DOT )
{
Io_WriteDot( pNtk, pFileName );
return;
}
if ( FileType == IO_FILE_GML )
{
Io_WriteGml( pNtk, pFileName );
return;
}
// convert logic network into netlist
if ( FileType == IO_FILE_PLA )
{
if ( Abc_NtkLevel(pNtk) > 1 )
{
fprintf( stdout, "PLA writing is available for collapsed networks.\n" );
return;
}
if ( Abc_NtkIsComb(pNtk) )
pNtkTemp = Abc_NtkLogicToNetlist( pNtk, 1 );
else
{
fprintf( stdout, "Latches are writen into the PLA file at PI/PO pairs.\n" );
pNtkCopy = Abc_NtkDup( pNtk );
Abc_NtkMakeComb( pNtkCopy );
pNtkTemp = Abc_NtkLogicToNetlist( pNtk, 1 );
Abc_NtkDelete( pNtkCopy );
}
}
else if ( FileType == IO_FILE_BENCH )
{
if ( !Abc_NtkIsStrash(pNtk) )
{
fprintf( stdout, "Writing BENCH is available for AIGs.\n" );
return;
}
pNtkTemp = Abc_NtkLogicToNetlistBench( pNtk );
}
else
pNtkTemp = Abc_NtkLogicToNetlist( pNtk, 0 );
if ( pNtkTemp == NULL )
{
fprintf( stdout, "Converting to netlist has failed.\n" );
return;
}
if ( FileType == IO_FILE_BLIF )
Io_WriteBlifNetlist( pNtkTemp, pFileName, 1 );
else if ( FileType == IO_FILE_BENCH )
Io_WriteBench( pNtkTemp, pFileName );
else if ( FileType == IO_FILE_PLA )
Io_WritePla( pNtkTemp, pFileName );
else if ( FileType == IO_FILE_EQN )
{
if ( Abc_NtkIsSopNetlist(pNtkTemp) )
Abc_NtkSopToAig( pNtkTemp );
Io_WriteEqn( pNtkTemp, pFileName );
}
else if ( FileType == IO_FILE_VERILOG )
{
if ( Abc_NtkIsSopNetlist(pNtkTemp) )
Abc_NtkSopToAig( pNtkTemp );
Io_WriteVerilog( pNtkTemp, pFileName, 1 );
}
else
fprintf( stderr, "Unknown file format.\n" );
Abc_NtkDelete( pNtkTemp );
}
/**Function*************************************************************
Synopsis [Creates PI terminal and net.]
@ -136,6 +399,73 @@ Abc_Obj_t * Io_ReadCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO )
return pLatch;
}
/**Function*************************************************************
Synopsis [Create the reset latch with data=1 and init=0.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Io_ReadCreateResetLatch( Abc_Ntk_t * pNtk, int fBlifMv )
{
Abc_Obj_t * pLatch, * pNode;
// create latch with 0 init value
pLatch = Io_ReadCreateLatch( pNtk, "_resetLI_", "_resetLO_" );
Abc_LatchSetInit0( pLatch );
// feed the latch with constant1- node
pNode = Abc_NtkCreateNode( pNtk );
pNode->pData = Abc_SopRegister( pNtk->pManFunc, "2\n1\n" );
Abc_ObjAddFanin( Abc_ObjFanin0(Abc_ObjFanin0(pLatch)), pNode );
return pLatch;
}
/**Function*************************************************************
Synopsis [Create a latch with the given input/output.]
Description [By default, the latch value is unknown (ABC_INIT_NONE).]
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Io_ReadCreateResetMux( Abc_Ntk_t * pNtk, char * pResetLO, char * pDataLI, int fBlifMv )
{
char Buffer[50];
Abc_Obj_t * pNode, * pData0Net, * pData1Net, * pResetLONet, * pLINet;
// get the reset output net
pResetLONet = Abc_NtkFindNet( pNtk, pResetLO );
assert( pResetLONet );
// get the latch input net
pData1Net = Abc_NtkFindOrCreateNet( pNtk, pDataLI );
// create Data0 net (coming from reset node)
pData0Net = Abc_NtkFindOrCreateNet( pNtk, Abc_ObjNameSuffix(pData1Net, "_reset") );
// create the node
pNode = Abc_NtkCreateNode( pNtk );
if ( fBlifMv )
{
// Vec_Att_t * p = Abc_NtkMvVar( pNtk );
int nValues = Abc_ObjMvVarNum(pData1Net);
sprintf( Buffer, "2 %d %d %d\n1 - - =1\n0 - - =2\n", nValues, nValues, nValues );
pNode->pData = Abc_SopRegister( pNtk->pManFunc, Buffer );
}
else
pNode->pData = Abc_SopCreateMux( pNtk->pManFunc );
// add nets
Abc_ObjAddFanin( pNode, pResetLONet );
Abc_ObjAddFanin( pNode, pData1Net );
Abc_ObjAddFanin( pNode, pData0Net );
// create the output net
pLINet = Abc_NtkFindOrCreateNet( pNtk, Abc_ObjNameSuffix(pData1Net, "_mux") );
Abc_ObjAddFanin( pLINet, pNode );
return pNode;
}
/**Function*************************************************************
Synopsis [Create node and the net driven by it.]

515
src/base/io/ioWriteBlifMv.c Normal file
View File

@ -0,0 +1,515 @@
/**CFile****************************************************************
FileName [ioWriteBlifMv.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Command processing package.]
Synopsis [Procedures to write BLIF-MV files.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: ioWriteBlifMv.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "io.h"
#include "main.h"
#include "mio.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
static void Io_NtkWriteBlifMv( FILE * pFile, Abc_Ntk_t * pNtk );
static void Io_NtkWriteBlifMvOne( FILE * pFile, Abc_Ntk_t * pNtk );
static void Io_NtkWriteBlifMvPis( FILE * pFile, Abc_Ntk_t * pNtk );
static void Io_NtkWriteBlifMvPos( FILE * pFile, Abc_Ntk_t * pNtk );
static void Io_NtkWriteBlifMvAsserts( FILE * pFile, Abc_Ntk_t * pNtk );
static void Io_NtkWriteBlifMvNodeFanins( FILE * pFile, Abc_Obj_t * pNode );
static void Io_NtkWriteBlifMvNode( FILE * pFile, Abc_Obj_t * pNode );
static void Io_NtkWriteBlifMvLatch( FILE * pFile, Abc_Obj_t * pLatch );
static void Io_NtkWriteBlifMvSubckt( FILE * pFile, Abc_Obj_t * pNode );
static void Io_NtkWriteBlifMvValues( FILE * pFile, Abc_Obj_t * pNode );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Write the network into a BLIF file with the given name.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteBlifMvDesign( Abc_Lib_t * pLib, char * FileName )
{
FILE * pFile;
Abc_Ntk_t * pNtk;
int i;
// start writing the file
pFile = fopen( FileName, "w" );
if ( pFile == NULL )
{
fprintf( stdout, "Io_WriteBlifMvDesign(): Cannot open the output file.\n" );
return;
}
fprintf( pFile, "# Benchmark \"%s\" written by ABC on %s\n", pLib->pName, Extra_TimeStamp() );
// write the master network
Vec_PtrForEachEntry( pLib->vModules, pNtk, i )
Io_NtkWriteBlifMv( pFile, pNtk );
fclose( pFile );
}
/**Function*************************************************************
Synopsis [Write the network into a BLIF file with the given name.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteBlifMvNetlist( Abc_Ntk_t * pNtk, char * FileName )
{
FILE * pFile;
// start writing the file
pFile = fopen( FileName, "w" );
if ( pFile == NULL )
{
fprintf( stdout, "Io_WriteMvNetlist(): Cannot open the output file.\n" );
return;
}
fprintf( pFile, "# Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
// write the master network
Io_NtkWriteBlifMv( pFile, pNtk );
fclose( pFile );
}
/**Function*************************************************************
Synopsis [Write the network into a BLIF file with the given name.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_NtkWriteBlifMv( FILE * pFile, Abc_Ntk_t * pNtk )
{
assert( Abc_NtkIsNetlist(pNtk) );
// write the model name
fprintf( pFile, ".model %s\n", Abc_NtkName(pNtk) );
// write the network
Io_NtkWriteBlifMvOne( pFile, pNtk );
// write EXDC network if it exists
if ( Abc_NtkExdc(pNtk) )
printf( "Io_NtkWriteBlifMv(): EXDC is not written.\n" );
// finalize the file
fprintf( pFile, ".end\n\n\n" );
}
/**Function*************************************************************
Synopsis [Write one network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_NtkWriteBlifMvOne( FILE * pFile, Abc_Ntk_t * pNtk )
{
ProgressBar * pProgress;
Abc_Obj_t * pNode, * pTerm, * pLatch;
int i;
// write the PIs
fprintf( pFile, ".inputs" );
Io_NtkWriteBlifMvPis( pFile, pNtk );
fprintf( pFile, "\n" );
// write the POs
fprintf( pFile, ".outputs" );
Io_NtkWriteBlifMvPos( pFile, pNtk );
fprintf( pFile, "\n" );
// write the assertions
if ( Abc_NtkAssertNum(pNtk) )
{
fprintf( pFile, ".asserts" );
Io_NtkWriteBlifMvAsserts( pFile, pNtk );
fprintf( pFile, "\n" );
}
// write the MV directives
fprintf( pFile, "\n" );
Abc_NtkForEachCi( pNtk, pTerm, i )
if ( Abc_ObjMvVarNum(Abc_ObjFanout0(pTerm)) > 2 )
fprintf( pFile, ".mv %s %d\n", Abc_ObjName(Abc_ObjFanout0(pTerm)), Abc_ObjMvVarNum(Abc_ObjFanout0(pTerm)) );
Abc_NtkForEachCo( pNtk, pTerm, i )
if ( Abc_ObjMvVarNum(Abc_ObjFanin0(pTerm)) > 2 )
fprintf( pFile, ".mv %s %d\n", Abc_ObjName(Abc_ObjFanin0(pTerm)), Abc_ObjMvVarNum(Abc_ObjFanin0(pTerm)) );
// write the blackbox
if ( Abc_NtkHasBlackbox( pNtk ) )
{
fprintf( pFile, ".blackbox\n" );
return;
}
// write the timing info
// Io_WriteTimingInfo( pFile, pNtk );
// write the latches
if ( !Abc_NtkIsComb(pNtk) )
{
fprintf( pFile, "\n" );
Abc_NtkForEachLatch( pNtk, pLatch, i )
Io_NtkWriteBlifMvLatch( pFile, pLatch );
fprintf( pFile, "\n" );
}
// write the subcircuits
if ( !Abc_NtkBlackboxNum(pNtk) )
{
fprintf( pFile, "\n" );
Abc_NtkForEachBlackbox( pNtk, pNode, i )
Io_NtkWriteBlifMvSubckt( pFile, pNode );
fprintf( pFile, "\n" );
}
// write each internal node
pProgress = Extra_ProgressBarStart( stdout, Abc_NtkObjNumMax(pNtk) );
Abc_NtkForEachNode( pNtk, pNode, i )
{
Extra_ProgressBarUpdate( pProgress, i, NULL );
Io_NtkWriteBlifMvNode( pFile, pNode );
}
Extra_ProgressBarStop( pProgress );
}
/**Function*************************************************************
Synopsis [Writes the primary input list.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_NtkWriteBlifMvPis( FILE * pFile, Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pTerm, * pNet;
int LineLength;
int AddedLength;
int NameCounter;
int i;
LineLength = 7;
NameCounter = 0;
Abc_NtkForEachPi( pNtk, pTerm, i )
{
pNet = Abc_ObjFanout0(pTerm);
// get the line length after this name is written
AddedLength = strlen(Abc_ObjName(pNet)) + 1;
if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
{ // write the line extender
fprintf( pFile, " \\\n" );
// reset the line length
LineLength = 0;
NameCounter = 0;
}
fprintf( pFile, " %s", Abc_ObjName(pNet) );
LineLength += AddedLength;
NameCounter++;
}
}
/**Function*************************************************************
Synopsis [Writes the primary input list.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_NtkWriteBlifMvPos( FILE * pFile, Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pTerm, * pNet;
int LineLength;
int AddedLength;
int NameCounter;
int i;
LineLength = 8;
NameCounter = 0;
Abc_NtkForEachPo( pNtk, pTerm, i )
{
pNet = Abc_ObjFanin0(pTerm);
// get the line length after this name is written
AddedLength = strlen(Abc_ObjName(pNet)) + 1;
if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
{ // write the line extender
fprintf( pFile, " \\\n" );
// reset the line length
LineLength = 0;
NameCounter = 0;
}
fprintf( pFile, " %s", Abc_ObjName(pNet) );
LineLength += AddedLength;
NameCounter++;
}
}
/**Function*************************************************************
Synopsis [Writes the assertion list.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_NtkWriteBlifMvAsserts( FILE * pFile, Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pTerm, * pNet;
int LineLength;
int AddedLength;
int NameCounter;
int i;
LineLength = 8;
NameCounter = 0;
Abc_NtkForEachAssert( pNtk, pTerm, i )
{
pNet = Abc_ObjFanin0(pTerm);
// get the line length after this name is written
AddedLength = strlen(Abc_ObjName(pNet)) + 1;
if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
{ // write the line extender
fprintf( pFile, " \\\n" );
// reset the line length
LineLength = 0;
NameCounter = 0;
}
fprintf( pFile, " %s", Abc_ObjName(pNet) );
LineLength += AddedLength;
NameCounter++;
}
}
/**Function*************************************************************
Synopsis [Write the latch into a file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_NtkWriteBlifMvLatch( FILE * pFile, Abc_Obj_t * pLatch )
{
Abc_Obj_t * pNetLi, * pNetLo;
int Reset;
pNetLi = Abc_ObjFanin0( Abc_ObjFanin0(pLatch) );
pNetLo = Abc_ObjFanout0( Abc_ObjFanout0(pLatch) );
Reset = (int)Abc_ObjData( pLatch );
// write the latch line
fprintf( pFile, ".latch" );
fprintf( pFile, " %10s", Abc_ObjName(pNetLi) );
fprintf( pFile, " %10s", Abc_ObjName(pNetLo) );
fprintf( pFile, "\n" );
// write the reset node
fprintf( pFile, ".reset %s\n", Abc_ObjName(pNetLo) );
fprintf( pFile, "%d\n", Reset-1 );
}
/**Function*************************************************************
Synopsis [Write the latch into a file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_NtkWriteBlifMvSubckt( FILE * pFile, Abc_Obj_t * pNode )
{
Abc_Ntk_t * pModel = pNode->pData;
Abc_Obj_t * pTerm;
int i;
// write the MV directives
fprintf( pFile, "\n" );
Abc_ObjForEachFanin( pNode, pTerm, i )
if ( Abc_ObjMvVarNum(pTerm) > 2 )
fprintf( pFile, ".mv %s %d\n", Abc_ObjName(pTerm), Abc_ObjMvVarNum(pTerm) );
Abc_ObjForEachFanout( pNode, pTerm, i )
if ( Abc_ObjMvVarNum(pTerm) > 2 )
fprintf( pFile, ".mv %s %d\n", Abc_ObjName(pTerm), Abc_ObjMvVarNum(pTerm) );
// write the subcircuit
fprintf( pFile, ".subckt %s %s", Abc_NtkName(pModel), Abc_ObjName(pNode) );
// write pairs of the formal=actual names
Abc_NtkForEachPi( pModel, pTerm, i )
{
fprintf( pFile, " %s", Abc_ObjName(Abc_ObjFanout0(pTerm)) );
pTerm = Abc_ObjFanin( pNode, i );
fprintf( pFile, "=%s", Abc_ObjName(Abc_ObjFanin0(pTerm)) );
}
Abc_NtkForEachPo( pModel, pTerm, i )
{
fprintf( pFile, " %s", Abc_ObjName(Abc_ObjFanin0(pTerm)) );
pTerm = Abc_ObjFanout( pNode, i );
fprintf( pFile, "=%s", Abc_ObjName(Abc_ObjFanout0(pTerm)) );
}
fprintf( pFile, "\n" );
}
/**Function*************************************************************
Synopsis [Write the node into a file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_NtkWriteBlifMvNode( FILE * pFile, Abc_Obj_t * pNode )
{
Abc_Obj_t * pFanin;
char * pCur;
int nValues, iFanin, i;
fprintf( pFile, "\n" );
// write .mv directives for the fanins
pCur = Abc_ObjData(pNode);
Abc_ObjForEachFanin( pNode, pFanin, i )
{
nValues = atoi(pCur);
if ( nValues > 2 )
fprintf( pFile, ".mv %s %d\n", Abc_ObjName(pFanin), nValues );
while ( *pCur++ != ' ' );
}
// write .mv directives for the node
nValues = atoi(pCur);
if ( nValues > 2 )
fprintf( pFile, ".mv %s %d\n", Abc_ObjName(Abc_ObjFanout0(pNode)), nValues );
while ( *pCur++ != '\n' );
// write the .names line
fprintf( pFile, ".table" );
Io_NtkWriteBlifMvNodeFanins( pFile, pNode );
fprintf( pFile, "\n" );
// write the cubes
if ( *pCur == 'd' )
{
fprintf( pFile, ".default " );
pCur++;
}
// write the literals
for ( ; *pCur; pCur++ )
{
fprintf( pFile, "%c", *pCur );
if ( *pCur != '=' )
continue;
// get the number
iFanin = atoi( pCur+1 );
fprintf( pFile, "%s", Abc_ObjName(Abc_ObjFanin(pNode,iFanin)) );
// scroll on to the next symbol
while ( *pCur != ' ' && *pCur != '\n' )
pCur++;
pCur--;
}
}
/**Function*************************************************************
Synopsis [Writes the primary input list.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_NtkWriteBlifMvNodeFanins( FILE * pFile, Abc_Obj_t * pNode )
{
Abc_Obj_t * pNet;
int LineLength;
int AddedLength;
int NameCounter;
char * pName;
int i;
LineLength = 6;
NameCounter = 0;
Abc_ObjForEachFanin( pNode, pNet, i )
{
// get the fanin name
pName = Abc_ObjName(pNet);
// get the line length after the fanin name is written
AddedLength = strlen(pName) + 1;
if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
{ // write the line extender
fprintf( pFile, " \\\n" );
// reset the line length
LineLength = 0;
NameCounter = 0;
}
fprintf( pFile, " %s", pName );
LineLength += AddedLength;
NameCounter++;
}
// get the output name
pName = Abc_ObjName(Abc_ObjFanout0(pNode));
// get the line length after the output name is written
AddedLength = strlen(pName) + 1;
if ( NameCounter && LineLength + AddedLength > 75 )
{ // write the line extender
fprintf( pFile, " \\\n" );
// reset the line length
LineLength = 0;
NameCounter = 0;
}
fprintf( pFile, " %s", pName );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

20
src/base/io/ioWriteDot.c
View File

@ -33,6 +33,26 @@ static int Abc_NtkCountLogicNodes( Vec_Ptr_t * vNodes );
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Writes the graph structure of network for DOT.]
Description [Useful for graph visualization using tools such as GraphViz:
http://www.graphviz.org/]
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteDot( Abc_Ntk_t * pNtk, char * FileName )
{
Vec_Ptr_t * vNodes;
vNodes = Abc_NtkCollectObjects( pNtk );
Io_WriteDotNtk( pNtk, vNodes, NULL, FileName, 0, 0 );
Vec_PtrFree( vNodes );
}
/**Function*************************************************************
Synopsis [Writes the graph structure of network for DOT.]

115
src/base/io/ioWriteEqn.c
View File

@ -25,9 +25,9 @@
////////////////////////////////////////////////////////////////////////
static void Io_NtkWriteEqnOne( FILE * pFile, Abc_Ntk_t * pNtk );
static void Io_NtkWriteEqnPis( FILE * pFile, Abc_Ntk_t * pNtk );
static void Io_NtkWriteEqnPos( FILE * pFile, Abc_Ntk_t * pNtk );
static void Io_NtkWriteEqnNode( FILE * pFile, Abc_Obj_t * pNode );
static void Io_NtkWriteEqnCis( FILE * pFile, Abc_Ntk_t * pNtk );
static void Io_NtkWriteEqnCos( FILE * pFile, Abc_Ntk_t * pNtk );
static int Io_NtkWriteEqnCheck( Abc_Ntk_t * pNtk );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
@ -48,10 +48,14 @@ void Io_WriteEqn( Abc_Ntk_t * pNtk, char * pFileName )
{
FILE * pFile;
assert( Abc_NtkIsSopNetlist(pNtk) );
assert( Abc_NtkIsAigNetlist(pNtk) );
if ( Abc_NtkLatchNum(pNtk) > 0 )
printf( "Warning: only combinational portion is being written.\n" );
// check that the names are fine for the EQN format
if ( !Io_NtkWriteEqnCheck(pNtk) )
return;
// start the output stream
pFile = fopen( pFileName, "w" );
if ( pFile == NULL )
@ -80,28 +84,37 @@ void Io_WriteEqn( Abc_Ntk_t * pNtk, char * pFileName )
***********************************************************************/
void Io_NtkWriteEqnOne( FILE * pFile, Abc_Ntk_t * pNtk )
{
Vec_Vec_t * vLevels;
ProgressBar * pProgress;
Abc_Obj_t * pNode;
int i;
Abc_Obj_t * pNode, * pFanin;
int i, k;
// write the PIs
fprintf( pFile, "INORDER =" );
Io_NtkWriteEqnPis( pFile, pNtk );
Io_NtkWriteEqnCis( pFile, pNtk );
fprintf( pFile, ";\n" );
// write the POs
fprintf( pFile, "OUTORDER =" );
Io_NtkWriteEqnPos( pFile, pNtk );
Io_NtkWriteEqnCos( pFile, pNtk );
fprintf( pFile, ";\n" );
// write each internal node
vLevels = Vec_VecAlloc( 10 );
pProgress = Extra_ProgressBarStart( stdout, Abc_NtkObjNumMax(pNtk) );
Abc_NtkForEachNode( pNtk, pNode, i )
{
Extra_ProgressBarUpdate( pProgress, i, NULL );
Io_NtkWriteEqnNode( pFile, pNode );
fprintf( pFile, "%s = ", Abc_ObjName(Abc_ObjFanout0(pNode)) );
// set the input names
Abc_ObjForEachFanin( pNode, pFanin, k )
Hop_IthVar(pNtk->pManFunc, k)->pData = Abc_ObjName(pFanin);
// write the formula
Hop_ObjPrintEqn( pFile, pNode->pData, vLevels, 0 );
fprintf( pFile, ";\n" );
}
Extra_ProgressBarStop( pProgress );
Vec_VecFree( vLevels );
}
@ -116,7 +129,7 @@ void Io_NtkWriteEqnOne( FILE * pFile, Abc_Ntk_t * pNtk )
SeeAlso []
***********************************************************************/
void Io_NtkWriteEqnPis( FILE * pFile, Abc_Ntk_t * pNtk )
void Io_NtkWriteEqnCis( FILE * pFile, Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pTerm, * pNet;
int LineLength;
@ -156,7 +169,7 @@ void Io_NtkWriteEqnPis( FILE * pFile, Abc_Ntk_t * pNtk )
SeeAlso []
***********************************************************************/
void Io_NtkWriteEqnPos( FILE * pFile, Abc_Ntk_t * pNtk )
void Io_NtkWriteEqnCos( FILE * pFile, Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pTerm, * pNet;
int LineLength;
@ -187,73 +200,51 @@ void Io_NtkWriteEqnPos( FILE * pFile, Abc_Ntk_t * pNtk )
/**Function*************************************************************
Synopsis [Write the node into a file.]
Synopsis [Make sure the network does not have offending names.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_NtkWriteEqnNode( FILE * pFile, Abc_Obj_t * pNode )
int Io_NtkWriteEqnCheck( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNet;
int LineLength;
int AddedLength;
int NameCounter;
char * pCube;
int Value, fFirstLit, i;
Abc_Obj_t * pObj;
char * pName;
int i, k, Length;
int RetValue = 1;
fprintf( pFile, "%s = ", Abc_ObjName(pNode) );
if ( Abc_SopIsConst0(pNode->pData) )
// make sure the network does not have proper names, such as "0" or "1" or containing parantheses
Abc_NtkForEachObj( pNtk, pObj, i )
{
fprintf( pFile, "0;\n" );
return;
}
if ( Abc_SopIsConst1(pNode->pData) )
{
fprintf( pFile, "1;\n" );
return;
}
NameCounter = 0;
LineLength = strlen(Abc_ObjName(pNode)) + 3;
Abc_SopForEachCube( pNode->pData, Abc_ObjFaninNum(pNode), pCube )
{
if ( pCube != pNode->pData )
pName = Nm_ManFindNameById(pNtk->pManName, i);
if ( pName == NULL )
continue;
Length = strlen(pName);
if ( pName[0] == '0' || pName[0] == '1' )
{
fprintf( pFile, " + " );
LineLength += 3;
RetValue = 0;
break;
}
// add the cube
fFirstLit = 1;
Abc_CubeForEachVar( pCube, Value, i )
{
if ( Value == '-' )
continue;
pNet = Abc_ObjFanin( pNode, i );
// get the line length after this name is written
AddedLength = !fFirstLit + (Value == '0') + strlen(Abc_ObjName(pNet));
if ( NameCounter && LineLength + AddedLength + 6 > IO_WRITE_LINE_LENGTH )
{ // write the line extender
fprintf( pFile, " \n " );
// reset the line length
LineLength = 0;
NameCounter = 0;
for ( k = 0; k < Length; k++ )
if ( pName[k] == '(' || pName[k] == ')' || pName[k] == '!' || pName[k] == '*' || pName[k] == '+' )
{
RetValue = 0;
break;
}
fprintf( pFile, "%s%s%s", (fFirstLit? "": "*"), ((Value == '0')? "!":""), Abc_ObjName(pNet) );
LineLength += AddedLength;
NameCounter++;
fFirstLit = 0;
}
if ( k < Length )
break;
}
fprintf( pFile, ";\n" );
if ( RetValue == 0 )
{
printf( "The network cannot be written in the EQN format because object %d has name \"%s\".\n", i, pName );
printf( "Consider renaming the objects using command \"short_names\" and trying again.\n" );
}
return RetValue;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

3
src/base/io/ioWriteList.c
View File

@ -19,7 +19,6 @@
***********************************************************************/
#include "io.h"
//#include "seqInt.h"
/*
-------- Original Message --------
@ -103,7 +102,7 @@ void Io_WriteList( Abc_Ntk_t * pNtk, char * pFileName, int fUseHost )
Abc_Obj_t * pObj;
int i;
assert( Abc_NtkIsSeq(pNtk) );
// assert( Abc_NtkIsSeq(pNtk) );
// start the output stream
pFile = fopen( pFileName, "w" );

6
src/base/io/ioWriteVer.c
View File

@ -62,6 +62,12 @@ void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName, int fVerLibStyle )
printf( "Io_WriteVerilog(): Can produce Verilog for AIG netlists only.\n" );
return;
}
if ( Abc_NtkLatchNum(pNtk) > 0 )
{
printf( "Io_WriteVerilog(): Currently cannot write verilog for sequential networks.\n" );
return;
}
/*
if ( !(Abc_NtkIsNetlist(pNtk) && (Abc_NtkHasMapping(pNtk) || Io_WriteVerilogCheckNtk(pNtk))) )
{

36
src/base/io/io_.c Normal file
View File

@ -0,0 +1,36 @@
/**CFile****************************************************************
FileName [io_.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Command processing package.]
Synopsis [Procedure to read network from file.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: io_.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "io.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

5
src/base/io/module.make
View File

@ -1,18 +1,19 @@
SRC += src/base/io/io.c \
src/base/io/ioRead.c \
src/base/io/ioReadAiger.c \
src/base/io/ioReadBaf.c \
src/base/io/ioReadBench.c \
src/base/io/ioReadBlif.c \
src/base/io/ioReadBlifAig.c \
src/base/io/ioReadBlifMv.c \
src/base/io/ioReadEdif.c \
src/base/io/ioReadEqn.c \
src/base/io/ioReadPla.c \
src/base/io/ioReadVerilog.c \
src/base/io/ioUtil.c \
src/base/io/ioWriteAiger.c \
src/base/io/ioWriteBaf.c \
src/base/io/ioWriteBench.c \
src/base/io/ioWriteBlif.c \
src/base/io/ioWriteBlifMv.c \
src/base/io/ioWriteCnf.c \
src/base/io/ioWriteDot.c \
src/base/io/ioWriteEqn.c \

13
src/base/main/mainUtils.c
View File

@ -20,6 +20,10 @@
#include "mainInt.h"
#ifndef _WIN32
#include "readline/readline.h"
#endif
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
@ -62,9 +66,18 @@ char * Abc_UtilsGetUsersInput( Abc_Frame_t * pAbc )
{
static char Buffer[1000], Prompt[1000];
sprintf( Prompt, "abc %02d> ", pAbc->nSteps );
#ifdef _WIN32
fprintf( pAbc->Out, "%s", Prompt );
fgets( Buffer, 999, stdin );
return Buffer;
#else
static char* line = NULL;
if (line != NULL) free(line);
line = readline(Prompt);
if (line == NULL){ printf("***EOF***\n"); exit(0); }
add_history(line);
return line;
#endif
}
/**Function*************************************************************

2
src/base/seq/seqMan.c
View File

@ -122,7 +122,7 @@ void Seq_Delete( Abc_Seq_t * p )
if ( p->vUses ) Vec_StrFree( p->vUses ); // the uses of phases
if ( p->vInits ) Vec_PtrFree( p->vInits ); // the initial values of the latches
if ( p->vNums ) Vec_IntFree( p->vNums ); // the numbers of latches
Extra_MmFixedStop( p->pMmInits, 0 );
Extra_MmFixedStop( p->pMmInits );
free( p );
}

1
src/bdd/parse/module.make
View File

@ -1,2 +1,3 @@
SRC += src/bdd/parse/parseCore.c \
src/bdd/parse/parseEqn.c \
src/bdd/parse/parseStack.c

349
src/bdd/parse/parseEqn.c Normal file
View File

@ -0,0 +1,349 @@
/**CFile****************************************************************
FileNameIn [parseEqn.c]
PackageName [ABC: Logic synthesis and verification system.]
Synopsis [Boolean formula parser.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - December 18, 2006.]
Revision [$Id: parseEqn.c,v 1.0 2006/12/18 00:00:00 alanmi Exp $]
***********************************************************************/
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
#include "parseInt.h"
#include "vec.h"
#include "hop.h"
// the list of operation symbols to be used in expressions
#define PARSE_EQN_SYM_OPEN '(' // opening paranthesis
#define PARSE_EQN_SYM_CLOSE ')' // closing paranthesis
#define PARSE_EQN_SYM_CONST0 '0' // constant 0
#define PARSE_EQN_SYM_CONST1 '1' // constant 1
#define PARSE_EQN_SYM_NEG '!' // negation before the variable
#define PARSE_EQN_SYM_AND '*' // logic AND
#define PARSE_EQN_SYM_OR '+' // logic OR
// the list of opcodes (also specifying operation precedence)
#define PARSE_EQN_OPER_NEG 10 // negation
#define PARSE_EQN_OPER_AND 9 // logic AND
#define PARSE_EQN_OPER_OR 7 // logic OR
#define PARSE_EQN_OPER_MARK 1 // OpStack token standing for an opening paranthesis
// these are values of the internal Flag
#define PARSE_EQN_FLAG_START 1 // after the opening parenthesis
#define PARSE_EQN_FLAG_VAR 2 // after operation is received
#define PARSE_EQN_FLAG_OPER 3 // after operation symbol is received
#define PARSE_EQN_FLAG_ERROR 4 // when error is detected
#define PARSE_EQN_STACKSIZE 1000
static Hop_Obj_t * Parse_ParserPerformTopOp( Hop_Man_t * pMan, Parse_StackFn_t * pStackFn, int Oper );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Derives the AIG corresponding to the equation.]
Description [Takes the stream to output messages, the formula, the vector
of variable names and the AIG manager.]
SideEffects []
SeeAlso []
***********************************************************************/
Hop_Obj_t * Parse_FormulaParserEqn( FILE * pOutput, char * pFormInit, Vec_Ptr_t * vVarNames, Hop_Man_t * pMan )
{
char * pFormula;
Parse_StackFn_t * pStackFn;
Parse_StackOp_t * pStackOp;
Hop_Obj_t * gFunc;
char * pTemp, * pName;
int nParans, fFound, Flag;
int Oper, Oper1, Oper2;
int i, v;
// make sure that the number of opening and closing parantheses is the same
nParans = 0;
for ( pTemp = pFormInit; *pTemp; pTemp++ )
if ( *pTemp == '(' )
nParans++;
else if ( *pTemp == ')' )
nParans--;
if ( nParans != 0 )
{
fprintf( pOutput, "Parse_FormulaParserEqn(): Different number of opening and closing parantheses ().\n" );
return NULL;
}
// copy the formula
pFormula = ALLOC( char, strlen(pFormInit) + 3 );
sprintf( pFormula, "(%s)", pFormInit );
// start the stacks
pStackFn = Parse_StackFnStart( PARSE_EQN_STACKSIZE );
pStackOp = Parse_StackOpStart( PARSE_EQN_STACKSIZE );
Flag = PARSE_EQN_FLAG_START;
for ( pTemp = pFormula; *pTemp; pTemp++ )
{
switch ( *pTemp )
{
// skip all spaces, tabs, and end-of-lines
case ' ':
case '\t':
case '\r':
case '\n':
continue;
case PARSE_EQN_SYM_CONST0:
Parse_StackFnPush( pStackFn, Hop_ManConst0(pMan) ); // Cudd_Ref( b0 );
if ( Flag == PARSE_EQN_FLAG_VAR )
{
fprintf( pOutput, "Parse_FormulaParserEqn(): No operation symbol before constant 0.\n" );
Flag = PARSE_EQN_FLAG_ERROR;
break;
}
Flag = PARSE_EQN_FLAG_VAR;
break;
case PARSE_EQN_SYM_CONST1:
Parse_StackFnPush( pStackFn, Hop_ManConst1(pMan) ); // Cudd_Ref( b1 );
if ( Flag == PARSE_EQN_FLAG_VAR )
{
fprintf( pOutput, "Parse_FormulaParserEqn(): No operation symbol before constant 1.\n" );
Flag = PARSE_EQN_FLAG_ERROR;
break;
}
Flag = PARSE_EQN_FLAG_VAR;
break;
case PARSE_EQN_SYM_NEG:
if ( Flag == PARSE_EQN_FLAG_VAR )
{// if NEGBEF follows a variable, AND is assumed
Parse_StackOpPush( pStackOp, PARSE_EQN_OPER_AND );
Flag = PARSE_EQN_FLAG_OPER;
}
Parse_StackOpPush( pStackOp, PARSE_EQN_OPER_NEG );
break;
case PARSE_EQN_SYM_AND:
case PARSE_EQN_SYM_OR:
if ( Flag != PARSE_EQN_FLAG_VAR )
{
fprintf( pOutput, "Parse_FormulaParserEqn(): There is no variable before AND, EXOR, or OR.\n" );
Flag = PARSE_EQN_FLAG_ERROR;
break;
}
if ( *pTemp == PARSE_EQN_SYM_AND )
Parse_StackOpPush( pStackOp, PARSE_EQN_OPER_AND );
else //if ( *pTemp == PARSE_EQN_SYM_OR )
Parse_StackOpPush( pStackOp, PARSE_EQN_OPER_OR );
Flag = PARSE_EQN_FLAG_OPER;
break;
case PARSE_EQN_SYM_OPEN:
if ( Flag == PARSE_EQN_FLAG_VAR )
{
// Parse_StackOpPush( pStackOp, PARSE_EQN_OPER_AND );
fprintf( pOutput, "Parse_FormulaParserEqn(): An opening paranthesis follows a var without operation sign.\n" );
Flag = PARSE_EQN_FLAG_ERROR;
break;
}
Parse_StackOpPush( pStackOp, PARSE_EQN_OPER_MARK );
// after an opening bracket, it feels like starting over again
Flag = PARSE_EQN_FLAG_START;
break;
case PARSE_EQN_SYM_CLOSE:
if ( !Parse_StackOpIsEmpty( pStackOp ) )
{
while ( 1 )
{
if ( Parse_StackOpIsEmpty( pStackOp ) )
{
fprintf( pOutput, "Parse_FormulaParserEqn(): There is no opening paranthesis\n" );
Flag = PARSE_EQN_FLAG_ERROR;
break;
}
Oper = Parse_StackOpPop( pStackOp );
if ( Oper == PARSE_EQN_OPER_MARK )
break;
// perform the given operation
if ( Parse_ParserPerformTopOp( pMan, pStackFn, Oper ) == NULL )
{
fprintf( pOutput, "Parse_FormulaParserEqn(): Unknown operation\n" );
free( pFormula );
return NULL;
}
}
}
else
{
fprintf( pOutput, "Parse_FormulaParserEqn(): There is no opening paranthesis\n" );
Flag = PARSE_EQN_FLAG_ERROR;
break;
}
if ( Flag != PARSE_EQN_FLAG_ERROR )
Flag = PARSE_EQN_FLAG_VAR;
break;
default:
// scan the next name
for ( i = 0; pTemp[i] &&
pTemp[i] != ' ' && pTemp[i] != '\t' && pTemp[i] != '\r' && pTemp[i] != '\n' &&
pTemp[i] != PARSE_EQN_SYM_AND && pTemp[i] != PARSE_EQN_SYM_OR && pTemp[i] != PARSE_EQN_SYM_CLOSE; i++ )
{
if ( pTemp[i] == PARSE_EQN_SYM_NEG || pTemp[i] == PARSE_EQN_SYM_OPEN )
{
fprintf( pOutput, "Parse_FormulaParserEqn(): The negation sign or an opening paranthesis inside the variable name.\n" );
Flag = PARSE_EQN_FLAG_ERROR;
break;
}
}
// variable name is found
fFound = 0;
Vec_PtrForEachEntry( vVarNames, pName, v )
if ( strncmp(pTemp, pName, i) == 0 && strlen(pName) == (unsigned)i )
{
pTemp += i-1;
fFound = 1;
break;
}
if ( !fFound )
{
fprintf( pOutput, "Parse_FormulaParserEqn(): The parser cannot find var \"%s\" in the input var list.\n", pTemp );
Flag = PARSE_EQN_FLAG_ERROR;
break;
}
if ( Flag == PARSE_EQN_FLAG_VAR )
{
fprintf( pOutput, "Parse_FormulaParserEqn(): The variable name \"%s\" follows another var without operation sign.\n", pTemp );
Flag = PARSE_EQN_FLAG_ERROR;
break;
}
Parse_StackFnPush( pStackFn, Hop_IthVar( pMan, v ) ); // Cudd_Ref( pbVars[v] );
Flag = PARSE_EQN_FLAG_VAR;
break;
}
if ( Flag == PARSE_EQN_FLAG_ERROR )
break; // error exit
else if ( Flag == PARSE_EQN_FLAG_START )
continue; // go on parsing
else if ( Flag == PARSE_EQN_FLAG_VAR )
while ( 1 )
{ // check if there are negations in the OpStack
if ( Parse_StackOpIsEmpty(pStackOp) )
break;
Oper = Parse_StackOpPop( pStackOp );
if ( Oper != PARSE_EQN_OPER_NEG )
{
Parse_StackOpPush( pStackOp, Oper );
break;
}
else
{
Parse_StackFnPush( pStackFn, Hop_Not(Parse_StackFnPop(pStackFn)) );
}
}
else // if ( Flag == PARSE_EQN_FLAG_OPER )
while ( 1 )
{ // execute all the operations in the OpStack
// with precedence higher or equal than the last one
Oper1 = Parse_StackOpPop( pStackOp ); // the last operation
if ( Parse_StackOpIsEmpty(pStackOp) )
{ // if it is the only operation, push it back
Parse_StackOpPush( pStackOp, Oper1 );
break;
}
Oper2 = Parse_StackOpPop( pStackOp ); // the operation before the last one
if ( Oper2 >= Oper1 )
{ // if Oper2 precedence is higher or equal, execute it
if ( Parse_ParserPerformTopOp( pMan, pStackFn, Oper2 ) == NULL )
{
fprintf( pOutput, "Parse_FormulaParserEqn(): Unknown operation\n" );
free( pFormula );
return NULL;
}
Parse_StackOpPush( pStackOp, Oper1 ); // push the last operation back
}
else
{ // if Oper2 precedence is lower, push them back and done
Parse_StackOpPush( pStackOp, Oper2 );
Parse_StackOpPush( pStackOp, Oper1 );
break;
}
}
}
if ( Flag != PARSE_EQN_FLAG_ERROR )
{
if ( !Parse_StackFnIsEmpty(pStackFn) )
{
gFunc = Parse_StackFnPop(pStackFn);
if ( Parse_StackFnIsEmpty(pStackFn) )
if ( Parse_StackOpIsEmpty(pStackOp) )
{
Parse_StackFnFree(pStackFn);
Parse_StackOpFree(pStackOp);
// Cudd_Deref( gFunc );
free( pFormula );
return gFunc;
}
else
fprintf( pOutput, "Parse_FormulaParserEqn(): Something is left in the operation stack\n" );
else
fprintf( pOutput, "Parse_FormulaParserEqn(): Something is left in the function stack\n" );
}
else
fprintf( pOutput, "Parse_FormulaParserEqn(): The input string is empty\n" );
}
free( pFormula );
return NULL;
}
/**Function*************************************************************
Synopsis [Performs the operation on the top entries in the stack.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Hop_Obj_t * Parse_ParserPerformTopOp( Hop_Man_t * pMan, Parse_StackFn_t * pStackFn, int Oper )
{
Hop_Obj_t * gArg1, * gArg2, * gFunc;
// perform the given operation
gArg2 = Parse_StackFnPop( pStackFn );
gArg1 = Parse_StackFnPop( pStackFn );
if ( Oper == PARSE_EQN_OPER_AND )
gFunc = Hop_And( pMan, gArg1, gArg2 );
else if ( Oper == PARSE_EQN_OPER_OR )
gFunc = Hop_Or( pMan, gArg1, gArg2 );
else
return NULL;
// Cudd_Ref( gFunc );
// Cudd_RecursiveDeref( dd, gArg1 );
// Cudd_RecursiveDeref( dd, gArg2 );
Parse_StackFnPush( pStackFn, gFunc );
return gFunc;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

4
src/bdd/parse/parseInt.h
View File

@ -57,8 +57,8 @@ typedef struct ParseStackOpStruct Parse_StackOp_t; // the operation stack
/*=== parseStack.c =============================================================*/
extern Parse_StackFn_t * Parse_StackFnStart ( int nDepth );
extern bool Parse_StackFnIsEmpty( Parse_StackFn_t * p );
extern void Parse_StackFnPush ( Parse_StackFn_t * p, DdNode * bFunc );
extern DdNode * Parse_StackFnPop ( Parse_StackFn_t * p );
extern void Parse_StackFnPush ( Parse_StackFn_t * p, void * bFunc );
extern void * Parse_StackFnPop ( Parse_StackFn_t * p );
extern void Parse_StackFnFree ( Parse_StackFn_t * p );
extern Parse_StackOp_t * Parse_StackOpStart ( int nDepth );

8
src/bdd/parse/parseStack.c
View File

@ -24,7 +24,7 @@
struct ParseStackFnStruct
{
DdNode ** pData; // the array of elements
void ** pData; // the array of elements
int Top; // the index
int Size; // the stack size
};
@ -56,7 +56,7 @@ Parse_StackFn_t * Parse_StackFnStart( int nDepth )
Parse_StackFn_t * p;
p = ALLOC( Parse_StackFn_t, 1 );
memset( p, 0, sizeof(Parse_StackFn_t) );
p->pData = ALLOC( DdNode *, nDepth );
p->pData = ALLOC( void *, nDepth );
p->Size = nDepth;
return p;
}
@ -88,7 +88,7 @@ bool Parse_StackFnIsEmpty( Parse_StackFn_t * p )
SeeAlso []
***********************************************************************/
void Parse_StackFnPush( Parse_StackFn_t * p, DdNode * bFunc )
void Parse_StackFnPush( Parse_StackFn_t * p, void * bFunc )
{
if ( p->Top >= p->Size )
{
@ -109,7 +109,7 @@ void Parse_StackFnPush( Parse_StackFn_t * p, DdNode * bFunc )
SeeAlso []
***********************************************************************/
DdNode * Parse_StackFnPop( Parse_StackFn_t * p )
void * Parse_StackFnPop( Parse_StackFn_t * p )
{
if ( p->Top == 0 )
{

4
src/map/fpga/fpgaCreate.c
View File

@ -226,8 +226,8 @@ void Fpga_ManFree( Fpga_Man_t * p )
Fpga_NodeVecFree( p->vAnds );
if ( p->vNodesAll )
Fpga_NodeVecFree( p->vNodesAll );
Extra_MmFixedStop( p->mmNodes, 0 );
Extra_MmFixedStop( p->mmCuts, 0 );
Extra_MmFixedStop( p->mmNodes );
Extra_MmFixedStop( p->mmCuts );
FREE( p->ppOutputNames );
FREE( p->pInputArrivals );
FREE( p->pInputs );

2
src/map/if/ifTime.c
View File

@ -206,7 +206,7 @@ void If_CutSortInputPins( If_Man_t * p, If_Cut_t * pCut, int * pPinPerm, float *
pPinPerm[best_i] = temp;
}
// verify
assert( pPinPerm[0] < pCut->nLeaves );
assert( pPinPerm[0] < (int)pCut->nLeaves );
for ( i = 1; i < (int)pCut->nLeaves; i++ )
{
assert( pPinPerm[i] < (int)pCut->nLeaves );

4
src/map/mapper/mapperCreate.c
View File

@ -261,8 +261,8 @@ void Map_ManFree( Map_Man_t * p )
if ( p->uCanons ) free( p->uCanons );
if ( p->uPhases ) free( p->uPhases );
if ( p->pCounters ) free( p->pCounters );
Extra_MmFixedStop( p->mmNodes, 0 );
Extra_MmFixedStop( p->mmCuts, 0 );
Extra_MmFixedStop( p->mmNodes );
Extra_MmFixedStop( p->mmCuts );
FREE( p->pInputArrivals );
FREE( p->pInputs );
FREE( p->pOutputs );

6
src/map/mapper/mapperLib.c
View File

@ -147,9 +147,9 @@ void Map_SuperLibFree( Map_SuperLib_t * p )
Map_SuperTableFree( p->tTableC );
if ( p->tTable )
Map_SuperTableFree( p->tTable );
Extra_MmFixedStop( p->mmSupers, 0 );
Extra_MmFixedStop( p->mmEntries, 0 );
Extra_MmFlexStop( p->mmForms, 0 );
Extra_MmFixedStop( p->mmSupers );
Extra_MmFixedStop( p->mmEntries );
Extra_MmFlexStop( p->mmForms );
FREE( p->ppSupers );
FREE( p );
}

2
src/map/mio/mioUtils.c
View File

@ -53,7 +53,7 @@ void Mio_LibraryDelete( Mio_Library_t * pLib )
FREE( pLib->pName );
Mio_LibraryForEachGateSafe( pLib, pGate, pGate2 )
Mio_GateDelete( pGate );
Extra_MmFlexStop( pLib->pMmFlex, 0 );
Extra_MmFlexStop( pLib->pMmFlex );
Vec_StrFree( pLib->vCube );
if ( pLib->tName2Gate )
st_free_table( pLib->tName2Gate );

2
src/map/super/superAnd.c
View File

@ -183,7 +183,7 @@ Super2_Man_t * Super2_ManStart()
***********************************************************************/
void Super2_ManStop( Super2_Man_t * pMan )
{
Extra_MmFixedStop( pMan->pMem, 0 );
Extra_MmFixedStop( pMan->pMem );
stmm_free_table( pMan->tTable );
free( pMan );
}

2
src/map/super/superGate.c
View File

@ -886,7 +886,7 @@ Super_Man_t * Super_ManStart()
***********************************************************************/
void Super_ManStop( Super_Man_t * pMan )
{
Extra_MmFixedStop( pMan->pMem, 0 );
Extra_MmFixedStop( pMan->pMem );
if ( pMan->tTable ) stmm_free_table( pMan->tTable );
FREE( pMan->pGates );
free( pMan );

9
src/misc/extra/extra.h
View File

@ -291,7 +291,7 @@ extern int Extra_BitMatrixIsClique( Extra_BitMat_t * p );
/*=== extraUtilFile.c ========================================================*/
extern char * Extra_FileGetSimilarName( char * pFileNameWrong, char * pS1, char * pS2, char * pS3, char * pS4, char * pS5 );
extern int Extra_FileNameCheckExtension( char * FileName, char * Extension );
extern char * Extra_FileNameExtension( char * FileName );
extern char * Extra_FileNameAppend( char * pBase, char * pSuffix );
extern char * Extra_FileNameGeneric( char * FileName );
extern int Extra_FileSize( char * pFileName );
@ -325,19 +325,20 @@ typedef struct Extra_MmStep_t_ Extra_MmStep_t;
// fixed-size-block memory manager
extern Extra_MmFixed_t * Extra_MmFixedStart( int nEntrySize );
extern void Extra_MmFixedStop( Extra_MmFixed_t * p, int fVerbose );
extern void Extra_MmFixedStop( Extra_MmFixed_t * p );
extern char * Extra_MmFixedEntryFetch( Extra_MmFixed_t * p );
extern void Extra_MmFixedEntryRecycle( Extra_MmFixed_t * p, char * pEntry );
extern void Extra_MmFixedRestart( Extra_MmFixed_t * p );
extern int Extra_MmFixedReadMemUsage( Extra_MmFixed_t * p );
// flexible-size-block memory manager
extern Extra_MmFlex_t * Extra_MmFlexStart();
extern void Extra_MmFlexStop( Extra_MmFlex_t * p, int fVerbose );
extern void Extra_MmFlexStop( Extra_MmFlex_t * p );
extern void Extra_MmFlexPrint( Extra_MmFlex_t * p );
extern char * Extra_MmFlexEntryFetch( Extra_MmFlex_t * p, int nBytes );
extern int Extra_MmFlexReadMemUsage( Extra_MmFlex_t * p );
// hierarchical memory manager
extern Extra_MmStep_t * Extra_MmStepStart( int nSteps );
extern void Extra_MmStepStop( Extra_MmStep_t * p, int fVerbose );
extern void Extra_MmStepStop( Extra_MmStep_t * p );
extern char * Extra_MmStepEntryFetch( Extra_MmStep_t * p, int nBytes );
extern void Extra_MmStepEntryRecycle( Extra_MmStep_t * p, char * pEntry, int nBytes );
extern int Extra_MmStepReadMemUsage( Extra_MmStep_t * p );

19
src/misc/extra/extraUtilFile.c
View File

@ -110,7 +110,7 @@ char * Extra_FileGetSimilarName( char * pFileNameWrong, char * pS1, char * pS2,
/**Function*************************************************************
Synopsis []
Synopsis [Returns the pointer to the file extension.]
Description []
@ -119,21 +119,14 @@ char * Extra_FileGetSimilarName( char * pFileNameWrong, char * pS1, char * pS2,
SeeAlso []
***********************************************************************/
int Extra_FileNameCheckExtension( char * FileName, char * Extension )
char * Extra_FileNameExtension( char * FileName )
{
char * pDot;
// find "dot" if it is present in the file name
// pDot = strstr( FileName, "." );
// find the last "dot" in the file name, if it is present
for ( pDot = FileName + strlen(FileName)-1; pDot >= FileName; pDot-- )
if ( *pDot == '.' )
break;
if ( *pDot != '.' )
return 0;
// check the extension
if ( pDot && strcmp( pDot+1, Extension ) == 0 )
return 1;
else
return 0;
return pDot + 1;
return NULL;
}
/**Function*************************************************************
@ -255,8 +248,8 @@ char * Extra_FileRead( FILE * pFile )
char * Extra_TimeStamp()
{
static char Buffer[100];
time_t ltime;
char * TimeStamp;
time_t ltime;
// get the current time
time( &ltime );
TimeStamp = asctime( localtime( &ltime ) );

60
src/misc/extra/extraUtilMemory.c
View File

@ -155,18 +155,30 @@ Extra_MmFixed_t * Extra_MmFixedStart( int nEntrySize )
SeeAlso []
***********************************************************************/
void Extra_MmFixedStop( Extra_MmFixed_t * p, int fVerbose )
void Extra_MmFixedPrint( Extra_MmFixed_t * p )
{
printf( "Fixed memory manager: Entry = %5d. Chunk = %5d. Chunks used = %5d.\n",
p->nEntrySize, p->nChunkSize, p->nChunks );
printf( " Entries used = %8d. Entries peak = %8d. Memory used = %8d. Memory alloc = %8d.\n",
p->nEntriesUsed, p->nEntriesMax, p->nEntrySize * p->nEntriesUsed, p->nMemoryAlloc );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Extra_MmFixedStop( Extra_MmFixed_t * p )
{
int i;
if ( p == NULL )
return;
if ( fVerbose )
{
printf( "Fixed memory manager: Entry = %5d. Chunk = %5d. Chunks used = %5d.\n",
p->nEntrySize, p->nChunkSize, p->nChunks );
printf( " Entries used = %8d. Entries peak = %8d. Memory used = %8d. Memory alloc = %8d.\n",
p->nEntriesUsed, p->nEntriesMax, p->nEntrySize * p->nEntriesUsed, p->nMemoryAlloc );
}
for ( i = 0; i < p->nChunks; i++ )
free( p->pChunks[i] );
free( p->pChunks );
@ -343,18 +355,30 @@ Extra_MmFlex_t * Extra_MmFlexStart()
SeeAlso []
***********************************************************************/
void Extra_MmFlexStop( Extra_MmFlex_t * p, int fVerbose )
void Extra_MmFlexPrint( Extra_MmFlex_t * p )
{
printf( "Flexible memory manager: Chunk size = %d. Chunks used = %d.\n",
p->nChunkSize, p->nChunks );
printf( " Entries used = %d. Memory used = %d. Memory alloc = %d.\n",
p->nEntriesUsed, p->nMemoryUsed, p->nMemoryAlloc );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Extra_MmFlexStop( Extra_MmFlex_t * p )
{
int i;
if ( p == NULL )
return;
if ( fVerbose )
{
printf( "Flexible memory manager: Chunk size = %d. Chunks used = %d.\n",
p->nChunkSize, p->nChunks );
printf( " Entries used = %d. Memory used = %d. Memory alloc = %d.\n",
p->nEntriesUsed, p->nMemoryUsed, p->nMemoryAlloc );
}
for ( i = 0; i < p->nChunks; i++ )
free( p->pChunks[i] );
free( p->pChunks );
@ -482,11 +506,11 @@ Extra_MmStep_t * Extra_MmStepStart( int nSteps )
SeeAlso []
***********************************************************************/
void Extra_MmStepStop( Extra_MmStep_t * p, int fVerbose )
void Extra_MmStepStop( Extra_MmStep_t * p )
{
int i;
for ( i = 0; i < p->nMems; i++ )
Extra_MmFixedStop( p->pMems[i], fVerbose );
Extra_MmFixedStop( p->pMems[i] );
// if ( p->pLargeChunks )
// {
// for ( i = 0; i < p->nLargeChunks; i++ )

8
src/misc/mvc/mvcMan.c
View File

@ -63,10 +63,10 @@ Mvc_Manager_t * Mvc_ManagerStart()
***********************************************************************/
void Mvc_ManagerFree( Mvc_Manager_t * p )
{
Extra_MmFixedStop( p->pMan1, 0 );
Extra_MmFixedStop( p->pMan2, 0 );
Extra_MmFixedStop( p->pMan4, 0 );
Extra_MmFixedStop( p->pManC, 0 );
Extra_MmFixedStop( p->pMan1 );
Extra_MmFixedStop( p->pMan2 );
Extra_MmFixedStop( p->pMan4 );
Extra_MmFixedStop( p->pManC );
free( p );
}

2
src/misc/nm/nmApi.c
View File

@ -72,7 +72,7 @@ Nm_Man_t * Nm_ManCreate( int nSize )
***********************************************************************/
void Nm_ManFree( Nm_Man_t * p )
{
Extra_MmFlexStop( p->pMem, 0 );
Extra_MmFlexStop( p->pMem );
FREE( p->pBinsI2N );
FREE( p->pBinsN2I );
FREE( p );

4
src/misc/st/stmm.c
View File

@ -105,7 +105,7 @@ stmm_free_table (table)
// no need to deallocate entries because they are in the memory manager now
// added by alanmi
if ( table->pMemMan )
Extra_MmFixedStop (table->pMemMan, 0);
Extra_MmFixedStop (table->pMemMan);
FREE (table->bins);
FREE (table);
}
@ -446,7 +446,7 @@ stmm_copy (old_table)
}
}
*/
Extra_MmFixedStop (new_table->pMemMan, 0);
Extra_MmFixedStop (new_table->pMemMan);
FREE (new_table->bins);
FREE (new_table);

19
src/misc/vec/vecAtt.h
View File

@ -26,7 +26,6 @@
////////////////////////////////////////////////////////////////////////
#include <stdio.h>
#include "extra.h"
////////////////////////////////////////////////////////////////////////
/// PARAMETERS ///
@ -46,9 +45,9 @@ typedef enum {
VEC_ATTR_LEVEL_REV, // 9
VEC_ATTR_RETIME_LAG, // 10
VEC_ATTR_FRAIG, // 11
VEC_ATTR_DATA1, // 12
VEC_ATTR_DATA2, // 13
VEC_ATTR_DATA3, // 14
VEC_ATTR_MVVAR, // 12
VEC_ATTR_DATA1, // 13
VEC_ATTR_DATA2, // 14
VEC_ATTR_TOTAL_NUM // 15
} Vec_AttrType_t;
@ -244,12 +243,12 @@ static inline void Vec_AttGrow( Vec_Att_t * p, int nCapMin )
if ( p->pArrayInt )
{
p->pArrayInt = REALLOC( int, p->pArrayInt, nCapMin );
memset( p->pArrayInt + nCapMin, 0xff, sizeof(int) * (nCapMin - p->nCap) );
memset( p->pArrayInt + p->nCap, 0xff, sizeof(int) * (nCapMin - p->nCap) );
}
else
{
p->pArrayPtr = REALLOC( void *, p->pArrayPtr, nCapMin );
memset( p->pArrayPtr + nCapMin, 0, sizeof(void *) * (nCapMin - p->nCap) );
memset( p->pArrayPtr + p->nCap, 0, sizeof(void *) * (nCapMin - p->nCap) );
}
p->nCap = nCapMin;
}
@ -270,7 +269,7 @@ static inline void Vec_AttWriteEntry( Vec_Att_t * p, int i, void * pEntry )
assert( p->pArrayPtr );
assert( p->pFuncStartObj == NULL );
if ( i >= p->nCap )
Vec_AttGrow( p, (2 * p->nCap > i)? 2 * p->nCap : i );
Vec_AttGrow( p, (2 * p->nCap > i)? 2 * p->nCap : i + 10 );
p->pArrayPtr[i] = pEntry;
}
@ -290,7 +289,7 @@ static inline void Vec_AttWriteEntryInt( Vec_Att_t * p, int i, int Entry )
assert( p->pArrayInt );
assert( p->pFuncStartObj == NULL );
if ( i >= p->nCap )
Vec_AttGrow( p, (2 * p->nCap > i)? 2 * p->nCap : i );
Vec_AttGrow( p, (2 * p->nCap > i)? 2 * p->nCap : i + 10 );
p->pArrayInt[i] = Entry;
}
@ -309,7 +308,7 @@ static inline void * Vec_AttEntry( Vec_Att_t * p, int i )
{
assert( p->pArrayPtr );
if ( i >= p->nCap )
Vec_AttGrow( p, (2 * p->nCap > i)? 2 * p->nCap : i );
Vec_AttGrow( p, (2 * p->nCap > i)? 2 * p->nCap : i + 10 );
if ( p->pArrayPtr[i] == NULL && p->pFuncStartObj )
p->pArrayPtr[i] = p->pFuncStartObj( p->pMan );
return p->pArrayPtr[i];
@ -331,7 +330,7 @@ static inline int Vec_AttEntryInt( Vec_Att_t * p, int i )
assert( p->pArrayInt );
assert( p->pMan == NULL );
if ( i >= p->nCap )
Vec_AttGrow( p, (2 * p->nCap > i)? 2 * p->nCap : i );
Vec_AttGrow( p, (2 * p->nCap > i)? 2 * p->nCap : i + 10 );
return p->pArrayInt[i];
}

1
src/misc/vec/vecFlt.h
View File

@ -26,7 +26,6 @@
////////////////////////////////////////////////////////////////////////
#include <stdio.h>
#include "extra.h"
////////////////////////////////////////////////////////////////////////
/// PARAMETERS ///

1
src/misc/vec/vecInt.h
View File

@ -25,6 +25,7 @@
/// INCLUDES ///
////////////////////////////////////////////////////////////////////////
#include <stdio.h>
#include "extra.h"
////////////////////////////////////////////////////////////////////////

1
src/misc/vec/vecPtr.h
View File

@ -26,7 +26,6 @@
////////////////////////////////////////////////////////////////////////
#include <stdio.h>
#include "extra.h"
////////////////////////////////////////////////////////////////////////
/// PARAMETERS ///

1
src/misc/vec/vecStr.h
View File

@ -26,7 +26,6 @@
////////////////////////////////////////////////////////////////////////
#include <stdio.h>
#include "extra.h"
////////////////////////////////////////////////////////////////////////
/// PARAMETERS ///

1
src/misc/vec/vecVec.h
View File

@ -26,7 +26,6 @@
////////////////////////////////////////////////////////////////////////
#include <stdio.h>
#include "extra.h"
////////////////////////////////////////////////////////////////////////
/// PARAMETERS ///

1
src/opt/cut/abcCut.c
View File

@ -20,7 +20,6 @@
#include "abc.h"
#include "cut.h"
#include "seqInt.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///

2
src/opt/cut/cutMan.c
View File

@ -145,7 +145,7 @@ void Cut_ManStop( Cut_Man_t * p )
if ( p->vCutPairs ) Vec_IntFree( p->vCutPairs );
if ( p->puTemp[0] ) free( p->puTemp[0] );
Extra_MmFixedStop( p->pMmCuts, 0 );
Extra_MmFixedStop( p->pMmCuts );
free( p );
}

2
src/opt/cut/cutOracle.c
View File

@ -148,7 +148,7 @@ void Cut_OracleStop( Cut_Oracle_t * p )
if ( p->vNodeStarts ) Vec_IntFree( p->vNodeStarts );
if ( p->vCutPairs ) Vec_IntFree( p->vCutPairs );
Extra_MmFixedStop( p->pMmCuts, 0 );
Extra_MmFixedStop( p->pMmCuts );
free( p );
}

2
src/opt/cut/cutPre22.c
View File

@ -798,7 +798,7 @@ Cut_CMan_t * Cut_CManStart()
void Cut_CManStop( Cut_CMan_t * p )
{
st_free_table( p->tTable );
Extra_MmFixedStop( p->pMem, 0 );
Extra_MmFixedStop( p->pMem );
free( p );
}
/**Function*************************************************************

65
src/opt/dec/decPrint.c
View File

@ -101,7 +101,7 @@ void Dec_GraphPrint( FILE * pFile, Dec_Graph_t * pGraph, char * pNamesIn[], char
SeeAlso []
***********************************************************************/
void Dec_GraphPrint_rec( FILE * pFile, Dec_Graph_t * pGraph, Dec_Node_t * pNode, int fCompl, char * pNamesIn[], int * pPos, int LitSizeMax )
void Dec_GraphPrint2_rec( FILE * pFile, Dec_Graph_t * pGraph, Dec_Node_t * pNode, int fCompl, char * pNamesIn[], int * pPos, int LitSizeMax )
{
Dec_Node_t * pNode0, * pNode1;
pNode0 = Dec_GraphNode(pGraph, pNode->eEdge0.Node);
@ -154,6 +154,69 @@ void Dec_GraphPrint_rec( FILE * pFile, Dec_Graph_t * pGraph, Dec_Node_t * pNode,
assert( 0 );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Dec_GraphPrint_rec( FILE * pFile, Dec_Graph_t * pGraph, Dec_Node_t * pNode, int fCompl, char * pNamesIn[], int * pPos, int LitSizeMax )
{
Dec_Node_t * pNode0, * pNode1;
Dec_Node_t * pNode00, * pNode01, * pNode10, * pNode11;
pNode0 = Dec_GraphNode(pGraph, pNode->eEdge0.Node);
pNode1 = Dec_GraphNode(pGraph, pNode->eEdge1.Node);
if ( Dec_GraphNodeIsVar(pGraph, pNode) ) // FT_NODE_LEAF )
{
(*pPos) += Dec_GraphPrintGetLeafName( pFile, Dec_GraphNodeInt(pGraph,pNode), fCompl, pNamesIn );
return;
}
if ( !Dec_GraphNodeIsVar(pGraph, pNode0) && !Dec_GraphNodeIsVar(pGraph, pNode1) )
{
pNode00 = Dec_GraphNode(pGraph, pNode0->eEdge0.Node);
pNode01 = Dec_GraphNode(pGraph, pNode0->eEdge1.Node);
pNode10 = Dec_GraphNode(pGraph, pNode1->eEdge0.Node);
pNode11 = Dec_GraphNode(pGraph, pNode1->eEdge1.Node);
if ( (pNode00 == pNode10 || pNode00 == pNode11) && (pNode01 == pNode10 || pNode01 == pNode11) )
{
fprintf( pFile, "(" );
(*pPos)++;
Dec_GraphPrint_rec( pFile, pGraph, pNode00, pNode00->fCompl0, pNamesIn, pPos, LitSizeMax );
fprintf( pFile, " # " );
(*pPos) += 3;
Dec_GraphPrint_rec( pFile, pGraph, pNode01, pNode01->fCompl1, pNamesIn, pPos, LitSizeMax );
fprintf( pFile, ")" );
(*pPos)++;
return;
}
}
if ( fCompl )
{
fprintf( pFile, "(" );
(*pPos)++;
Dec_GraphPrint_rec( pFile, pGraph, pNode0, !pNode->fCompl0, pNamesIn, pPos, LitSizeMax );
fprintf( pFile, " + " );
(*pPos) += 3;
Dec_GraphPrint_rec( pFile, pGraph, pNode1, !pNode->fCompl1, pNamesIn, pPos, LitSizeMax );
fprintf( pFile, ")" );
(*pPos)++;
}
else
{
fprintf( pFile, "(" );
(*pPos)++;
Dec_GraphPrint_rec( pFile, pGraph, pNode0, pNode->fCompl0, pNamesIn, pPos, LitSizeMax );
Dec_GraphPrint_rec( pFile, pGraph, pNode1, pNode->fCompl1, pNamesIn, pPos, LitSizeMax );
fprintf( pFile, ")" );
(*pPos)++;
}
}
/**Function*************************************************************
Synopsis []

2
src/opt/fxu/fxuMatrix.c
View File

@ -130,7 +130,7 @@ void Fxu_MatrixDelete( Fxu_Matrix * p )
MEM_FREE_FXU( p, Fxu_Var, 1, pVar );
}
#else
Extra_MmFixedStop( p->pMemMan, 0 );
Extra_MmFixedStop( p->pMemMan );
#endif
Vec_PtrFree( p->vPairs );

5
src/opt/rwr/rwr.h
View File

@ -95,6 +95,9 @@ struct Rwr_Node_t_ // 24 bytes
{
int Id; // ID
int TravId; // traversal ID
short nScore;
short nGain;
short nAdded;
unsigned uTruth : 16; // truth table
unsigned Volume : 8; // volume
unsigned Level : 6; // level
@ -123,6 +126,8 @@ static inline Rwr_Node_t * Rwr_NotCond( Rwr_Node_t * p, int c ) { return (Rwr_N
extern void Rwr_ManPreprocess( Rwr_Man_t * p );
/*=== rwrEva.c ========================================================*/
extern int Rwr_NodeRewrite( Rwr_Man_t * p, Cut_Man_t * pManCut, Abc_Obj_t * pNode, int fUpdateLevel, int fUseZeros );
extern void Rwr_ScoresClean( Rwr_Man_t * p );
extern void Rwr_ScoresReport( Rwr_Man_t * p );
/*=== rwrLib.c ========================================================*/
extern void Rwr_ManPrecompute( Rwr_Man_t * p );
extern Rwr_Node_t * Rwr_ManAddVar( Rwr_Man_t * p, unsigned uTruth, int fPrecompute );

112
src/opt/rwr/rwrEva.c
View File

@ -198,7 +198,9 @@ p->timeRes += clock() - clk;
p->nScores[p->pMap[uTruthBest]]++;
p->nNodesGained += GainBest;
if ( fUseZeros || GainBest > 0 )
{
p->nNodesRewritten++;
}
// report the progress
if ( fVeryVerbose && GainBest > 0 )
@ -257,6 +259,14 @@ Dec_Graph_t * Rwr_CutEvaluate( Rwr_Man_t * p, Abc_Obj_t * pRoot, Cut_Cut_t * pCu
GainBest = nNodesSaved - nNodesAdded;
pGraphBest = pGraphCur;
// score the graph
if ( GainBest > 0 )
{
pNode->nScore++;
pNode->nGain += GainBest;
pNode->nAdded += nNodesAdded;
}
// if ( GainBest > 0 )
// printf( "%d %d ", nNodesSaved, nNodesAdded );
}
@ -267,7 +277,6 @@ Dec_Graph_t * Rwr_CutEvaluate( Rwr_Man_t * p, Abc_Obj_t * pRoot, Cut_Cut_t * pCu
return pGraphBest;
}
/**Function*************************************************************
Synopsis [Checks the type of the cut.]
@ -418,6 +427,107 @@ int Rwr_NodeGetDepth_rec( Abc_Obj_t * pObj, Vec_Ptr_t * vLeaves )
return 1 + ABC_MAX( Depth0, Depth1 );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Rwr_ScoresClean( Rwr_Man_t * p )
{
Vec_Ptr_t * vSubgraphs;
Rwr_Node_t * pNode;
int i, k;
for ( i = 0; i < p->vClasses->nSize; i++ )
{
vSubgraphs = Vec_VecEntry( p->vClasses, i );
Vec_PtrForEachEntry( vSubgraphs, pNode, k )
pNode->nScore = pNode->nGain = pNode->nAdded = 0;
}
}
static int Gains[222];
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Rwr_ScoresCompare( int * pNum1, int * pNum2 )
{
if ( Gains[*pNum1] > Gains[*pNum2] )
return -1;
if ( Gains[*pNum1] < Gains[*pNum2] )
return 1;
return 0;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Rwr_ScoresReport( Rwr_Man_t * p )
{
extern void Ivy_TruthDsdComputePrint( unsigned uTruth );
int Perm[222];
Vec_Ptr_t * vSubgraphs;
Rwr_Node_t * pNode;
int i, iNew, k;
unsigned uTruth;
// collect total gains
assert( p->vClasses->nSize == 222 );
for ( i = 0; i < p->vClasses->nSize; i++ )
{
Perm[i] = i;
Gains[i] = 0;
vSubgraphs = Vec_VecEntry( p->vClasses, i );
Vec_PtrForEachEntry( vSubgraphs, pNode, k )
Gains[i] += pNode->nGain;
}
// sort the gains
qsort( Perm, 222, sizeof(int), (int (*)(const void *, const void *))Rwr_ScoresCompare );
// print classes
for ( i = 0; i < p->vClasses->nSize; i++ )
{
iNew = Perm[i];
if ( Gains[iNew] == 0 )
break;
vSubgraphs = Vec_VecEntry( p->vClasses, iNew );
printf( "CLASS %3d: Subgr = %3d. Total gain = %6d. ", iNew, Vec_PtrSize(vSubgraphs), Gains[iNew] );
uTruth = (unsigned)p->pMapInv[iNew];
Extra_PrintBinary( stdout, &uTruth, 16 );
printf( " " );
Ivy_TruthDsdComputePrint( (unsigned)p->pMapInv[iNew] | ((unsigned)p->pMapInv[iNew] << 16) );
Vec_PtrForEachEntry( vSubgraphs, pNode, k )
{
if ( pNode->nScore == 0 )
continue;
printf( " %2d: S=%5d. A=%5d. G=%6d. ", k, pNode->nScore, pNode->nAdded, pNode->nGain );
Dec_GraphPrint( stdout, (Dec_Graph_t *)pNode->pNext, NULL, NULL );
}
}
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

5
src/opt/rwr/rwrMan.c
View File

@ -118,7 +118,7 @@ void Rwr_ManStop( Rwr_Man_t * p )
Vec_IntFree( p->vLevNums );
Vec_PtrFree( p->vFanins );
Vec_PtrFree( p->vFaninsCur );
Extra_MmFixedStop( p->pMmNode, 0 );
Extra_MmFixedStop( p->pMmNode );
FREE( p->pMapInv );
free( p->pTable );
free( p->pPractical );
@ -159,7 +159,7 @@ void Rwr_ManPrintStats( Rwr_Man_t * p )
PRT( "Update ", p->timeUpdate );
PRT( "TOTAL ", p->timeTotal );
/*
printf( "The scores are:\n" );
for ( i = 0; i < 222; i++ )
if ( p->nScores[i] > 0 )
@ -168,6 +168,7 @@ void Rwr_ManPrintStats( Rwr_Man_t * p )
printf( "%3d = %8d canon = %5d ", i, p->nScores[i], p->pMapInv[i] );
Ivy_TruthDsdComputePrint( (unsigned)p->pMapInv[i] | ((unsigned)p->pMapInv[i] << 16) );
}
*/
printf( "\n" );
}

2
src/opt/sim/simMan.c
View File

@ -210,7 +210,7 @@ void Sim_ManStop( Sim_Man_t * p )
if ( p->vSuppStr ) Sim_UtilInfoFree( p->vSuppStr );
// if ( p->vSuppFun ) Sim_UtilInfoFree( p->vSuppFun );
if ( p->vSuppTargs ) Vec_VecFree( p->vSuppTargs );
if ( p->pMmPat ) Extra_MmFixedStop( p->pMmPat, 0 );
if ( p->pMmPat ) Extra_MmFixedStop( p->pMmPat );
if ( p->vFifo ) Vec_PtrFree( p->vFifo );
if ( p->vDiffs ) Vec_IntFree( p->vDiffs );
free( p );

4
src/opt/sim/simSymSim.c
View File

@ -65,8 +65,8 @@ clk = clock();
Abc_NtkForEachCo( p->pNtk, pNode, i )
{
pNode = Abc_ObjFanin0(pNode);
if ( Abc_ObjIsCi(pNode) || Abc_AigNodeIsConst(pNode) )
continue;
// if ( Abc_ObjIsCi(pNode) || Abc_AigNodeIsConst(pNode) )
// continue;
nPairsTotal = Vec_IntEntry(p->vPairsTotal, i);
nPairsSym = Vec_IntEntry(p->vPairsSym, i);
nPairsNonSym = Vec_IntEntry(p->vPairsNonSym,i);

2
src/sat/asat/jfront.c
View File

@ -177,7 +177,7 @@ void Asat_JManStop( solver * pSat )
if ( p == NULL )
return;
pSat->pJMan = NULL;
Extra_MmFlexStop( p->pMem, 0 );
Extra_MmFlexStop( p->pMem );
Vec_PtrFree( p->vVars );
free( p );
}

2
src/sat/csat/csat_apis.c
View File

@ -111,7 +111,7 @@ void ABC_ReleaseManager( ABC_Manager mng )
ABC_TargetResFree(p_res);
if ( mng->tNode2Name ) stmm_free_table( mng->tNode2Name );
if ( mng->tName2Node ) stmm_free_table( mng->tName2Node );
if ( mng->pMmNames ) Extra_MmFlexStop( mng->pMmNames, 0 );
if ( mng->pMmNames ) Extra_MmFlexStop( mng->pMmNames );
if ( mng->pNtk ) Abc_NtkDelete( mng->pNtk );
if ( mng->pTarget ) Abc_NtkDelete( mng->pTarget );
if ( mng->vNodes ) Vec_PtrFree( mng->vNodes );

66
todo.txt
View File

@ -1,56 +1,26 @@
Minor things:
- add required time support
- clean end-of-line markers (CR is more preferable than CR-LF)
- prevent node name clash between PO and internal names (i.e. [484])
- add the output of ABC version/platform in the output files
- fix gcc compiler warnings
Major things:
- substantially improving performance of FRAIGing
(used in equivalence checking and lossless synthesis)
- developing a new (more efficient and faster) AIG rewriting package
- implementing additional rewriting options for delay optimization
- making technology mapping applicable to very large designs by adding
on-demand cut computation currenlty available as a stand-alone command "cut"
- experimenting with yield-aware standard-cell mapping
- developing a mapper for arbitrary programmable macrocell
architecture specified using a configuration file (this mapper should work
for both cell-evalution and mainstream FPGA mapping)
- developing incremental retiming and incremental integrated sequential
synthesis
- developing sequential verification combined with integrated sequential
synthesis
Other great projects:
- hierarchical BLIF input in ABC (output of black boxes)
- required time support
- printing ABC version/platform in the output files
- fix gcc compiler warnings
- port "mfs" from MVSIS
- improve AIG rewriting package
- unify functional representation of local functions
- additional rewriting options for delay optimization
- experiment with yield-aware standard-cell mapping
- improving area recovery in integrated sequential synthesis
- high-effort logic synthesis for hard miters (cofactoring, Boolean division)
- incremental retiming and sequential integration
- 5-6 input AIG rewriting using new ideas
- placement-aware mapping
- mapping into MV cells
- better ways of constructing BDDs
- SAT solver with linear constraints
- specialized synthesis for EXORs and large MUXes
- sequential AIG rewriting
- sequential AIG rewriting initial state computation
- placement-aware mapping
- sequential equivalence checking
- parser for Verilog netlists
- hierarchy manager (hierarchical BLIF/BLIF-MV parser)
Other:
- required time based on all cuts
- comparing tts of differently derived the same cut
- area flow based AIG rewriting
- cut frontier adjustment
- completely silent mode
High-priority changes:
- add a new mode to "fpga" to differentiate latch-to-latch and pad-to-latch paths
- support asynchronous set/reset in retiming and retiming/mapping
- port "mfs" into ABC
- reduce the latch count in the new version of "retime" and "spfga"