mirror of https://github.com/YosysHQ/abc.git
Experiments with functional matching.
This commit is contained in:
Alan Mishchenko
parent
ac16c95706
commit
7d9e3c2ffe
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@ -2519,6 +2519,10 @@ SOURCE=.\src\opt\sfm\sfmCore.c
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# End Source File
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# Begin Source File
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SOURCE=.\src\opt\sfm\sfmDec.c
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# End Source File
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# Begin Source File
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SOURCE=.\src\opt\sfm\sfmInt.h
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# End Source File
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# Begin Source File
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@ -1,5 +1,6 @@
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SRC += src/opt/sfm/sfmCnf.c \
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src/opt/sfm/sfmCore.c \
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src/opt/sfm/sfmDec.c \
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src/opt/sfm/sfmNtk.c \
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src/opt/sfm/sfmSat.c \
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src/opt/sfm/sfmWin.c
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@ -0,0 +1,549 @@
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/**CFile****************************************************************
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FileName [sfmDec.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [SAT-based optimization using internal don't-cares.]
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Synopsis [SAT-based decomposition.]
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Author [Alan Mishchenko]
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Affiliation [UC Berkeley]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: sfmDec.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "sfmInt.h"
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#include "bool/kit/kit.h"
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#include "base/abc/abc.h"
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ABC_NAMESPACE_IMPL_START
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////////////////////////////////////////////////////////////////////////
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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#define SFM_FAN_MAX 6
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typedef struct Sfm_Dec_t_ Sfm_Dec_t;
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struct Sfm_Dec_t_
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{
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// parameters
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Sfm_Par_t * pPars; // parameters
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// library
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Vec_Int_t vGateSizes; // fanin counts
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Vec_Wrd_t vGateFuncs; // gate truth tables
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Vec_Wec_t vGateCnfs; // gate CNFs
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// objects
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int iTarget; // target node
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Vec_Int_t vObjTypes; // PI (1), PO (2)
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Vec_Int_t vObjGates; // functionality
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Vec_Wec_t vObjFanins; // fanin IDs
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// solver
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sat_solver * pSat; // reusable solver
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Vec_Wec_t vClauses; // CNF clauses for the node
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Vec_Int_t vPols[2]; // onset/offset polarity
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Vec_Int_t vImpls[2]; // onset/offset implications
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Vec_Wrd_t vSets[2]; // onset/offset patterns
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int nPats[3];
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// temporary
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Vec_Int_t vTemp;
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Vec_Int_t vTemp2;
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// statistics
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abctime timeWin;
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abctime timeCnf;
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abctime timeSat;
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};
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Sfm_Dec_t * Sfm_DecStart()
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{
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Sfm_Dec_t * p = ABC_CALLOC( Sfm_Dec_t, 1 );
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p->pSat = sat_solver_new();
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return p;
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}
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void Sfm_DecStop( Sfm_Dec_t * p )
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{
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// library
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Vec_IntErase( &p->vGateSizes );
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Vec_WrdErase( &p->vGateFuncs );
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Vec_WecErase( &p->vGateCnfs );
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// objects
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Vec_IntErase( &p->vObjTypes );
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Vec_IntErase( &p->vObjGates );
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Vec_WecErase( &p->vObjFanins );
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// solver
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sat_solver_delete( p->pSat );
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Vec_WecErase( &p->vClauses );
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Vec_IntErase( &p->vPols[0] );
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Vec_IntErase( &p->vPols[1] );
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Vec_IntErase( &p->vImpls[0] );
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Vec_IntErase( &p->vImpls[1] );
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Vec_WrdErase( &p->vSets[0] );
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Vec_WrdErase( &p->vSets[1] );
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// temporary
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Vec_IntErase( &p->vTemp );
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Vec_IntErase( &p->vTemp2 );
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ABC_FREE( p );
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Sfm_DecCreateCnf( Sfm_Dec_t * p )
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{
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Vec_Str_t * vCnf, * vCnfBase;
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Vec_Int_t * vCover;
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word uTruth;
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int i, nCubes;
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vCnf = Vec_StrAlloc( 100 );
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vCover = Vec_IntAlloc( 100 );
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Vec_WecInit( &p->vGateCnfs, Vec_IntSize(&p->vGateSizes) );
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Vec_WrdForEachEntry( &p->vGateFuncs, uTruth, i )
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{
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nCubes = Sfm_TruthToCnf( uTruth, Vec_IntEntry(&p->vGateSizes, i), vCover, vCnf );
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vCnfBase = (Vec_Str_t *)Vec_WecEntry( &p->vGateCnfs, i );
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Vec_StrGrow( vCnfBase, Vec_StrSize(vCnf) );
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memcpy( Vec_StrArray(vCnfBase), Vec_StrArray(vCnf), Vec_StrSize(vCnf) );
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vCnfBase->nSize = Vec_StrSize(vCnf);
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}
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Vec_IntFree( vCover );
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Vec_StrFree( vCnf );
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Sfm_DecCreateAigLibrary( Sfm_Dec_t * p )
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{
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// const0
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Vec_IntPush( &p->vGateSizes, 0 );
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Vec_WrdPush( &p->vGateFuncs, 0 );
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// const1
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Vec_IntPush( &p->vGateSizes, 0 );
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Vec_WrdPush( &p->vGateFuncs, ~(word)0 );
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// buffer
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Vec_IntPush( &p->vGateSizes, 1 );
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Vec_WrdPush( &p->vGateFuncs, ABC_CONST(0xAAAAAAAAAAAAAAAA) );
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// inverter
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Vec_IntPush( &p->vGateSizes, 1 );
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Vec_WrdPush( &p->vGateFuncs, ABC_CONST(0x5555555555555555) );
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// and00
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Vec_IntPush( &p->vGateSizes, 2 );
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Vec_WrdPush( &p->vGateFuncs, ABC_CONST(0xCCCCCCCCCCCCCCCC) & ABC_CONST(0xAAAAAAAAAAAAAAAA) );
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// and01
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Vec_IntPush( &p->vGateSizes, 2 );
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Vec_WrdPush( &p->vGateFuncs, ABC_CONST(0xCCCCCCCCCCCCCCCC) &~ABC_CONST(0xAAAAAAAAAAAAAAAA) );
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// and10
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Vec_IntPush( &p->vGateSizes, 2 );
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Vec_WrdPush( &p->vGateFuncs,~ABC_CONST(0xCCCCCCCCCCCCCCCC) & ABC_CONST(0xAAAAAAAAAAAAAAAA) );
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// and11
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Vec_IntPush( &p->vGateSizes, 2 );
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Vec_WrdPush( &p->vGateFuncs,~ABC_CONST(0xCCCCCCCCCCCCCCCC) &~ABC_CONST(0xAAAAAAAAAAAAAAAA) );
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/*
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// xor
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Vec_IntPush( &p->vGateSizes, 2 );
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Vec_WrdPush( &p->vGateFuncs, ABC_CONST(0xCCCCCCCCCCCCCCCC) ^ ABC_CONST(0xAAAAAAAAAAAAAAAA) );
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// xnor
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Vec_IntPush( &p->vGateSizes, 2 );
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Vec_WrdPush( &p->vGateFuncs, ABC_CONST(0xCCCCCCCCCCCCCCCC) ^~ABC_CONST(0xAAAAAAAAAAAAAAAA) );
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// mux
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Vec_IntPush( &p->vGateSizes, 3 );
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Vec_WrdPush( &p->vGateFuncs, (ABC_CONST(0xF0F0F0F0F0F0F0F0) & ABC_CONST(0xCCCCCCCCCCCCCCCC)) | (ABC_CONST(0x0F0F0F0F0F0F0F0F) & ABC_CONST(0xAAAAAAAAAAAAAAAA)) );
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*/
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// derive CNF for these functions
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Sfm_DecCreateCnf( p );
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}
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void Vec_IntLift( Vec_Int_t * p, int Amount )
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{
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int i;
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for ( i = 0; i < p->nSize; i++ )
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p->pArray[i] += Amount;
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Sfm_DecPrepareSolver( Sfm_Dec_t * p )
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{
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abctime clk = Abc_Clock();
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Vec_Int_t * vLevel, * vClause;
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int i, k, Type, Gate, iObj, RetValue;
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int nSatVars = 2 * Vec_IntSize(&p->vObjTypes) - p->iTarget - 1;
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assert( Vec_IntSize(&p->vObjTypes) == Vec_IntSize(&p->vObjGates) );
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assert( p->iTarget < Vec_IntSize(&p->vObjTypes) );
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// collect variables of root nodes
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Vec_IntClear( &p->vTemp );
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Vec_IntForEachEntryStart( &p->vObjTypes, Type, i, p->iTarget )
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if ( Type == 2 )
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Vec_IntPush( &p->vTemp, i );
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assert( Vec_IntSize(&p->vTemp) > 0 );
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// create SAT solver
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sat_solver_restart( p->pSat );
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sat_solver_setnvars( p->pSat, nSatVars + Vec_IntSize(&p->vTemp) );
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// add CNF clauses for the TFI
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Vec_IntForEachEntryStop( &p->vObjTypes, Type, i, p->iTarget + 1 )
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{
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if ( Type == 1 )
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continue;
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// generate CNF
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Gate = Vec_IntEntry( &p->vObjGates, i );
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vLevel = Vec_WecEntry( &p->vObjFanins, i );
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Sfm_TranslateCnf( &p->vClauses, (Vec_Str_t *)Vec_WecEntry(&p->vGateCnfs, Gate), vLevel, -1 );
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// add clauses
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Vec_WecForEachLevel( &p->vClauses, vClause, k )
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{
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if ( Vec_IntSize(vClause) == 0 )
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break;
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RetValue = sat_solver_addclause( p->pSat, Vec_IntArray(vClause), Vec_IntArray(vClause) + Vec_IntSize(vClause) );
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if ( RetValue == 0 )
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return 0;
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}
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}
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// add CNF clauses for the TFO
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Vec_IntForEachEntryStart( &p->vObjTypes, Type, i, p->iTarget + 1 )
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{
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assert( Type != 1 );
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// generate CNF
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Gate = Vec_IntEntry( &p->vObjGates, i );
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vLevel = Vec_WecEntry( &p->vObjFanins, i );
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Vec_IntLift( vLevel, Vec_IntSize(&p->vObjTypes) );
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Sfm_TranslateCnf( &p->vClauses, (Vec_Str_t *)Vec_WecEntry(&p->vGateCnfs, Gate), vLevel, p->iTarget );
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Vec_IntLift( vLevel, Vec_IntSize(&p->vObjTypes) );
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// add clauses
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Vec_WecForEachLevel( &p->vClauses, vClause, k )
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{
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if ( Vec_IntSize(vClause) == 0 )
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break;
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RetValue = sat_solver_addclause( p->pSat, Vec_IntArray(vClause), Vec_IntArray(vClause) + Vec_IntSize(vClause) );
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if ( RetValue == 0 )
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return 0;
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}
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}
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if ( p->iTarget + 1 < Vec_IntSize(&p->vObjTypes) )
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{
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// create XOR clauses for the roots
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Vec_IntForEachEntry( &p->vTemp, iObj, i )
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{
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sat_solver_add_xor( p->pSat, iObj, 2*iObj + Vec_IntSize(&p->vObjTypes) - p->iTarget - 1, nSatVars++, 0 );
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Vec_IntWriteEntry( &p->vTemp, i, Abc_Var2Lit(nSatVars-1, 0) );
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}
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// make OR clause for the last nRoots variables
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RetValue = sat_solver_addclause( p->pSat, Vec_IntArray(&p->vTemp), Vec_IntLimit(&p->vTemp) );
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if ( RetValue == 0 )
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return 0;
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assert( nSatVars == sat_solver_nvars(p->pSat) );
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}
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else assert( Vec_IntSize(&p->vTemp) == 1 );
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// finalize
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RetValue = sat_solver_simplify( p->pSat );
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p->timeCnf += Abc_Clock() - clk;
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return 1;
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Sfm_DecPeformDec( Sfm_Dec_t * p )
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{
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int fVerbose = 1;
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int nBTLimit = 0;
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abctime clk = Abc_Clock();
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int i, k, c, status, Lits[2];
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// check stuck-at-0/1 (on/off-set empty)
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p->nPats[0] = p->nPats[1] = 0;
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for ( c = 0; c < 2; c++ )
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{
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Lits[0] = Abc_Var2Lit( p->iTarget, c );
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status = sat_solver_solve( p->pSat, Lits, Lits + 1, nBTLimit, 0, 0, 0 );
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if ( status == l_Undef )
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return 0;
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if ( status == l_False )
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{
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Vec_IntPush( &p->vObjTypes, 0 );
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Vec_IntPush( &p->vObjGates, c );
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Vec_WecPushLevel( &p->vObjFanins );
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return 1;
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}
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assert( status == l_True );
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// record this status
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for ( i = 0; i < p->iTarget; i++ )
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{
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Vec_IntPush( &p->vPols[c], sat_solver_var_value(p->pSat, i) );
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Vec_WrdPush( &p->vSets[c], 0 );
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}
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p->nPats[c]++;
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}
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// proceed checking divisors based on their values
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for ( c = 0; c < 2; c++ )
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{
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Lits[0] = Abc_Var2Lit( p->iTarget, c );
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for ( i = 0; i < p->iTarget; i++ )
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{
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if ( Vec_WrdEntry(&p->vSets[c], i) ) // diff value is possible
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continue;
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Lits[1] = Abc_Var2Lit( i, Vec_IntEntry(&p->vPols[c], i) );
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status = sat_solver_solve( p->pSat, Lits, Lits + 2, nBTLimit, 0, 0, 0 );
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if ( status == l_Undef )
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return 0;
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if ( status == l_False )
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{
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Vec_IntPush( &p->vImpls[c], i );
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continue;
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}
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assert( status == l_True );
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// record this status
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for ( i = 0; i < p->iTarget; i++ )
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if ( sat_solver_var_value(p->pSat, i) ^ Vec_IntEntry(&p->vPols[c], i) )
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*Vec_WrdEntryP(&p->vSets[c], i) |= ((word)1 << p->nPats[c]);
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p->nPats[c]++;
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}
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}
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// print the results
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if ( fVerbose )
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for ( c = 0; c < 2; c++ )
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{
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printf( "\nON-SET reference vertex:\n" );
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for ( i = 0; i < p->iTarget; i++ )
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printf( "%d", Vec_IntEntry(&p->vPols[c], i) );
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printf( "\n" );
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printf( " " );
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for ( i = 0; i < p->iTarget; i++ )
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printf( "%d", i % 10 );
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printf( "\n" );
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for ( k = 0; k < p->nPats[c]; k++ )
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{
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printf( "%2d : ", k );
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for ( i = 0; i < p->iTarget; i++ )
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printf( "%d", (int)((Vec_WrdEntry(&p->vSets[c], i) >> k) & 1) );
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printf( "\n" );
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}
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}
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p->timeSat += Abc_Clock() - clk;
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return 1;
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}
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/**Function*************************************************************
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Synopsis [Testbench for the new AIG minimization.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Abc_NtkDfsReverseOne_rec( Abc_Obj_t * pNode, Vec_Int_t * vNodes )
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{
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Abc_Obj_t * pFanout; int i;
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if ( Abc_NodeIsTravIdCurrent( pNode ) )
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return;
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Abc_NodeSetTravIdCurrent( pNode );
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if ( Abc_ObjIsCo(pNode) )
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{
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Vec_IntPush( vNodes, Abc_ObjId(pNode) );
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return;
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}
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assert( Abc_ObjIsNode( pNode ) );
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Abc_ObjForEachFanout( pNode, pFanout, i )
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Abc_NtkDfsReverseOne_rec( pFanout, vNodes );
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Vec_IntPush( vNodes, Abc_ObjId(pNode) );
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}
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void Abc_NtkDfsOne_rec( Abc_Obj_t * pNode, Vec_Int_t * vMap, Vec_Int_t * vTypes )
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{
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Abc_Obj_t * pFanin; int i;
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if ( Abc_NodeIsTravIdCurrent( pNode ) )
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return;
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Abc_NodeSetTravIdCurrent( pNode );
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if ( Abc_ObjIsCi(pNode) )
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{
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pNode->iTemp = Vec_IntSize(vMap);
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Vec_IntPush( vMap, Abc_ObjId(pNode) );
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Vec_IntPush( vTypes, 1 );
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return;
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}
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assert( Abc_ObjIsNode(pNode) );
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Abc_ObjForEachFanin( pNode, pFanin, i )
|
||||
Abc_NtkDfsOne_rec( pFanin, vMap, vTypes );
|
||||
pNode->iTemp = Vec_IntSize(vMap);
|
||||
Vec_IntPush( vMap, Abc_ObjId(pNode) );
|
||||
Vec_IntPush( vTypes, 0 );
|
||||
}
|
||||
int Sfm_DecExtract( Abc_Ntk_t * pNtk, int iNode, Vec_Int_t * vTypes, Vec_Int_t * vGates, Vec_Wec_t * vFanins, Vec_Int_t * vMap, Vec_Int_t * vTemp )
|
||||
{
|
||||
Abc_Obj_t * pNode = Abc_NtkObj( pNtk, iNode );
|
||||
Vec_Int_t * vLevel;
|
||||
int i, iObj, iTarget;
|
||||
assert( Abc_ObjIsNode(pNode) );
|
||||
// collect transitive fanout
|
||||
Vec_IntClear( vTemp );
|
||||
Abc_NtkIncrementTravId( pNtk );
|
||||
Abc_NtkDfsReverseOne_rec( pNode, vTemp );
|
||||
// collect transitive fanin
|
||||
Vec_IntClear( vMap );
|
||||
Vec_IntClear( vTypes );
|
||||
Abc_NtkDfsOne_rec( pNode, vMap, vTypes );
|
||||
Vec_IntPop( vMap );
|
||||
Vec_IntPop( vTypes );
|
||||
assert( Vec_IntSize(vMap) == Vec_IntSize(vTypes) );
|
||||
// remember target node
|
||||
iTarget = Vec_IntSize( vMap );
|
||||
// add transitive fanout
|
||||
Vec_IntForEachEntryReverse( vTemp, iObj, i )
|
||||
{
|
||||
pNode = Abc_NtkObj( pNtk, iObj );
|
||||
if ( Abc_ObjIsCo(pNode) )
|
||||
{
|
||||
assert( Vec_IntEntry(vTypes, Abc_ObjFanin0(pNode)->iTemp) == 0 );
|
||||
Vec_IntWriteEntry( vTypes, Abc_ObjFanin0(pNode)->iTemp, 2 );
|
||||
continue;
|
||||
}
|
||||
pNode->iTemp = Vec_IntSize(vMap);
|
||||
Vec_IntPush( vMap, Abc_ObjId(pNode) );
|
||||
Vec_IntPush( vTypes, 0 );
|
||||
}
|
||||
assert( Vec_IntSize(vMap) == Vec_IntSize(vTypes) );
|
||||
// create gates and fanins
|
||||
Vec_IntClear( vGates );
|
||||
Vec_WecClear( vFanins );
|
||||
Vec_IntForEachEntry( vMap, iObj, i )
|
||||
{
|
||||
vLevel = Vec_WecPushLevel( vFanins );
|
||||
pNode = Abc_NtkObj( pNtk, iObj );
|
||||
if ( Abc_ObjIsCi(pNode) )
|
||||
{
|
||||
Vec_IntPush( vGates, -1 );
|
||||
continue;
|
||||
}
|
||||
assert( Abc_ObjFaninNum(pNode) == 2 );
|
||||
if ( !Abc_ObjFaninC0(pNode) && !Abc_ObjFaninC1(pNode) )
|
||||
Vec_IntPush( vGates, 4 );
|
||||
else if ( !Abc_ObjFaninC0(pNode) && Abc_ObjFaninC1(pNode) )
|
||||
Vec_IntPush( vGates, 5 );
|
||||
else if ( Abc_ObjFaninC0(pNode) && !Abc_ObjFaninC1(pNode) )
|
||||
Vec_IntPush( vGates, 6 );
|
||||
else //if ( Abc_ObjFaninC0(pNode) && Abc_ObjFaninC1(pNode) )
|
||||
Vec_IntPush( vGates, 7 );
|
||||
Vec_IntPush( vLevel, Abc_ObjFanin0(pNode)->iTemp );
|
||||
Vec_IntPush( vLevel, Abc_ObjFanin1(pNode)->iTemp );
|
||||
}
|
||||
return iTarget;
|
||||
}
|
||||
void Sfm_DecInsert( Abc_Ntk_t * pNtk, int iNode, int Limit, Vec_Int_t * vTypes, Vec_Int_t * vGates, Vec_Wec_t * vFanins, Vec_Int_t * vMap )
|
||||
{
|
||||
Abc_Obj_t * pTarget = Abc_NtkObj( pNtk, iNode );
|
||||
Vec_Int_t * vLevel;
|
||||
Abc_Obj_t * pObjNew = NULL;
|
||||
int i, k, iObj, Gate;
|
||||
assert( Limit < Vec_IntSize(vTypes) );
|
||||
Vec_IntForEachEntryStart( vGates, Gate, i, Limit )
|
||||
{
|
||||
assert( Gate >= 0 && Gate <= 7 );
|
||||
vLevel = Vec_WecEntry( vFanins, i );
|
||||
if ( Gate == 0 )
|
||||
pObjNew = Abc_NtkCreateNodeConst0( pNtk );
|
||||
else if ( Gate == 1 )
|
||||
pObjNew = Abc_NtkCreateNodeConst1( pNtk );
|
||||
else if ( Gate == 2 )
|
||||
pObjNew = Abc_NtkCreateNodeBuf( pNtk, Abc_NtkObj(pNtk, Vec_IntEntry(vMap, Vec_IntEntry(vLevel,0))) );
|
||||
else if ( Gate == 3 )
|
||||
pObjNew = Abc_NtkCreateNodeInv( pNtk, Abc_NtkObj(pNtk, Vec_IntEntry(vMap, Vec_IntEntry(vLevel,0))) );
|
||||
else // if ( Gate >= 4 )
|
||||
{
|
||||
pObjNew = Abc_NtkCreateNode( pNtk );
|
||||
Vec_IntForEachEntry( vLevel, iObj, k )
|
||||
Abc_ObjAddFanin( pObjNew, Abc_NtkObj(pNtk, Vec_IntEntry(vMap, iObj)) );
|
||||
pObjNew->pData = NULL; // SELECTION FUNCTION
|
||||
}
|
||||
// transfer the fanout
|
||||
Abc_ObjTransferFanout( pTarget, pObjNew );
|
||||
assert( Abc_ObjFanoutNum(pTarget) == 0 );
|
||||
Abc_NtkDeleteObj_rec( pTarget, 1 );
|
||||
}
|
||||
}
|
||||
void Sfm_DecTestBench( Abc_Ntk_t * pNtk )
|
||||
{
|
||||
Vec_Int_t * vMap, * vTemp;
|
||||
Abc_Obj_t * pObj; int i, Limit;
|
||||
Sfm_Dec_t * p = Sfm_DecStart();
|
||||
Sfm_DecCreateAigLibrary( p );
|
||||
assert( Abc_NtkIsSopLogic(pNtk) );
|
||||
assert( Abc_NtkGetFaninMax(pNtk) <= 2 );
|
||||
vMap = Vec_IntAlloc( Abc_NtkObjNumMax(pNtk) ); // Sfm->Ntk
|
||||
vTemp = Vec_IntAlloc( Abc_NtkObjNumMax(pNtk) );
|
||||
Abc_NtkForEachNode( pNtk, pObj, i )
|
||||
{
|
||||
p->iTarget = Sfm_DecExtract( pNtk, i, &p->vObjTypes, &p->vObjGates, &p->vObjFanins, vMap, vTemp );
|
||||
Limit = Vec_IntSize( &p->vObjTypes );
|
||||
if ( !Sfm_DecPrepareSolver( p ) )
|
||||
continue;
|
||||
if ( !Sfm_DecPeformDec( p ) )
|
||||
continue;
|
||||
Sfm_DecInsert( pNtk, p->iTarget, Limit, &p->vObjTypes, &p->vObjGates, &p->vObjFanins, vMap );
|
||||
}
|
||||
Vec_IntFree( vMap );
|
||||
Vec_IntFree( vTemp );
|
||||
Sfm_DecStop( p );
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// END OF FILE ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
ABC_NAMESPACE_IMPL_END
|
||||
|
||||
Loading…
Reference in New Issue