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abc
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Version abc60211

This commit is contained in:
Alan Mishchenko 2006-02-11 08:01:00 -08:00
parent c0ef1f469a
commit 77d7377442
72 changed files with 4426 additions and 2150 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Makefile
View File

@ -10,7 +10,7 @@ MODULES := src/base/abc src/base/abci src/base/seq src/base/cmd src/base/io src/
src/bdd/cudd src/bdd/dsd src/bdd/epd src/bdd/mtr src/bdd/parse src/bdd/reo \
src/map/fpga src/map/pga src/map/mapper src/map/mio src/map/super \
src/misc/extra src/misc/mvc src/misc/st src/misc/util src/misc/vec \
src/opt/cut src/opt/dec src/opt/fxu src/opt/rwr src/opt/sim src/opt/xyz \
src/opt/cut src/opt/dec src/opt/fxu src/opt/rwr src/opt/sim \
src/sat/asat src/sat/csat src/sat/msat src/sat/fraig
default: $(PROG)

24
abc.dsp
View File

@ -174,6 +174,10 @@ SOURCE=.\src\base\abci\abcAttach.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcAuto.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcBalance.c
# End Source File
# Begin Source File
@ -210,10 +214,6 @@ SOURCE=.\src\base\abci\abcMiter.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcNewAig.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcNtbdd.c
# End Source File
# Begin Source File
@ -262,6 +262,10 @@ SOURCE=.\src\base\abci\abcTiming.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcUnate.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcUnreach.c
# End Source File
# Begin Source File
@ -1128,6 +1132,10 @@ SOURCE=.\src\sat\aig\fraigSolver.c
SOURCE=.\src\sat\aig\fraigTrav.c
# End Source File
# Begin Source File
SOURCE=.\src\sat\aig\rwrTruth.c
# End Source File
# End Group
# End Group
# Begin Group "opt"
@ -1650,6 +1658,10 @@ SOURCE=.\src\misc\extra\extra.h
# End Source File
# Begin Source File
SOURCE=.\src\misc\extra\extraBddAuto.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\extra\extraBddKmap.c
# End Source File
# Begin Source File
@ -1662,6 +1674,10 @@ SOURCE=.\src\misc\extra\extraBddSymm.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\extra\extraBddUnate.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\extra\extraUtilBitMatrix.c
# End Source File
# Begin Source File

BIN
abc.opt
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Binary file not shown.

723
abc.plg
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@ -1,723 +0,0 @@
<html>
<body>
<pre>
<h1>Build Log</h1>
<h3>
--------------------Configuration: abc - Win32 Debug--------------------
</h3>
<h3>Command Lines</h3>
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP8E2.tmp" with contents
[
/nologo /MLd /W3 /Gm /GX /ZI /Od /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\aig" /I "src\sat\asat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D "HAVE_ASSERT_H" /FR"Debug/" /Fp"Debug/abc.pch" /YX /Fo"Debug/" /Fd"Debug/" /FD /GZ /c
"C:\_projects\abc\src\sat\aig\fraigSim.c"
]
Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP8E2.tmp"
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP8E3.tmp" with contents
[
kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /incremental:yes /pdb:"Debug/abc.pdb" /debug /machine:I386 /out:"_TEST/abc.exe" /pdbtype:sept
.\Debug\abcAig.obj
.\Debug\abcCheck.obj
.\Debug\abcDfs.obj
.\Debug\abcFanio.obj
.\Debug\abcFunc.obj
.\Debug\abcLatch.obj
.\Debug\abcMinBase.obj
.\Debug\abcNames.obj
.\Debug\abcNetlist.obj
.\Debug\abcNtk.obj
.\Debug\abcObj.obj
.\Debug\abcRefs.obj
.\Debug\abcShow.obj
.\Debug\abcSop.obj
.\Debug\abcUtil.obj
.\Debug\abc.obj
.\Debug\abcAttach.obj
.\Debug\abcBalance.obj
.\Debug\abcCollapse.obj
.\Debug\abcCut.obj
.\Debug\abcDsd.obj
.\Debug\abcFpga.obj
.\Debug\abcFraig.obj
.\Debug\abcFxu.obj
.\Debug\abcMap.obj
.\Debug\abcMiter.obj
.\Debug\abcNtbdd.obj
.\Debug\abcPga.obj
.\Debug\abcPrint.obj
.\Debug\abcReconv.obj
.\Debug\abcRefactor.obj
.\Debug\abcRenode.obj
.\Debug\abcRewrite.obj
.\Debug\abcSat.obj
.\Debug\abcStrash.obj
.\Debug\abcSweep.obj
.\Debug\abcSymm.obj
.\Debug\abcTiming.obj
.\Debug\abcUnreach.obj
.\Debug\abcVanEijk.obj
.\Debug\abcVanImp.obj
.\Debug\abcVerify.obj
.\Debug\seqAigCore.obj
.\Debug\seqAigIter.obj
.\Debug\seqCreate.obj
.\Debug\seqFpgaCore.obj
.\Debug\seqFpgaIter.obj
.\Debug\seqLatch.obj
.\Debug\seqMan.obj
.\Debug\seqMapCore.obj
.\Debug\seqMapIter.obj
.\Debug\seqRetCore.obj
.\Debug\seqRetIter.obj
.\Debug\seqShare.obj
.\Debug\seqUtil.obj
.\Debug\cmd.obj
.\Debug\cmdAlias.obj
.\Debug\cmdApi.obj
.\Debug\cmdFlag.obj
.\Debug\cmdHist.obj
.\Debug\cmdUtils.obj
.\Debug\io.obj
.\Debug\ioRead.obj
.\Debug\ioReadBaf.obj
.\Debug\ioReadBench.obj
.\Debug\ioReadBlif.obj
.\Debug\ioReadEdif.obj
.\Debug\ioReadEqn.obj
.\Debug\ioReadPla.obj
.\Debug\ioReadVerilog.obj
.\Debug\ioUtil.obj
.\Debug\ioWriteBaf.obj
.\Debug\ioWriteBench.obj
.\Debug\ioWriteBlif.obj
.\Debug\ioWriteCnf.obj
.\Debug\ioWriteDot.obj
.\Debug\ioWriteEqn.obj
.\Debug\ioWriteGml.obj
.\Debug\ioWriteList.obj
.\Debug\ioWritePla.obj
.\Debug\ioWriteVerilog.obj
.\Debug\libSupport.obj
.\Debug\main.obj
.\Debug\mainFrame.obj
.\Debug\mainInit.obj
.\Debug\mainUtils.obj
.\Debug\cuddAddAbs.obj
.\Debug\cuddAddApply.obj
.\Debug\cuddAddFind.obj
.\Debug\cuddAddInv.obj
.\Debug\cuddAddIte.obj
.\Debug\cuddAddNeg.obj
.\Debug\cuddAddWalsh.obj
.\Debug\cuddAndAbs.obj
.\Debug\cuddAnneal.obj
.\Debug\cuddApa.obj
.\Debug\cuddAPI.obj
.\Debug\cuddApprox.obj
.\Debug\cuddBddAbs.obj
.\Debug\cuddBddCorr.obj
.\Debug\cuddBddIte.obj
.\Debug\cuddBridge.obj
.\Debug\cuddCache.obj
.\Debug\cuddCheck.obj
.\Debug\cuddClip.obj
.\Debug\cuddCof.obj
.\Debug\cuddCompose.obj
.\Debug\cuddDecomp.obj
.\Debug\cuddEssent.obj
.\Debug\cuddExact.obj
.\Debug\cuddExport.obj
.\Debug\cuddGenCof.obj
.\Debug\cuddGenetic.obj
.\Debug\cuddGroup.obj
.\Debug\cuddHarwell.obj
.\Debug\cuddInit.obj
.\Debug\cuddInteract.obj
.\Debug\cuddLCache.obj
.\Debug\cuddLevelQ.obj
.\Debug\cuddLinear.obj
.\Debug\cuddLiteral.obj
.\Debug\cuddMatMult.obj
.\Debug\cuddPriority.obj
.\Debug\cuddRead.obj
.\Debug\cuddRef.obj
.\Debug\cuddReorder.obj
.\Debug\cuddSat.obj
.\Debug\cuddSign.obj
.\Debug\cuddSolve.obj
.\Debug\cuddSplit.obj
.\Debug\cuddSubsetHB.obj
.\Debug\cuddSubsetSP.obj
.\Debug\cuddSymmetry.obj
.\Debug\cuddTable.obj
.\Debug\cuddUtil.obj
.\Debug\cuddWindow.obj
.\Debug\cuddZddCount.obj
.\Debug\cuddZddFuncs.obj
.\Debug\cuddZddGroup.obj
.\Debug\cuddZddIsop.obj
.\Debug\cuddZddLin.obj
.\Debug\cuddZddMisc.obj
.\Debug\cuddZddPort.obj
.\Debug\cuddZddReord.obj
.\Debug\cuddZddSetop.obj
.\Debug\cuddZddSymm.obj
.\Debug\cuddZddUtil.obj
.\Debug\epd.obj
.\Debug\mtrBasic.obj
.\Debug\mtrGroup.obj
.\Debug\parseCore.obj
.\Debug\parseStack.obj
.\Debug\dsdApi.obj
.\Debug\dsdCheck.obj
.\Debug\dsdLocal.obj
.\Debug\dsdMan.obj
.\Debug\dsdProc.obj
.\Debug\dsdTree.obj
.\Debug\reoApi.obj
.\Debug\reoCore.obj
.\Debug\reoProfile.obj
.\Debug\reoSift.obj
.\Debug\reoSwap.obj
.\Debug\reoTest.obj
.\Debug\reoTransfer.obj
.\Debug\reoUnits.obj
.\Debug\added.obj
.\Debug\solver.obj
.\Debug\msatActivity.obj
.\Debug\msatClause.obj
.\Debug\msatClauseVec.obj
.\Debug\msatMem.obj
.\Debug\msatOrderJ.obj
.\Debug\msatQueue.obj
.\Debug\msatRead.obj
.\Debug\msatSolverApi.obj
.\Debug\msatSolverCore.obj
.\Debug\msatSolverIo.obj
.\Debug\msatSolverSearch.obj
.\Debug\msatSort.obj
.\Debug\msatVec.obj
.\Debug\fraigApi.obj
.\Debug\fraigCanon.obj
.\Debug\fraigFanout.obj
.\Debug\fraigFeed.obj
.\Debug\fraigMan.obj
.\Debug\fraigMem.obj
.\Debug\fraigNode.obj
.\Debug\fraigPrime.obj
.\Debug\fraigSat.obj
.\Debug\fraigTable.obj
.\Debug\fraigUtil.obj
.\Debug\fraigVec.obj
.\Debug\csat_apis.obj
.\Debug\aigBalance.obj
.\Debug\aigCheck.obj
.\Debug\aigFanout.obj
.\Debug\aigMan.obj
.\Debug\aigMem.obj
.\Debug\aigNode.obj
.\Debug\aigOper.obj
.\Debug\aigReplace.obj
.\Debug\aigTable.obj
.\Debug\aigUtil.obj
.\Debug\fraigClass.obj
.\Debug\fraigCore.obj
.\Debug\fraigProve.obj
.\Debug\fraigSim.obj
.\Debug\fraigSolver.obj
.\Debug\fraigTrav.obj
.\Debug\fxu.obj
.\Debug\fxuCreate.obj
.\Debug\fxuHeapD.obj
.\Debug\fxuHeapS.obj
.\Debug\fxuList.obj
.\Debug\fxuMatrix.obj
.\Debug\fxuPair.obj
.\Debug\fxuPrint.obj
.\Debug\fxuReduce.obj
.\Debug\fxuSelect.obj
.\Debug\fxuSingle.obj
.\Debug\fxuUpdate.obj
.\Debug\rwrDec.obj
.\Debug\rwrEva.obj
.\Debug\rwrExp.obj
.\Debug\rwrLib.obj
.\Debug\rwrMan.obj
.\Debug\rwrPrint.obj
.\Debug\rwrUtil.obj
.\Debug\cutApi.obj
.\Debug\cutCut.obj
.\Debug\cutMan.obj
.\Debug\cutMerge.obj
.\Debug\cutNode.obj
.\Debug\cutOracle.obj
.\Debug\cutSeq.obj
.\Debug\cutTruth.obj
.\Debug\decAbc.obj
.\Debug\decFactor.obj
.\Debug\decMan.obj
.\Debug\decPrint.obj
.\Debug\decUtil.obj
.\Debug\simMan.obj
.\Debug\simSat.obj
.\Debug\simSeq.obj
.\Debug\simSupp.obj
.\Debug\simSwitch.obj
.\Debug\simSym.obj
.\Debug\simSymSat.obj
.\Debug\simSymSim.obj
.\Debug\simSymStr.obj
.\Debug\simUtils.obj
.\Debug\xyzBuild.obj
.\Debug\xyzCore.obj
.\Debug\xyzMan.obj
.\Debug\xyzMinEsop.obj
.\Debug\xyzMinMan.obj
.\Debug\xyzMinSop.obj
.\Debug\xyzMinUtil.obj
.\Debug\xyzTest.obj
.\Debug\fpga.obj
.\Debug\fpgaCore.obj
.\Debug\fpgaCreate.obj
.\Debug\fpgaCut.obj
.\Debug\fpgaCutUtils.obj
.\Debug\fpgaFanout.obj
.\Debug\fpgaLib.obj
.\Debug\fpgaMatch.obj
.\Debug\fpgaSwitch.obj
.\Debug\fpgaTime.obj
.\Debug\fpgaTruth.obj
.\Debug\fpgaUtils.obj
.\Debug\fpgaVec.obj
.\Debug\mapper.obj
.\Debug\mapperCanon.obj
.\Debug\mapperCore.obj
.\Debug\mapperCreate.obj
.\Debug\mapperCut.obj
.\Debug\mapperCutUtils.obj
.\Debug\mapperFanout.obj
.\Debug\mapperLib.obj
.\Debug\mapperMatch.obj
.\Debug\mapperRefs.obj
.\Debug\mapperSuper.obj
.\Debug\mapperSwitch.obj
.\Debug\mapperTable.obj
.\Debug\mapperTime.obj
.\Debug\mapperTree.obj
.\Debug\mapperTruth.obj
.\Debug\mapperUtils.obj
.\Debug\mapperVec.obj
.\Debug\mio.obj
.\Debug\mioApi.obj
.\Debug\mioFunc.obj
.\Debug\mioRead.obj
.\Debug\mioUtils.obj
.\Debug\super.obj
.\Debug\superAnd.obj
.\Debug\superGate.obj
.\Debug\superWrite.obj
.\Debug\pgaCore.obj
.\Debug\pgaMan.obj
.\Debug\pgaMatch.obj
.\Debug\pgaUtil.obj
.\Debug\extraBddKmap.obj
.\Debug\extraBddMisc.obj
.\Debug\extraBddSymm.obj
.\Debug\extraUtilBitMatrix.obj
.\Debug\extraUtilCanon.obj
.\Debug\extraUtilFile.obj
.\Debug\extraUtilMemory.obj
.\Debug\extraUtilMisc.obj
.\Debug\extraUtilProgress.obj
.\Debug\extraUtilReader.obj
.\Debug\st.obj
.\Debug\stmm.obj
.\Debug\cpu_stats.obj
.\Debug\cpu_time.obj
.\Debug\datalimit.obj
.\Debug\getopt.obj
.\Debug\pathsearch.obj
.\Debug\safe_mem.obj
.\Debug\strsav.obj
.\Debug\texpand.obj
.\Debug\mvc.obj
.\Debug\mvcApi.obj
.\Debug\mvcCompare.obj
.\Debug\mvcContain.obj
.\Debug\mvcCover.obj
.\Debug\mvcCube.obj
.\Debug\mvcDivide.obj
.\Debug\mvcDivisor.obj
.\Debug\mvcList.obj
.\Debug\mvcLits.obj
.\Debug\mvcMan.obj
.\Debug\mvcOpAlg.obj
.\Debug\mvcOpBool.obj
.\Debug\mvcPrint.obj
.\Debug\mvcSort.obj
.\Debug\mvcUtils.obj
.\Debug\abcNewAig.obj
.\Debug\fraigCnf.obj
.\Debug\fraigEngine.obj
]
Creating command line "link.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP8E3.tmp"
<h3>Output Window</h3>
Compiling...
fraigSim.c
Linking...
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP8E4.tmp" with contents
[
/nologo /o"Debug/abc.bsc"
.\Debug\abcAig.sbr
.\Debug\abcCheck.sbr
.\Debug\abcDfs.sbr
.\Debug\abcFanio.sbr
.\Debug\abcFunc.sbr
.\Debug\abcLatch.sbr
.\Debug\abcMinBase.sbr
.\Debug\abcNames.sbr
.\Debug\abcNetlist.sbr
.\Debug\abcNtk.sbr
.\Debug\abcObj.sbr
.\Debug\abcRefs.sbr
.\Debug\abcShow.sbr
.\Debug\abcSop.sbr
.\Debug\abcUtil.sbr
.\Debug\abc.sbr
.\Debug\abcAttach.sbr
.\Debug\abcBalance.sbr
.\Debug\abcCollapse.sbr
.\Debug\abcCut.sbr
.\Debug\abcDsd.sbr
.\Debug\abcFpga.sbr
.\Debug\abcFraig.sbr
.\Debug\abcFxu.sbr
.\Debug\abcMap.sbr
.\Debug\abcMiter.sbr
.\Debug\abcNtbdd.sbr
.\Debug\abcPga.sbr
.\Debug\abcPrint.sbr
.\Debug\abcReconv.sbr
.\Debug\abcRefactor.sbr
.\Debug\abcRenode.sbr
.\Debug\abcRewrite.sbr
.\Debug\abcSat.sbr
.\Debug\abcStrash.sbr
.\Debug\abcSweep.sbr
.\Debug\abcSymm.sbr
.\Debug\abcTiming.sbr
.\Debug\abcUnreach.sbr
.\Debug\abcVanEijk.sbr
.\Debug\abcVanImp.sbr
.\Debug\abcVerify.sbr
.\Debug\seqAigCore.sbr
.\Debug\seqAigIter.sbr
.\Debug\seqCreate.sbr
.\Debug\seqFpgaCore.sbr
.\Debug\seqFpgaIter.sbr
.\Debug\seqLatch.sbr
.\Debug\seqMan.sbr
.\Debug\seqMapCore.sbr
.\Debug\seqMapIter.sbr
.\Debug\seqRetCore.sbr
.\Debug\seqRetIter.sbr
.\Debug\seqShare.sbr
.\Debug\seqUtil.sbr
.\Debug\cmd.sbr
.\Debug\cmdAlias.sbr
.\Debug\cmdApi.sbr
.\Debug\cmdFlag.sbr
.\Debug\cmdHist.sbr
.\Debug\cmdUtils.sbr
.\Debug\io.sbr
.\Debug\ioRead.sbr
.\Debug\ioReadBaf.sbr
.\Debug\ioReadBench.sbr
.\Debug\ioReadBlif.sbr
.\Debug\ioReadEdif.sbr
.\Debug\ioReadEqn.sbr
.\Debug\ioReadPla.sbr
.\Debug\ioReadVerilog.sbr
.\Debug\ioUtil.sbr
.\Debug\ioWriteBaf.sbr
.\Debug\ioWriteBench.sbr
.\Debug\ioWriteBlif.sbr
.\Debug\ioWriteCnf.sbr
.\Debug\ioWriteDot.sbr
.\Debug\ioWriteEqn.sbr
.\Debug\ioWriteGml.sbr
.\Debug\ioWriteList.sbr
.\Debug\ioWritePla.sbr
.\Debug\ioWriteVerilog.sbr
.\Debug\libSupport.sbr
.\Debug\main.sbr
.\Debug\mainFrame.sbr
.\Debug\mainInit.sbr
.\Debug\mainUtils.sbr
.\Debug\cuddAddAbs.sbr
.\Debug\cuddAddApply.sbr
.\Debug\cuddAddFind.sbr
.\Debug\cuddAddInv.sbr
.\Debug\cuddAddIte.sbr
.\Debug\cuddAddNeg.sbr
.\Debug\cuddAddWalsh.sbr
.\Debug\cuddAndAbs.sbr
.\Debug\cuddAnneal.sbr
.\Debug\cuddApa.sbr
.\Debug\cuddAPI.sbr
.\Debug\cuddApprox.sbr
.\Debug\cuddBddAbs.sbr
.\Debug\cuddBddCorr.sbr
.\Debug\cuddBddIte.sbr
.\Debug\cuddBridge.sbr
.\Debug\cuddCache.sbr
.\Debug\cuddCheck.sbr
.\Debug\cuddClip.sbr
.\Debug\cuddCof.sbr
.\Debug\cuddCompose.sbr
.\Debug\cuddDecomp.sbr
.\Debug\cuddEssent.sbr
.\Debug\cuddExact.sbr
.\Debug\cuddExport.sbr
.\Debug\cuddGenCof.sbr
.\Debug\cuddGenetic.sbr
.\Debug\cuddGroup.sbr
.\Debug\cuddHarwell.sbr
.\Debug\cuddInit.sbr
.\Debug\cuddInteract.sbr
.\Debug\cuddLCache.sbr
.\Debug\cuddLevelQ.sbr
.\Debug\cuddLinear.sbr
.\Debug\cuddLiteral.sbr
.\Debug\cuddMatMult.sbr
.\Debug\cuddPriority.sbr
.\Debug\cuddRead.sbr
.\Debug\cuddRef.sbr
.\Debug\cuddReorder.sbr
.\Debug\cuddSat.sbr
.\Debug\cuddSign.sbr
.\Debug\cuddSolve.sbr
.\Debug\cuddSplit.sbr
.\Debug\cuddSubsetHB.sbr
.\Debug\cuddSubsetSP.sbr
.\Debug\cuddSymmetry.sbr
.\Debug\cuddTable.sbr
.\Debug\cuddUtil.sbr
.\Debug\cuddWindow.sbr
.\Debug\cuddZddCount.sbr
.\Debug\cuddZddFuncs.sbr
.\Debug\cuddZddGroup.sbr
.\Debug\cuddZddIsop.sbr
.\Debug\cuddZddLin.sbr
.\Debug\cuddZddMisc.sbr
.\Debug\cuddZddPort.sbr
.\Debug\cuddZddReord.sbr
.\Debug\cuddZddSetop.sbr
.\Debug\cuddZddSymm.sbr
.\Debug\cuddZddUtil.sbr
.\Debug\epd.sbr
.\Debug\mtrBasic.sbr
.\Debug\mtrGroup.sbr
.\Debug\parseCore.sbr
.\Debug\parseStack.sbr
.\Debug\dsdApi.sbr
.\Debug\dsdCheck.sbr
.\Debug\dsdLocal.sbr
.\Debug\dsdMan.sbr
.\Debug\dsdProc.sbr
.\Debug\dsdTree.sbr
.\Debug\reoApi.sbr
.\Debug\reoCore.sbr
.\Debug\reoProfile.sbr
.\Debug\reoSift.sbr
.\Debug\reoSwap.sbr
.\Debug\reoTest.sbr
.\Debug\reoTransfer.sbr
.\Debug\reoUnits.sbr
.\Debug\added.sbr
.\Debug\solver.sbr
.\Debug\msatActivity.sbr
.\Debug\msatClause.sbr
.\Debug\msatClauseVec.sbr
.\Debug\msatMem.sbr
.\Debug\msatOrderJ.sbr
.\Debug\msatQueue.sbr
.\Debug\msatRead.sbr
.\Debug\msatSolverApi.sbr
.\Debug\msatSolverCore.sbr
.\Debug\msatSolverIo.sbr
.\Debug\msatSolverSearch.sbr
.\Debug\msatSort.sbr
.\Debug\msatVec.sbr
.\Debug\fraigApi.sbr
.\Debug\fraigCanon.sbr
.\Debug\fraigFanout.sbr
.\Debug\fraigFeed.sbr
.\Debug\fraigMan.sbr
.\Debug\fraigMem.sbr
.\Debug\fraigNode.sbr
.\Debug\fraigPrime.sbr
.\Debug\fraigSat.sbr
.\Debug\fraigTable.sbr
.\Debug\fraigUtil.sbr
.\Debug\fraigVec.sbr
.\Debug\csat_apis.sbr
.\Debug\aigBalance.sbr
.\Debug\aigCheck.sbr
.\Debug\aigFanout.sbr
.\Debug\aigMan.sbr
.\Debug\aigMem.sbr
.\Debug\aigNode.sbr
.\Debug\aigOper.sbr
.\Debug\aigReplace.sbr
.\Debug\aigTable.sbr
.\Debug\aigUtil.sbr
.\Debug\fraigClass.sbr
.\Debug\fraigCore.sbr
.\Debug\fraigProve.sbr
.\Debug\fraigSim.sbr
.\Debug\fraigSolver.sbr
.\Debug\fraigTrav.sbr
.\Debug\fxu.sbr
.\Debug\fxuCreate.sbr
.\Debug\fxuHeapD.sbr
.\Debug\fxuHeapS.sbr
.\Debug\fxuList.sbr
.\Debug\fxuMatrix.sbr
.\Debug\fxuPair.sbr
.\Debug\fxuPrint.sbr
.\Debug\fxuReduce.sbr
.\Debug\fxuSelect.sbr
.\Debug\fxuSingle.sbr
.\Debug\fxuUpdate.sbr
.\Debug\rwrDec.sbr
.\Debug\rwrEva.sbr
.\Debug\rwrExp.sbr
.\Debug\rwrLib.sbr
.\Debug\rwrMan.sbr
.\Debug\rwrPrint.sbr
.\Debug\rwrUtil.sbr
.\Debug\cutApi.sbr
.\Debug\cutCut.sbr
.\Debug\cutMan.sbr
.\Debug\cutMerge.sbr
.\Debug\cutNode.sbr
.\Debug\cutOracle.sbr
.\Debug\cutSeq.sbr
.\Debug\cutTruth.sbr
.\Debug\decAbc.sbr
.\Debug\decFactor.sbr
.\Debug\decMan.sbr
.\Debug\decPrint.sbr
.\Debug\decUtil.sbr
.\Debug\simMan.sbr
.\Debug\simSat.sbr
.\Debug\simSeq.sbr
.\Debug\simSupp.sbr
.\Debug\simSwitch.sbr
.\Debug\simSym.sbr
.\Debug\simSymSat.sbr
.\Debug\simSymSim.sbr
.\Debug\simSymStr.sbr
.\Debug\simUtils.sbr
.\Debug\xyzBuild.sbr
.\Debug\xyzCore.sbr
.\Debug\xyzMan.sbr
.\Debug\xyzMinEsop.sbr
.\Debug\xyzMinMan.sbr
.\Debug\xyzMinSop.sbr
.\Debug\xyzMinUtil.sbr
.\Debug\xyzTest.sbr
.\Debug\fpga.sbr
.\Debug\fpgaCore.sbr
.\Debug\fpgaCreate.sbr
.\Debug\fpgaCut.sbr
.\Debug\fpgaCutUtils.sbr
.\Debug\fpgaFanout.sbr
.\Debug\fpgaLib.sbr
.\Debug\fpgaMatch.sbr
.\Debug\fpgaSwitch.sbr
.\Debug\fpgaTime.sbr
.\Debug\fpgaTruth.sbr
.\Debug\fpgaUtils.sbr
.\Debug\fpgaVec.sbr
.\Debug\mapper.sbr
.\Debug\mapperCanon.sbr
.\Debug\mapperCore.sbr
.\Debug\mapperCreate.sbr
.\Debug\mapperCut.sbr
.\Debug\mapperCutUtils.sbr
.\Debug\mapperFanout.sbr
.\Debug\mapperLib.sbr
.\Debug\mapperMatch.sbr
.\Debug\mapperRefs.sbr
.\Debug\mapperSuper.sbr
.\Debug\mapperSwitch.sbr
.\Debug\mapperTable.sbr
.\Debug\mapperTime.sbr
.\Debug\mapperTree.sbr
.\Debug\mapperTruth.sbr
.\Debug\mapperUtils.sbr
.\Debug\mapperVec.sbr
.\Debug\mio.sbr
.\Debug\mioApi.sbr
.\Debug\mioFunc.sbr
.\Debug\mioRead.sbr
.\Debug\mioUtils.sbr
.\Debug\super.sbr
.\Debug\superAnd.sbr
.\Debug\superGate.sbr
.\Debug\superWrite.sbr
.\Debug\pgaCore.sbr
.\Debug\pgaMan.sbr
.\Debug\pgaMatch.sbr
.\Debug\pgaUtil.sbr
.\Debug\extraBddKmap.sbr
.\Debug\extraBddMisc.sbr
.\Debug\extraBddSymm.sbr
.\Debug\extraUtilBitMatrix.sbr
.\Debug\extraUtilCanon.sbr
.\Debug\extraUtilFile.sbr
.\Debug\extraUtilMemory.sbr
.\Debug\extraUtilMisc.sbr
.\Debug\extraUtilProgress.sbr
.\Debug\extraUtilReader.sbr
.\Debug\st.sbr
.\Debug\stmm.sbr
.\Debug\cpu_stats.sbr
.\Debug\cpu_time.sbr
.\Debug\datalimit.sbr
.\Debug\getopt.sbr
.\Debug\pathsearch.sbr
.\Debug\safe_mem.sbr
.\Debug\strsav.sbr
.\Debug\texpand.sbr
.\Debug\mvc.sbr
.\Debug\mvcApi.sbr
.\Debug\mvcCompare.sbr
.\Debug\mvcContain.sbr
.\Debug\mvcCover.sbr
.\Debug\mvcCube.sbr
.\Debug\mvcDivide.sbr
.\Debug\mvcDivisor.sbr
.\Debug\mvcList.sbr
.\Debug\mvcLits.sbr
.\Debug\mvcMan.sbr
.\Debug\mvcOpAlg.sbr
.\Debug\mvcOpBool.sbr
.\Debug\mvcPrint.sbr
.\Debug\mvcSort.sbr
.\Debug\mvcUtils.sbr
.\Debug\abcNewAig.sbr
.\Debug\fraigCnf.sbr
.\Debug\fraigEngine.sbr]
Creating command line "bscmake.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP8E4.tmp"
Creating browse info file...
<h3>Output Window</h3>
<h3>Results</h3>
abc.exe - 0 error(s), 0 warning(s)
</pre>
</body>
</html>

78
abc.rc
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@ -1,78 +0,0 @@
# global parameters
#set check # checks intermediate networks
#set checkfio # prints warnings when fanins/fanouts are duplicated
set checkread # checks new networks after reading from file
set backup # saves backup networks retrived by "undo" and "recall"
set savesteps 1 # sets the maximum number of backup networks to save
# program names for internal calls
set dotwin dot.exe
set dotunix dot
set gsviewwin gsview32.exe
set gsviewunix gv
set siswin sis.exe
set sisunix sis
set mvsiswin mvsis.exe
set mvsisunix mvsis
# standard aliases
alias b balance
alias cl cleanup
alias clp collapse
alias esd ext_seq_dcs
alias f fraig
alias fs fraig_sweep
alias fsto fraig_store
alias fres fraig_restore
alias ft fraig_trust
alias mu renode -m
alias pex print_exdc -d
alias pf print_factor
alias pfan print_fanio
alias pl print_level
alias pio print_io
alias pk print_kmap
alias ps print_stats
alias psu print_supp
alias psy print_symm
alias q quit
alias r read
alias ren renode
alias rl read_blif
alias rb read_bench
alias ret retime
alias rp read_pla
alias rv read_verilog
alias rsup read_super mcnc5_old.super
alias rlib read_library
alias rw rewrite
alias rwz rewrite -z
alias rf refactor
alias rfz refactor -z
alias sa set autoexec ps
alias so source -x
alias st strash
alias sw sweep
alias ssw ssweep
alias scl scleanup
alias u undo
alias wb write_blif
alias wl write_blif
alias wp write_pla
alias wv write_verilog
# standard scripts
alias cnf "st; ren -c; write_cnf"
alias prove "st; ren -c; sat"
alias opt "b; ren; b"
alias share "b; ren; fx; b"
alias sharem "b; ren -m; fx; b"
alias sharedsd "b; ren; dsd -g; sw; fx; b"
alias resyn "b; rw; rwz; b; rwz; b"
alias resyn2 "b; rw; rf; b; rw; rwz; b; rfz; rwz; b"
alias compress "b; rw -l; rwz -l; b; rwz -l; b"
alias compress2 "b; rw -l; rf -l; b; rw -l; rwz -l; b; rfz -l; rwz -l; b"
alias choice "fraig_store; resyn; fraig_store; resyn2; fraig_store; fraig_restore"
alias choice2 "fraig_store; balance; fraig_store; resyn; fraig_store; resyn2; fraig_store; resyn2; fraig_store; fraig_restore"
alias try "st; fpga; miter; fraig -rp"

BIN
abclib.opt
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958
abclib.plg
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@ -1,958 +0,0 @@
<html>
<body>
<pre>
<h1>Build Log</h1>
<h3>
--------------------Configuration: abclib - Win32 Debug--------------------
</h3>
<h3>Command Lines</h3>
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP513.tmp" with contents
[
/nologo /MLd /W3 /Gm /GX /ZI /Od /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mapp" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /D "WIN32" /D "_DEBUG" /D "_MBCS" /D "_LIB" /D "__STDC__" /D "HAVE_ASSERT_H" /FR"abclib\DebugLib/" /Fp"abclib\DebugLib/abclib.pch" /YX /Fo"abclib\DebugLib/" /Fd"abclib\DebugLib/" /FD /GZ /c
"C:\_projects\abc\src\base\abc\abcAig.c"
"C:\_projects\abc\src\base\abc\abcCheck.c"
"C:\_projects\abc\src\base\abc\abcDfs.c"
"C:\_projects\abc\src\base\abc\abcFanio.c"
"C:\_projects\abc\src\base\abc\abcFunc.c"
"C:\_projects\abc\src\base\abc\abcLatch.c"
"C:\_projects\abc\src\base\abc\abcMinBase.c"
"C:\_projects\abc\src\base\abc\abcNames.c"
"C:\_projects\abc\src\base\abc\abcNetlist.c"
"C:\_projects\abc\src\base\abc\abcNtk.c"
"C:\_projects\abc\src\base\abc\abcObj.c"
"C:\_projects\abc\src\base\abc\abcRefs.c"
"C:\_projects\abc\src\base\abc\abcShow.c"
"C:\_projects\abc\src\base\abc\abcSop.c"
"C:\_projects\abc\src\base\abc\abcUtil.c"
"C:\_projects\abc\src\base\abci\abc.c"
"C:\_projects\abc\src\base\abci\abcAttach.c"
"C:\_projects\abc\src\base\abci\abcBalance.c"
"C:\_projects\abc\src\base\abci\abcCollapse.c"
"C:\_projects\abc\src\base\abci\abcCut.c"
"C:\_projects\abc\src\base\abci\abcDsd.c"
"C:\_projects\abc\src\base\abci\abcFpga.c"
"C:\_projects\abc\src\base\abci\abcFraig.c"
"C:\_projects\abc\src\base\abci\abcFxu.c"
"C:\_projects\abc\src\base\abci\abcMap.c"
"C:\_projects\abc\src\base\abci\abcMiter.c"
"C:\_projects\abc\src\base\abci\abcNtbdd.c"
"C:\_projects\abc\src\base\abci\abcPga.c"
"C:\_projects\abc\src\base\abci\abcPrint.c"
"C:\_projects\abc\src\base\abci\abcReconv.c"
"C:\_projects\abc\src\base\abci\abcRefactor.c"
"C:\_projects\abc\src\base\abci\abcRenode.c"
"C:\_projects\abc\src\base\abci\abcRewrite.c"
"C:\_projects\abc\src\base\abci\abcSat.c"
"C:\_projects\abc\src\base\abci\abcStrash.c"
"C:\_projects\abc\src\base\abci\abcSweep.c"
"C:\_projects\abc\src\base\abci\abcSymm.c"
"C:\_projects\abc\src\base\abci\abcTiming.c"
"C:\_projects\abc\src\base\abci\abcUnreach.c"
"C:\_projects\abc\src\base\abci\abcVanEijk.c"
"C:\_projects\abc\src\base\abci\abcVanImp.c"
"C:\_projects\abc\src\base\abci\abcVerify.c"
"C:\_projects\abc\src\base\seq\seqAigCore.c"
"C:\_projects\abc\src\base\seq\seqAigIter.c"
"C:\_projects\abc\src\base\seq\seqCreate.c"
"C:\_projects\abc\src\base\seq\seqFpgaCore.c"
"C:\_projects\abc\src\base\seq\seqFpgaIter.c"
"C:\_projects\abc\src\base\seq\seqLatch.c"
"C:\_projects\abc\src\base\seq\seqMan.c"
"C:\_projects\abc\src\base\seq\seqMapCore.c"
"C:\_projects\abc\src\base\seq\seqMapIter.c"
"C:\_projects\abc\src\base\seq\seqRetCore.c"
"C:\_projects\abc\src\base\seq\seqRetIter.c"
"C:\_projects\abc\src\base\seq\seqShare.c"
"C:\_projects\abc\src\base\seq\seqUtil.c"
"C:\_projects\abc\src\base\cmd\cmd.c"
"C:\_projects\abc\src\base\cmd\cmdAlias.c"
"C:\_projects\abc\src\base\cmd\cmdApi.c"
"C:\_projects\abc\src\base\cmd\cmdFlag.c"
"C:\_projects\abc\src\base\cmd\cmdHist.c"
"C:\_projects\abc\src\base\cmd\cmdUtils.c"
"C:\_projects\abc\src\base\io\io.c"
"C:\_projects\abc\src\base\io\ioRead.c"
"C:\_projects\abc\src\base\io\ioReadBaf.c"
"C:\_projects\abc\src\base\io\ioReadBench.c"
"C:\_projects\abc\src\base\io\ioReadBlif.c"
"C:\_projects\abc\src\base\io\ioReadEdif.c"
"C:\_projects\abc\src\base\io\ioReadEqn.c"
"C:\_projects\abc\src\base\io\ioReadPla.c"
"C:\_projects\abc\src\base\io\ioReadVerilog.c"
"C:\_projects\abc\src\base\io\ioUtil.c"
"C:\_projects\abc\src\base\io\ioWriteBaf.c"
"C:\_projects\abc\src\base\io\ioWriteBench.c"
"C:\_projects\abc\src\base\io\ioWriteBlif.c"
"C:\_projects\abc\src\base\io\ioWriteCnf.c"
"C:\_projects\abc\src\base\io\ioWriteDot.c"
"C:\_projects\abc\src\base\io\ioWriteEqn.c"
"C:\_projects\abc\src\base\io\ioWriteGml.c"
"C:\_projects\abc\src\base\io\ioWriteList.c"
"C:\_projects\abc\src\base\io\ioWritePla.c"
"C:\_projects\abc\src\base\io\ioWriteVerilog.c"
"C:\_projects\abc\src\base\main\libSupport.c"
"C:\_projects\abc\src\base\main\main.c"
"C:\_projects\abc\src\base\main\mainFrame.c"
"C:\_projects\abc\src\base\main\mainInit.c"
"C:\_projects\abc\src\base\main\mainUtils.c"
"C:\_projects\abc\src\sat\fraig\fraigSat.c"
"C:\_projects\abc\src\sat\csat\csat_apis.c"
"C:\_projects\abc\src\opt\fxu\fxuCreate.c"
"C:\_projects\abc\src\opt\fxu\fxuReduce.c"
"C:\_projects\abc\src\opt\rwr\rwrDec.c"
"C:\_projects\abc\src\opt\rwr\rwrEva.c"
"C:\_projects\abc\src\opt\rwr\rwrExp.c"
"C:\_projects\abc\src\opt\rwr\rwrLib.c"
"C:\_projects\abc\src\opt\rwr\rwrMan.c"
"C:\_projects\abc\src\opt\rwr\rwrPrint.c"
"C:\_projects\abc\src\opt\rwr\rwrUtil.c"
"C:\_projects\abc\src\opt\dec\decAbc.c"
"C:\_projects\abc\src\opt\dec\decFactor.c"
"C:\_projects\abc\src\opt\dec\decMan.c"
"C:\_projects\abc\src\opt\dec\decPrint.c"
"C:\_projects\abc\src\opt\dec\decUtil.c"
"C:\_projects\abc\src\opt\sim\simMan.c"
"C:\_projects\abc\src\opt\sim\simSat.c"
"C:\_projects\abc\src\opt\sim\simSeq.c"
"C:\_projects\abc\src\opt\sim\simSupp.c"
"C:\_projects\abc\src\opt\sim\simSwitch.c"
"C:\_projects\abc\src\opt\sim\simSym.c"
"C:\_projects\abc\src\opt\sim\simSymSat.c"
"C:\_projects\abc\src\opt\sim\simSymSim.c"
"C:\_projects\abc\src\opt\sim\simSymStr.c"
"C:\_projects\abc\src\opt\sim\simUtils.c"
"C:\_projects\abc\src\map\fpga\fpga.c"
"C:\_projects\abc\src\map\fpga\fpgaCreate.c"
"C:\_projects\abc\src\map\mapper\mapper.c"
"C:\_projects\abc\src\map\mapper\mapperCanon.c"
"C:\_projects\abc\src\map\mapper\mapperCore.c"
"C:\_projects\abc\src\map\mapper\mapperCreate.c"
"C:\_projects\abc\src\map\mapper\mapperCut.c"
"C:\_projects\abc\src\map\mapper\mapperCutUtils.c"
"C:\_projects\abc\src\map\mapper\mapperFanout.c"
"C:\_projects\abc\src\map\mapper\mapperLib.c"
"C:\_projects\abc\src\map\mapper\mapperMatch.c"
"C:\_projects\abc\src\map\mapper\mapperRefs.c"
"C:\_projects\abc\src\map\mapper\mapperSuper.c"
"C:\_projects\abc\src\map\mapper\mapperSwitch.c"
"C:\_projects\abc\src\map\mapper\mapperTable.c"
"C:\_projects\abc\src\map\mapper\mapperTime.c"
"C:\_projects\abc\src\map\mapper\mapperTree.c"
"C:\_projects\abc\src\map\mapper\mapperTruth.c"
"C:\_projects\abc\src\map\mapper\mapperUtils.c"
"C:\_projects\abc\src\map\mapper\mapperVec.c"
"C:\_projects\abc\src\map\mio\mio.c"
"C:\_projects\abc\src\map\mio\mioApi.c"
"C:\_projects\abc\src\map\mio\mioFunc.c"
"C:\_projects\abc\src\map\mio\mioRead.c"
"C:\_projects\abc\src\map\mio\mioUtils.c"
"C:\_projects\abc\src\map\super\super.c"
"C:\_projects\abc\src\map\super\superAnd.c"
"C:\_projects\abc\src\map\super\superGate.c"
"C:\_projects\abc\src\map\super\superWrite.c"
"C:\_projects\abc\src\map\pga\pgaCore.c"
"C:\_projects\abc\src\map\pga\pgaMan.c"
"C:\_projects\abc\src\map\pga\pgaMatch.c"
"C:\_projects\abc\src\map\pga\pgaUtil.c"
]
Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP513.tmp"
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP514.tmp" with contents
[
/nologo /out:"abclib\abclib_debug.lib"
.\abclib\DebugLib\abcAig.obj
.\abclib\DebugLib\abcCheck.obj
.\abclib\DebugLib\abcDfs.obj
.\abclib\DebugLib\abcFanio.obj
.\abclib\DebugLib\abcFunc.obj
.\abclib\DebugLib\abcLatch.obj
.\abclib\DebugLib\abcMinBase.obj
.\abclib\DebugLib\abcNames.obj
.\abclib\DebugLib\abcNetlist.obj
.\abclib\DebugLib\abcNtk.obj
.\abclib\DebugLib\abcObj.obj
.\abclib\DebugLib\abcRefs.obj
.\abclib\DebugLib\abcShow.obj
.\abclib\DebugLib\abcSop.obj
.\abclib\DebugLib\abcUtil.obj
.\abclib\DebugLib\abc.obj
.\abclib\DebugLib\abcAttach.obj
.\abclib\DebugLib\abcBalance.obj
.\abclib\DebugLib\abcCollapse.obj
.\abclib\DebugLib\abcCut.obj
.\abclib\DebugLib\abcDsd.obj
.\abclib\DebugLib\abcFpga.obj
.\abclib\DebugLib\abcFraig.obj
.\abclib\DebugLib\abcFxu.obj
.\abclib\DebugLib\abcMap.obj
.\abclib\DebugLib\abcMiter.obj
.\abclib\DebugLib\abcNtbdd.obj
.\abclib\DebugLib\abcPga.obj
.\abclib\DebugLib\abcPrint.obj
.\abclib\DebugLib\abcReconv.obj
.\abclib\DebugLib\abcRefactor.obj
.\abclib\DebugLib\abcRenode.obj
.\abclib\DebugLib\abcRewrite.obj
.\abclib\DebugLib\abcSat.obj
.\abclib\DebugLib\abcStrash.obj
.\abclib\DebugLib\abcSweep.obj
.\abclib\DebugLib\abcSymm.obj
.\abclib\DebugLib\abcTiming.obj
.\abclib\DebugLib\abcUnreach.obj
.\abclib\DebugLib\abcVanEijk.obj
.\abclib\DebugLib\abcVanImp.obj
.\abclib\DebugLib\abcVerify.obj
.\abclib\DebugLib\seqAigCore.obj
.\abclib\DebugLib\seqAigIter.obj
.\abclib\DebugLib\seqCreate.obj
.\abclib\DebugLib\seqFpgaCore.obj
.\abclib\DebugLib\seqFpgaIter.obj
.\abclib\DebugLib\seqLatch.obj
.\abclib\DebugLib\seqMan.obj
.\abclib\DebugLib\seqMapCore.obj
.\abclib\DebugLib\seqMapIter.obj
.\abclib\DebugLib\seqRetCore.obj
.\abclib\DebugLib\seqRetIter.obj
.\abclib\DebugLib\seqShare.obj
.\abclib\DebugLib\seqUtil.obj
.\abclib\DebugLib\cmd.obj
.\abclib\DebugLib\cmdAlias.obj
.\abclib\DebugLib\cmdApi.obj
.\abclib\DebugLib\cmdFlag.obj
.\abclib\DebugLib\cmdHist.obj
.\abclib\DebugLib\cmdUtils.obj
.\abclib\DebugLib\io.obj
.\abclib\DebugLib\ioRead.obj
.\abclib\DebugLib\ioReadBaf.obj
.\abclib\DebugLib\ioReadBench.obj
.\abclib\DebugLib\ioReadBlif.obj
.\abclib\DebugLib\ioReadEdif.obj
.\abclib\DebugLib\ioReadEqn.obj
.\abclib\DebugLib\ioReadPla.obj
.\abclib\DebugLib\ioReadVerilog.obj
.\abclib\DebugLib\ioUtil.obj
.\abclib\DebugLib\ioWriteBaf.obj
.\abclib\DebugLib\ioWriteBench.obj
.\abclib\DebugLib\ioWriteBlif.obj
.\abclib\DebugLib\ioWriteCnf.obj
.\abclib\DebugLib\ioWriteDot.obj
.\abclib\DebugLib\ioWriteEqn.obj
.\abclib\DebugLib\ioWriteGml.obj
.\abclib\DebugLib\ioWriteList.obj
.\abclib\DebugLib\ioWritePla.obj
.\abclib\DebugLib\ioWriteVerilog.obj
.\abclib\DebugLib\libSupport.obj
.\abclib\DebugLib\main.obj
.\abclib\DebugLib\mainFrame.obj
.\abclib\DebugLib\mainInit.obj
.\abclib\DebugLib\mainUtils.obj
.\abclib\DebugLib\cuddAddAbs.obj
.\abclib\DebugLib\cuddAddApply.obj
.\abclib\DebugLib\cuddAddFind.obj
.\abclib\DebugLib\cuddAddInv.obj
.\abclib\DebugLib\cuddAddIte.obj
.\abclib\DebugLib\cuddAddNeg.obj
.\abclib\DebugLib\cuddAddWalsh.obj
.\abclib\DebugLib\cuddAndAbs.obj
.\abclib\DebugLib\cuddAnneal.obj
.\abclib\DebugLib\cuddApa.obj
.\abclib\DebugLib\cuddAPI.obj
.\abclib\DebugLib\cuddApprox.obj
.\abclib\DebugLib\cuddBddAbs.obj
.\abclib\DebugLib\cuddBddCorr.obj
.\abclib\DebugLib\cuddBddIte.obj
.\abclib\DebugLib\cuddBridge.obj
.\abclib\DebugLib\cuddCache.obj
.\abclib\DebugLib\cuddCheck.obj
.\abclib\DebugLib\cuddClip.obj
.\abclib\DebugLib\cuddCof.obj
.\abclib\DebugLib\cuddCompose.obj
.\abclib\DebugLib\cuddDecomp.obj
.\abclib\DebugLib\cuddEssent.obj
.\abclib\DebugLib\cuddExact.obj
.\abclib\DebugLib\cuddExport.obj
.\abclib\DebugLib\cuddGenCof.obj
.\abclib\DebugLib\cuddGenetic.obj
.\abclib\DebugLib\cuddGroup.obj
.\abclib\DebugLib\cuddHarwell.obj
.\abclib\DebugLib\cuddInit.obj
.\abclib\DebugLib\cuddInteract.obj
.\abclib\DebugLib\cuddLCache.obj
.\abclib\DebugLib\cuddLevelQ.obj
.\abclib\DebugLib\cuddLinear.obj
.\abclib\DebugLib\cuddLiteral.obj
.\abclib\DebugLib\cuddMatMult.obj
.\abclib\DebugLib\cuddPriority.obj
.\abclib\DebugLib\cuddRead.obj
.\abclib\DebugLib\cuddRef.obj
.\abclib\DebugLib\cuddReorder.obj
.\abclib\DebugLib\cuddSat.obj
.\abclib\DebugLib\cuddSign.obj
.\abclib\DebugLib\cuddSolve.obj
.\abclib\DebugLib\cuddSplit.obj
.\abclib\DebugLib\cuddSubsetHB.obj
.\abclib\DebugLib\cuddSubsetSP.obj
.\abclib\DebugLib\cuddSymmetry.obj
.\abclib\DebugLib\cuddTable.obj
.\abclib\DebugLib\cuddUtil.obj
.\abclib\DebugLib\cuddWindow.obj
.\abclib\DebugLib\cuddZddCount.obj
.\abclib\DebugLib\cuddZddFuncs.obj
.\abclib\DebugLib\cuddZddGroup.obj
.\abclib\DebugLib\cuddZddIsop.obj
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.\abclib\DebugLib\fxu.obj
.\abclib\DebugLib\fxuCreate.obj
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.\abclib\DebugLib\rwrDec.obj
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.\abclib\DebugLib\mio.obj
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.\abclib\DebugLib\mvcDivide.obj
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]
Creating command line "link.exe -lib @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP514.tmp"
<h3>Output Window</h3>
Compiling...
abcAig.c
abcCheck.c
abcDfs.c
abcFanio.c
abcFunc.c
abcLatch.c
abcMinBase.c
abcNames.c
abcNetlist.c
abcNtk.c
abcObj.c
abcRefs.c
abcShow.c
abcSop.c
abcUtil.c
abc.c
C:\_projects\abc\src\base\abci\abc.c(2890) : warning C4013: 'Abc_NtkMiterSat2' undefined; assuming extern returning int
abcAttach.c
abcBalance.c
abcCollapse.c
abcCut.c
abcDsd.c
abcFpga.c
abcFraig.c
abcFxu.c
abcMap.c
abcMiter.c
abcNtbdd.c
abcPga.c
abcPrint.c
abcReconv.c
abcRefactor.c
abcRenode.c
abcRewrite.c
abcSat.c
abcStrash.c
abcSweep.c
abcSymm.c
abcTiming.c
abcUnreach.c
abcVanEijk.c
abcVanImp.c
abcVerify.c
seqAigCore.c
seqAigIter.c
seqCreate.c
seqFpgaCore.c
seqFpgaIter.c
seqLatch.c
seqMan.c
seqMapCore.c
seqMapIter.c
seqRetCore.c
seqRetIter.c
seqShare.c
seqUtil.c
cmd.c
cmdAlias.c
cmdApi.c
cmdFlag.c
cmdHist.c
cmdUtils.c
io.c
ioRead.c
ioReadBaf.c
ioReadBench.c
ioReadBlif.c
ioReadEdif.c
ioReadEqn.c
ioReadPla.c
ioReadVerilog.c
ioUtil.c
ioWriteBaf.c
ioWriteBench.c
ioWriteBlif.c
ioWriteCnf.c
ioWriteDot.c
ioWriteEqn.c
ioWriteGml.c
ioWriteList.c
ioWritePla.c
ioWriteVerilog.c
libSupport.c
main.c
mainFrame.c
mainInit.c
mainUtils.c
fraigSat.c
csat_apis.c
fxuCreate.c
fxuReduce.c
rwrDec.c
rwrEva.c
rwrExp.c
rwrLib.c
rwrMan.c
rwrPrint.c
rwrUtil.c
decAbc.c
decFactor.c
decMan.c
decPrint.c
decUtil.c
simMan.c
simSat.c
simSeq.c
simSupp.c
simSwitch.c
simSym.c
simSymSat.c
simSymSim.c
simSymStr.c
simUtils.c
fpga.c
fpgaCreate.c
mapper.c
mapperCanon.c
mapperCore.c
mapperCreate.c
mapperCut.c
mapperCutUtils.c
mapperFanout.c
mapperLib.c
mapperMatch.c
mapperRefs.c
mapperSuper.c
mapperSwitch.c
mapperTable.c
mapperTime.c
mapperTree.c
mapperTruth.c
mapperUtils.c
mapperVec.c
mio.c
mioApi.c
mioFunc.c
mioRead.c
mioUtils.c
super.c
superAnd.c
superGate.c
superWrite.c
pgaCore.c
pgaMan.c
pgaMatch.c
pgaUtil.c
Creating library...
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP515.tmp" with contents
[
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.\abclib\DebugLib\mapperUtils.sbr
.\abclib\DebugLib\mapperVec.sbr
.\abclib\DebugLib\mio.sbr
.\abclib\DebugLib\mioApi.sbr
.\abclib\DebugLib\mioFunc.sbr
.\abclib\DebugLib\mioRead.sbr
.\abclib\DebugLib\mioUtils.sbr
.\abclib\DebugLib\super.sbr
.\abclib\DebugLib\superAnd.sbr
.\abclib\DebugLib\superGate.sbr
.\abclib\DebugLib\superWrite.sbr
.\abclib\DebugLib\pgaCore.sbr
.\abclib\DebugLib\pgaMan.sbr
.\abclib\DebugLib\pgaMatch.sbr
.\abclib\DebugLib\pgaUtil.sbr
.\abclib\DebugLib\extraBddKmap.sbr
.\abclib\DebugLib\extraBddMisc.sbr
.\abclib\DebugLib\extraBddSymm.sbr
.\abclib\DebugLib\extraUtilBitMatrix.sbr
.\abclib\DebugLib\extraUtilCanon.sbr
.\abclib\DebugLib\extraUtilFile.sbr
.\abclib\DebugLib\extraUtilMemory.sbr
.\abclib\DebugLib\extraUtilMisc.sbr
.\abclib\DebugLib\extraUtilProgress.sbr
.\abclib\DebugLib\extraUtilReader.sbr
.\abclib\DebugLib\st.sbr
.\abclib\DebugLib\stmm.sbr
.\abclib\DebugLib\cpu_stats.sbr
.\abclib\DebugLib\cpu_time.sbr
.\abclib\DebugLib\datalimit.sbr
.\abclib\DebugLib\getopt.sbr
.\abclib\DebugLib\pathsearch.sbr
.\abclib\DebugLib\safe_mem.sbr
.\abclib\DebugLib\strsav.sbr
.\abclib\DebugLib\texpand.sbr
.\abclib\DebugLib\mvc.sbr
.\abclib\DebugLib\mvcApi.sbr
.\abclib\DebugLib\mvcCompare.sbr
.\abclib\DebugLib\mvcContain.sbr
.\abclib\DebugLib\mvcCover.sbr
.\abclib\DebugLib\mvcCube.sbr
.\abclib\DebugLib\mvcDivide.sbr
.\abclib\DebugLib\mvcDivisor.sbr
.\abclib\DebugLib\mvcList.sbr
.\abclib\DebugLib\mvcLits.sbr
.\abclib\DebugLib\mvcMan.sbr
.\abclib\DebugLib\mvcOpAlg.sbr
.\abclib\DebugLib\mvcOpBool.sbr
.\abclib\DebugLib\mvcPrint.sbr
.\abclib\DebugLib\mvcSort.sbr
.\abclib\DebugLib\mvcUtils.sbr]
Creating command line "bscmake.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP515.tmp"
Creating browse info file...
<h3>Output Window</h3>
<h3>Results</h3>
abclib_debug.lib - 0 error(s), 1 warning(s)
</pre>
</body>
</html>

BIN
abctestlib.opt
View File

Binary file not shown.

32
abctestlib.plg
View File

@ -1,32 +0,0 @@
<html>
<body>
<pre>
<h1>Build Log</h1>
<h3>
--------------------Configuration: abctestlib - Win32 Release--------------------
</h3>
<h3>Command Lines</h3>
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP86.tmp" with contents
[
/nologo /ML /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /Fp"Release/abctestlib.pch" /YX /Fo"Release/" /Fd"Release/" /FD /c
"C:\_projects\abctestlib\demo.c"
]
Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP86.tmp"
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP87.tmp" with contents
[
kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib C:\_projects\abc\abclib\abclib_release.lib /nologo /subsystem:console /incremental:no /pdb:"Release/abctestlib.pdb" /machine:I386 /out:"_TEST/abctestlib.exe"
.\Release\demo.obj
]
Creating command line "link.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP87.tmp"
<h3>Output Window</h3>
Compiling...
demo.c
Linking...
<h3>Results</h3>
abctestlib.exe - 0 error(s), 0 warning(s)
</pre>
</body>
</html>

67
mcnc_temp.genlib_temp
View File

@ -1,67 +0,0 @@
# The genlib library "mcnc_temp.genlib".
GATE inv1 1.00 O=!a;
PIN a INV 1 999 0.90 0.00 0.90 0.00
GATE inv2 2.00 O=!a;
PIN a INV 2 999 1.00 0.00 1.00 0.00
GATE inv3 3.00 O=!a;
PIN a INV 3 999 1.10 0.00 1.10 0.00
GATE inv4 4.00 O=!a;
PIN a INV 4 999 1.20 0.00 1.20 0.00
GATE nand2 2.00 O=!(a*b);
PIN a INV 1 999 1.00 0.00 1.00 0.00
PIN b INV 1 999 1.00 0.00 1.00 0.00
GATE nand3 3.00 O=!(a*b*c);
PIN a INV 1 999 1.10 0.00 1.10 0.00
PIN b INV 1 999 1.10 0.00 1.10 0.00
PIN c INV 1 999 1.10 0.00 1.10 0.00
GATE nand4 4.00 O=!(a*b*c*d);
PIN a INV 1 999 1.40 0.00 1.40 0.00
PIN b INV 1 999 1.40 0.00 1.40 0.00
PIN c INV 1 999 1.40 0.00 1.40 0.00
PIN d INV 1 999 1.40 0.00 1.40 0.00
GATE nor2 2.00 O=!(a+b);
PIN a INV 1 999 1.40 0.00 1.40 0.00
PIN b INV 1 999 1.40 0.00 1.40 0.00
GATE nor3 3.00 O=!(a+b+c);
PIN a INV 1 999 2.40 0.00 2.40 0.00
PIN b INV 1 999 2.40 0.00 2.40 0.00
PIN c INV 1 999 2.40 0.00 2.40 0.00
GATE nor4 4.00 O=!(a+b+c+d);
PIN a INV 1 999 3.80 0.00 3.80 0.00
PIN b INV 1 999 3.80 0.00 3.80 0.00
PIN c INV 1 999 3.80 0.00 3.80 0.00
PIN d INV 1 999 3.80 0.00 3.80 0.00
GATE xora 5.00 O=a*!b+!a*b;
PIN a UNKNOWN 2 999 1.90 0.00 1.90 0.00
PIN b UNKNOWN 2 999 1.90 0.00 1.90 0.00
GATE xorb 5.00 O=!(a*b+!a*!b);
PIN a UNKNOWN 2 999 1.90 0.00 1.90 0.00
PIN b UNKNOWN 2 999 1.90 0.00 1.90 0.00
GATE xnora 5.00 O=a*b+!a*!b;
PIN a UNKNOWN 2 999 2.10 0.00 2.10 0.00
PIN b UNKNOWN 2 999 2.10 0.00 2.10 0.00
GATE xnorb 5.00 O=!(!a*b+a*!b);
PIN a UNKNOWN 2 999 2.10 0.00 2.10 0.00
PIN b UNKNOWN 2 999 2.10 0.00 2.10 0.00
GATE aoi21 3.00 O=!(a*b+c);
PIN a INV 1 999 1.60 0.00 1.60 0.00
PIN b INV 1 999 1.60 0.00 1.60 0.00
PIN c INV 1 999 1.60 0.00 1.60 0.00
GATE aoi22 4.00 O=!(a*b+c*d);
PIN a INV 1 999 2.00 0.00 2.00 0.00
PIN b INV 1 999 2.00 0.00 2.00 0.00
PIN c INV 1 999 2.00 0.00 2.00 0.00
PIN d INV 1 999 2.00 0.00 2.00 0.00
GATE oai21 3.00 O=!((a+b)*c);
PIN a INV 1 999 1.60 0.00 1.60 0.00
PIN b INV 1 999 1.60 0.00 1.60 0.00
PIN c INV 1 999 1.60 0.00 1.60 0.00
GATE oai22 4.00 O=!((a+b)*(c+d));
PIN a INV 1 999 2.00 0.00 2.00 0.00
PIN b INV 1 999 2.00 0.00 2.00 0.00
PIN c INV 1 999 2.00 0.00 2.00 0.00
PIN d INV 1 999 2.00 0.00 2.00 0.00
GATE buf 1.00 O=a;
PIN a NONINV 1 999 1.00 0.00 1.00 0.00
GATE zero 0.00 O=CONST0;
GATE one 0.00 O=CONST1;

42
mcnc_temp.super
View File

@ -1,42 +0,0 @@
#
# Supergate library derived for "mcnc_temp.genlib_temp" on Sun Dec 25 06:29:48 2005.
#
# Command line: "super -i 5 -l 1 -d 10000000.00 -a 10000000.00 -t 100 mcnc_temp.genlib_temp".
#
# The number of inputs = 5.
# The number of levels = 1.
# The maximum delay = 10000000.00.
# The maximum area = 10000000.00.
# The maximum runtime (sec) = 100.
#
# The number of attempts = 860.
# The number of supergates = 20.
# The number of functions = 0.
# The total functions = 4294967296 (2^32).
#
# Generation time (sec) = 0.01.
#
mcnc_temp.genlib_temp
5
20
25
* xorb 1 0
* nor4 2 1 0 3
* nor3 2 1 0
* oai22 2 1 0 3
* oai22 2 0 1 3
* aoi21 1 0 2
* aoi22 2 3 1 0
* nor2 1 0
* oai22 2 3 1 0
* aoi21 2 0 1
* aoi22 2 0 1 3
* aoi21 2 1 0
* aoi22 2 1 0 3
* oai21 1 0 2
* oai21 2 0 1
* oai21 2 1 0
* nand2 1 0
* nand3 2 1 0
* nand4 2 1 0 3
* xnora 1 0

51
regtest_output.txt
View File

@ -1,16 +1,16 @@
UC Berkeley, ABC 1.01 (compiled Dec 3 2005 16:58:37)
UC Berkeley, ABC 1.01 (compiled Feb 3 2006 10:48:34)
abc 01> so regtest.script
abc - > r examples/apex4.pla; resyn; sharem; fpga; cec; ps; clp; share; resyn; map; cec; ps
Networks are equivalent after fraiging.
examples/apex4: i/o = 9/ 19 lat = 0 nd = 1182 cube = 2193 lev = 7
examples/apex4: i/o = 9/ 19 lat = 0 nd = 1185 cube = 2200 lev = 7
The shared BDD size is 900 nodes.
A simple supergate library is derived from gate library "mcnc_temp.genlib".
Loaded 20 unique 5-input supergates from "mcnc_temp.super". Time = 0.02 sec
Loaded 20 unique 5-input supergates from "mcnc_temp.super". Time = 0.03 sec
Networks are equivalent after fraiging.
examples/apex4: i/o = 9/ 19 lat = 0 nd = 1849 area = 4581.00 delay = 11.60 lev = 11
examples/apex4: i/o = 9/ 19 lat = 0 nd = 1837 area = 4560.00 delay = 11.70 lev = 11
abc - > r examples/C2670.blif; resyn; fpga; cec; ps; u; map; cec; ps
Networks are equivalent after fraiging.
C2670.iscas : i/o = 233/ 140 lat = 0 nd = 219 cube = 446 lev = 7
C2670.iscas : i/o = 233/ 140 lat = 0 nd = 218 cube = 444 lev = 7
Networks are equivalent after fraiging.
C2670.iscas : i/o = 233/ 140 lat = 0 nd = 466 area = 1160.00 delay = 15.50 lev = 14
abc - > r examples/frg2.blif; dsd; muxes; cec; clp; share; resyn; map; cec; ps
@ -20,17 +20,17 @@ Networks are equivalent after fraiging.
frg2 : i/o = 143/ 139 lat = 0 nd = 547 area = 1381.00 delay = 9.70 lev = 9
abc - > r examples/pj1.blif; resyn; fpga; cec; ps; u; map; cec; ps
Networks are equivalent after fraiging.
exCombCkt : i/o = 1769/1063 lat = 0 nd = 5611 cube = 10398 lev = 15
exCombCkt : i/o = 1769/1063 lat = 0 nd = 5609 cube = 10395 lev = 15
Networks are equivalent after fraiging.
exCombCkt : i/o = 1769/1063 lat = 0 nd = 10317 area = 24980.00 delay = 29.80 lev = 27
abc - > r examples/s38584.bench; resyn; fpga; cec; ps; u; map; cec; ps
Networks are equivalent after fraiging.
examples/s38584: i/o = 12/ 278 lat = 1452 nd = 4411 cube = 7544 lev = 9
examples/s38584: i/o = 12/ 278 lat = 1452 nd = 4405 cube = 7515 lev = 9
Networks are equivalent after fraiging.
examples/s38584: i/o = 12/ 278 lat = 1452 nd = 8510 area = 19315.00 delay = 20.60 lev = 17
examples/s38584: i/o = 12/ 278 lat = 1452 nd = 8509 area = 19316.00 delay = 20.60 lev = 17
abc - > r examples/ac.v; resyn; fpga; cec; ps; u; map; cec; ps
Networks are equivalent after fraiging.
ac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 4086 cube = 7790 lev = 4
ac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 4085 cube = 7780 lev = 4
Networks are equivalent after fraiging.
ac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 8278 area = 19714.00 delay = 8.10 lev = 8
abc - > r examples/s444.blif; b; esd -v; dsd; cec; ps
@ -42,14 +42,14 @@ The number of minterms in the reachable state set = 8865.
BDD nodes in the unreachable states before reordering 124.
BDD nodes in the unreachable states after reordering 113.
Networks are equivalent after fraiging.
s444 : i/o = 3/ 6 lat = 21 nd = 81 cube = 120 lev = 7
s444 : i/o = 3/ 6 lat = 21 nd = 81 cube = 119 lev = 7
abc - > r examples/i10.blif; fpga; cec; ps; u; map; cec; ps
The network was strashed and balanced before FPGA mapping.
Networks are equivalent after fraiging.
i10 : i/o = 257/ 224 lat = 0 nd = 898 cube = 1603 lev = 13
i10 : i/o = 257/ 224 lat = 0 nd = 899 cube = 1604 lev = 13
The network was strashed and balanced before mapping.
Networks are equivalent after fraiging.
i10 : i/o = 257/ 224 lat = 0 nd = 1708 area = 4275.00 delay = 30.80 lev = 28
i10 : i/o = 257/ 224 lat = 0 nd = 1676 area = 4219.00 delay = 30.80 lev = 29
abc - > r examples/i10.blif; choice; fpga; cec; ps; u; map; cec; ps
The number of AIG nodes added to storage = 2675.
The number of AIG nodes added to storage = 1744.
@ -57,21 +57,25 @@ The number of AIG nodes added to storage = 1431.
Currently stored 3 networks with 5850 nodes will be fraiged.
Performing FPGA mapping with choices.
Networks are equivalent after fraiging.
i10 : i/o = 257/ 224 lat = 0 nd = 793 cube = 1454 lev = 12
i10 : i/o = 257/ 224 lat = 0 nd = 792 cube = 1459 lev = 12
Performing mapping with choices.
Networks are equivalent after fraiging.
i10 : i/o = 257/ 224 lat = 0 nd = 1485 area = 3521.00 delay = 25.60 lev = 23
i10 : i/o = 257/ 224 lat = 0 nd = 1484 area = 3518.00 delay = 25.60 lev = 23
abc - > r examples/s6669.blif; fpga; ps; sec; u; sfpga; ps; sec; u; fpga; ret; ps; sec
The network was strashed and balanced before FPGA mapping.
s6669 : i/o = 83/ 55 lat = 239 nd = 678 bdd = 3036 lev = 20
s6669 : i/o = 83/ 55 lat = 239 nd = 679 bdd = 3046 lev = 20
Networks are equivalent after fraiging.
The network was strashed and balanced before FPGA mapping/retiming.
The number of LUTs with incompatible edges = 99.
The number of LUTs with more than 4 inputs = 61.
s6669 : i/o = 83/ 55 lat = 451 nd = 865 bdd = 4221 lev = 6
The number of MUXes detected = 120 (34.25 % of logic). Creating solver = 0.00 sec
SAT solver time = 0.00 sec
The number of LUTs with incompatible edges = 24.
The number of LUTs with more than 4 inputs = 18.
s6669 : i/o = 83/ 55 lat = 404 nd = 818 bdd = 3829 lev = 6
Networks are equivalent after fraiging.
The network was strashed and balanced before FPGA mapping.
s6669 : i/o = 83/ 55 lat = 393 nd = 787 bdd = 3300 lev = 8
The number of MUXes detected = 69 (37.03 % of logic). Creating solver = 0.00 sec
SAT solver time = 0.00 sec
s6669 : i/o = 83/ 55 lat = 346 nd = 772 bdd = 3254 lev = 9
Networks are equivalent after fraiging.
abc - > r examples/s5378.blif; map -s; ps; sec; u; smap; ps; sec; u; map; ret; ps; sec
The network was strashed and balanced before mapping.
@ -81,10 +85,13 @@ The number of nodes with equal fanins = 5.
The network was strashed and balanced before SC mapping/retiming.
The mininum clock period computed is 10.00.
The resulting network is derived as BDD logic network (this is temporary).
s5378 : i/o = 35/ 49 lat = 396 nd = 1252 bdd = 4619 lev = 7
The number of MUXes detected = 0 ( 0.00 % of logic). Creating solver = 0.00 sec
SAT solver time = 0.00 sec
s5378 : i/o = 35/ 49 lat = 396 nd = 1252 bdd = 4612 lev = 7
Networks are equivalent after fraiging.
The network was strashed and balanced before mapping.
s5378 : i/o = 35/ 49 lat = 364 nd = 1084 area = 2453.00 delay = 11.70 lev = 11
s5378 : i/o = 35/ 49 lat = 360 nd = 1087 area = 2454.00 delay = 12.10 lev = 11
Networks are equivalent after fraiging.
abc - > time
elapse: 42.05 seconds, total: 42.05 seconds
elapse: 39.54 seconds, total: 39.54 seconds
abc 122>

4
src/base/abc/abc.h
View File

@ -425,7 +425,7 @@ extern void Abc_AigSetNodePhases( Abc_Ntk_t * pNtk );
/*=== abcAttach.c ==========================================================*/
extern int Abc_NtkAttach( Abc_Ntk_t * pNtk );
/*=== abcBalance.c ==========================================================*/
extern Abc_Ntk_t * Abc_NtkBalance( Abc_Ntk_t * pNtk, bool fDuplicate );
extern Abc_Ntk_t * Abc_NtkBalance( Abc_Ntk_t * pNtk, bool fDuplicate, bool fSelective );
/*=== abcCheck.c ==========================================================*/
extern bool Abc_NtkCheck( Abc_Ntk_t * pNtk );
extern bool Abc_NtkCheckRead( Abc_Ntk_t * pNtk );
@ -587,6 +587,7 @@ extern DdNode * Abc_NodeConeDcs( DdManager * dd, DdNode ** pbVarsX, Dd
extern Vec_Ptr_t * Abc_NodeCollectTfoCands( Abc_ManCut_t * p, Abc_Obj_t * pRoot, Vec_Ptr_t * vFanins, int LevelMax );
/*=== abcRefs.c ==========================================================*/
extern int Abc_NodeMffcSize( Abc_Obj_t * pNode );
extern int Abc_NodeMffcSizeSupp( Abc_Obj_t * pNode );
extern int Abc_NodeMffcSizeStop( Abc_Obj_t * pNode );
extern int Abc_NodeMffcLabel( Abc_Obj_t * pNode );
extern int Abc_NodeMffcLabelFast( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes );
@ -673,6 +674,7 @@ extern int Abc_NtkGetChoiceNum( Abc_Ntk_t * pNtk );
extern int Abc_NtkGetFaninMax( Abc_Ntk_t * pNtk );
extern void Abc_NtkCleanCopy( Abc_Ntk_t * pNtk );
extern void Abc_NtkCleanNext( Abc_Ntk_t * pNtk );
extern void Abc_NtkCleanMarkA( Abc_Ntk_t * pNtk );
extern Abc_Obj_t * Abc_NodeHasUniqueCoFanout( Abc_Obj_t * pNode );
extern bool Abc_NtkLogicHasSimpleCos( Abc_Ntk_t * pNtk );
extern int Abc_NtkLogicMakeSimpleCos( Abc_Ntk_t * pNtk, bool fDuplicate );

88
src/base/abc/abcRefs.c
View File

@ -25,6 +25,7 @@
////////////////////////////////////////////////////////////////////////
static int Abc_NodeRefDeref( Abc_Obj_t * pNode, bool fReference, bool fLabel, Vec_Ptr_t * vNodes );
static int Abc_NodeMffcCountSupp( Vec_Ptr_t * vNodes );
static int Abc_NodeRefDerefStop( Abc_Obj_t * pNode, bool fReference );
static int Abc_NodeDeref( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes );
@ -46,6 +47,7 @@ static int Abc_NodeDeref( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes );
int Abc_NodeMffcSize( Abc_Obj_t * pNode )
{
int nConeSize1, nConeSize2;
assert( Abc_NtkIsStrash(pNode->pNtk) );
assert( !Abc_ObjIsComplement( pNode ) );
assert( Abc_ObjIsNode( pNode ) );
if ( Abc_ObjFaninNum(pNode) == 0 )
@ -57,6 +59,36 @@ int Abc_NodeMffcSize( Abc_Obj_t * pNode )
return nConeSize1;
}
/**Function*************************************************************
Synopsis [Returns the MFFC size.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NodeMffcSizeSupp( Abc_Obj_t * pNode )
{
Vec_Ptr_t * vNodes;
int nSuppSize, nConeSize1, nConeSize2;
assert( Abc_NtkIsStrash(pNode->pNtk) );
assert( !Abc_ObjIsComplement( pNode ) );
assert( Abc_ObjIsNode( pNode ) );
if ( Abc_ObjFaninNum(pNode) == 0 )
return 0;
vNodes = Vec_PtrAlloc( 10 );
nConeSize1 = Abc_NodeRefDeref( pNode, 0, 0, vNodes ); // dereference
nSuppSize = Abc_NodeMffcCountSupp(vNodes);
nConeSize2 = Abc_NodeRefDeref( pNode, 1, 0, NULL ); // reference
assert( nConeSize1 == nConeSize2 );
assert( nConeSize1 > 0 );
Vec_PtrFree(vNodes);
return nSuppSize;
}
/**Function*************************************************************
Synopsis [Returns the MFFC size while stopping at the complemented edges.]
@ -71,6 +103,7 @@ int Abc_NodeMffcSize( Abc_Obj_t * pNode )
int Abc_NodeMffcSizeStop( Abc_Obj_t * pNode )
{
int nConeSize1, nConeSize2;
assert( Abc_NtkIsStrash(pNode->pNtk) );
assert( !Abc_ObjIsComplement( pNode ) );
assert( Abc_ObjIsNode( pNode ) );
if ( Abc_ObjFaninNum(pNode) == 0 )
@ -217,6 +250,61 @@ int Abc_NodeRefDeref( Abc_Obj_t * pNode, bool fReference, bool fLabel, Vec_Ptr_t
return Counter;
}
/**Function*************************************************************
Synopsis [References/references the node and returns MFFC supp size.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NodeMffcCountSupp( Vec_Ptr_t * vNodes )
{
Abc_Obj_t * pNode, * pNode0, * pNode1;
int i, Counter = 0;
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( Abc_ObjIsCi(pNode) )
{
if ( pNode->fMarkB == 0 )
{
pNode->fMarkB = 1;
Counter++;
}
continue;
}
pNode0 = Abc_ObjFanin0(pNode);
if ( pNode0->vFanouts.nSize > 0 && pNode0->fMarkB == 0 )
{
pNode0->fMarkB = 1;
Counter++;
}
pNode1 = Abc_ObjFanin1(pNode);
if ( pNode1->vFanouts.nSize > 0 && pNode1->fMarkB == 0 )
{
pNode1->fMarkB = 1;
Counter++;
}
}
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( Abc_ObjIsCi(pNode) )
{
pNode->fMarkB = 0;
continue;
}
pNode0 = Abc_ObjFanin0(pNode);
pNode0->fMarkB = 0;
pNode1 = Abc_ObjFanin1(pNode);
pNode1->fMarkB = 0;
}
return Counter;
}
/**Function*************************************************************
Synopsis [References/references the node and returns MFFC size.]

2
src/base/abc/abcSop.c
View File

@ -308,7 +308,7 @@ char * Abc_SopCreateXorSpecial( Extra_MmFlex_t * pMan, int nVars )
char * Abc_SopCreateNxor( Extra_MmFlex_t * pMan, int nVars )
{
assert( nVars == 2 );
return Abc_SopRegister(pMan, "11 1\n11 1\n");
return Abc_SopRegister(pMan, "11 1\n00 1\n");
}
/**Function*************************************************************

19
src/base/abc/abcUtil.c
View File

@ -333,6 +333,25 @@ void Abc_NtkCleanNext( Abc_Ntk_t * pNtk )
pObj->pNext = NULL;
}
/**Function*************************************************************
Synopsis [Cleans the copy field of all objects.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkCleanMarkA( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pObj;
int i = 0;
Abc_NtkForEachObj( pNtk, pObj, i )
pObj->fMarkA = 0;
}
/**Function*************************************************************
Synopsis [Checks if the internal node has a unique CO.]

330
src/base/abci/abc.c
View File

@ -40,6 +40,8 @@ static int Abc_CommandPrintFactor ( Abc_Frame_t * pAbc, int argc, char ** argv
static int Abc_CommandPrintLevel ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandPrintSupport ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandPrintSymms ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandPrintUnate ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandPrintAuto ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandPrintKMap ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandPrintGates ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandPrintSharing ( Abc_Frame_t * pAbc, int argc, char ** argv );
@ -137,6 +139,8 @@ void Abc_Init( Abc_Frame_t * pAbc )
Cmd_CommandAdd( pAbc, "Printing", "print_level", Abc_CommandPrintLevel, 0 );
Cmd_CommandAdd( pAbc, "Printing", "print_supp", Abc_CommandPrintSupport, 0 );
Cmd_CommandAdd( pAbc, "Printing", "print_symm", Abc_CommandPrintSymms, 0 );
Cmd_CommandAdd( pAbc, "Printing", "print_unate", Abc_CommandPrintUnate, 0 );
Cmd_CommandAdd( pAbc, "Printing", "print_auto", Abc_CommandPrintAuto, 0 );
Cmd_CommandAdd( pAbc, "Printing", "print_kmap", Abc_CommandPrintKMap, 0 );
Cmd_CommandAdd( pAbc, "Printing", "print_gates", Abc_CommandPrintGates, 0 );
Cmd_CommandAdd( pAbc, "Printing", "print_sharing", Abc_CommandPrintSharing, 0 );
@ -247,7 +251,7 @@ int Abc_CommandPrintStats( Abc_Frame_t * pAbc, int argc, char ** argv )
int c;
int fFactor;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -310,7 +314,7 @@ int Abc_CommandPrintExdc( Abc_Frame_t * pAbc, int argc, char ** argv )
extern double Abc_NtkSpacePercentage( Abc_Obj_t * pNode );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -398,7 +402,7 @@ int Abc_CommandPrintIo( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Obj_t * pNode;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -467,7 +471,7 @@ int Abc_CommandPrintLatch( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Ntk_t * pNtk;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -517,7 +521,7 @@ int Abc_CommandPrintFanio( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Ntk_t * pNtk;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -570,7 +574,7 @@ int Abc_CommandPrintFactor( Abc_Frame_t * pAbc, int argc, char ** argv )
int c;
int fUseRealNames;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -653,7 +657,7 @@ int Abc_CommandPrintLevel( Abc_Frame_t * pAbc, int argc, char ** argv )
int fListNodes;
int fProfile;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -742,7 +746,7 @@ int Abc_CommandPrintSupport( Abc_Frame_t * pAbc, int argc, char ** argv )
extern Vec_Ptr_t * Sim_ComputeFunSupp( Abc_Ntk_t * pNtk, int fVerbose );
extern void Abc_NtkPrintStrSupports( Abc_Ntk_t * pNtk );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -817,7 +821,7 @@ int Abc_CommandPrintSymms( Abc_Frame_t * pAbc, int argc, char ** argv )
int fVerbose;
extern void Abc_NtkSymmetries( Abc_Ntk_t * pNtk, int fUseBdds, int fNaive, int fVerbose );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -873,6 +877,160 @@ usage:
return 1;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_CommandPrintUnate( Abc_Frame_t * pAbc, int argc, char ** argv )
{
FILE * pOut, * pErr;
Abc_Ntk_t * pNtk;
int c;
int fUseBdds;
int fUseNaive;
int fVerbose;
extern void Abc_NtkPrintUnate( Abc_Ntk_t * pNtk, int fUseBdds, int fUseNaive, int fVerbose );
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
// set defaults
fUseBdds = 1;
fUseNaive = 0;
fVerbose = 0;
util_getopt_reset();
while ( ( c = util_getopt( argc, argv, "bnvh" ) ) != EOF )
{
switch ( c )
{
case 'b':
fUseBdds ^= 1;
break;
case 'n':
fUseNaive ^= 1;
break;
case 'v':
fVerbose ^= 1;
break;
case 'h':
goto usage;
default:
goto usage;
}
}
if ( pNtk == NULL )
{
fprintf( pErr, "Empty network.\n" );
return 1;
}
if ( !Abc_NtkIsStrash(pNtk) )
{
fprintf( pErr, "This command works only for AIGs (run \"strash\").\n" );
return 1;
}
Abc_NtkPrintUnate( pNtk, fUseBdds, fUseNaive, fVerbose );
return 0;
usage:
fprintf( pErr, "usage: print_unate [-bnvh]\n" );
fprintf( pErr, "\t computes unate variables of the PO functions\n" );
fprintf( pErr, "\t-b : toggle BDD-based or SAT-based computations [default = %s].\n", fUseBdds? "BDD": "SAT" );
fprintf( pErr, "\t-n : toggle naive BDD-based computation [default = %s].\n", fUseNaive? "yes": "no" );
fprintf( pErr, "\t-v : enable verbose output [default = %s].\n", fVerbose? "yes": "no" );
fprintf( pErr, "\t-h : print the command usage\n");
return 1;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_CommandPrintAuto( Abc_Frame_t * pAbc, int argc, char ** argv )
{
FILE * pOut, * pErr;
Abc_Ntk_t * pNtk;
int c;
int Output;
int fNaive;
int fVerbose;
extern void Abc_NtkAutoPrint( Abc_Ntk_t * pNtk, int Output, int fNaive, int fVerbose );
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
// set defaults
Output = -1;
fNaive = 0;
fVerbose = 0;
util_getopt_reset();
while ( ( c = util_getopt( argc, argv, "Onvh" ) ) != EOF )
{
switch ( c )
{
case 'O':
if ( util_optind >= argc )
{
fprintf( pErr, "Command line switch \"-O\" should be followed by an integer.\n" );
goto usage;
}
Output = atoi(argv[util_optind]);
util_optind++;
if ( Output < 0 )
goto usage;
break;
case 'n':
fNaive ^= 1;
break;
case 'v':
fVerbose ^= 1;
break;
case 'h':
goto usage;
default:
goto usage;
}
}
if ( pNtk == NULL )
{
fprintf( pErr, "Empty network.\n" );
return 1;
}
if ( !Abc_NtkIsStrash(pNtk) )
{
fprintf( pErr, "This command works only for AIGs (run \"strash\").\n" );
return 1;
}
Abc_NtkAutoPrint( pNtk, Output, fNaive, fVerbose );
return 0;
usage:
fprintf( pErr, "usage: print_auto [-O num] [-nvh]\n" );
fprintf( pErr, "\t computes autosymmetries of the PO functions\n" );
fprintf( pErr, "\t-O num : (optional) the 0-based number of the output [default = all]\n");
fprintf( pErr, "\t-n : enable naive BDD-based computation [default = %s].\n", fNaive? "yes": "no" );
fprintf( pErr, "\t-v : enable verbose output [default = %s].\n", fVerbose? "yes": "no" );
fprintf( pErr, "\t-h : print the command usage\n");
return 1;
}
/**Function*************************************************************
Synopsis []
@ -894,7 +1052,7 @@ int Abc_CommandPrintKMap( Abc_Frame_t * pAbc, int argc, char ** argv )
extern void Abc_NodePrintKMap( Abc_Obj_t * pNode, int fUseRealNames );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -981,7 +1139,7 @@ int Abc_CommandPrintGates( Abc_Frame_t * pAbc, int argc, char ** argv )
extern void Abc_NtkPrintGates( Abc_Ntk_t * pNtk, int fUseLibrary );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -1044,7 +1202,7 @@ int Abc_CommandPrintSharing( Abc_Frame_t * pAbc, int argc, char ** argv )
extern void Abc_NtkPrintSharing( Abc_Ntk_t * pNtk );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -1106,7 +1264,7 @@ int Abc_CommandShowBdd( Abc_Frame_t * pAbc, int argc, char ** argv )
int c;
extern void Abc_NodeShowBdd( Abc_Obj_t * pNode );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -1194,7 +1352,7 @@ int Abc_CommandShowCut( Abc_Frame_t * pAbc, int argc, char ** argv )
int nConeSizeMax;
extern void Abc_NodeShowCut( Abc_Obj_t * pNode, int nNodeSizeMax, int nConeSizeMax );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -1295,7 +1453,7 @@ int Abc_CommandShowAig( Abc_Frame_t * pAbc, int argc, char ** argv )
extern void Abc_NtkShowAig( Abc_Ntk_t * pNtk );
extern void Abc_NtkShowMulti( Abc_Ntk_t * pNtk );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -1369,7 +1527,7 @@ int Abc_CommandShowNtk( Abc_Frame_t * pAbc, int argc, char ** argv )
int fGateNames;
extern void Abc_NtkShow( Abc_Ntk_t * pNtk, int fGateNames );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -1432,7 +1590,7 @@ int Abc_CommandCollapse( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Ntk_t * pNtk, * pNtkRes;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -1506,7 +1664,7 @@ int Abc_CommandStrash( Abc_Frame_t * pAbc, int argc, char ** argv )
int fAllNodes;
int fCleanup;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -1573,22 +1731,27 @@ int Abc_CommandBalance( Abc_Frame_t * pAbc, int argc, char ** argv )
FILE * pOut, * pErr;
Abc_Ntk_t * pNtk, * pNtkRes, * pNtkTemp;
int c;
int fDuplicate;
bool fDuplicate;
bool fSelective;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
// set defaults
fDuplicate = 0;
fSelective = 0;
util_getopt_reset();
while ( ( c = util_getopt( argc, argv, "dh" ) ) != EOF )
while ( ( c = util_getopt( argc, argv, "dsh" ) ) != EOF )
{
switch ( c )
{
case 'd':
fDuplicate ^= 1;
break;
case 's':
fSelective ^= 1;
break;
case 'h':
goto usage;
default:
@ -1610,7 +1773,7 @@ int Abc_CommandBalance( Abc_Frame_t * pAbc, int argc, char ** argv )
// get the new network
if ( Abc_NtkIsStrash(pNtk) )
{
pNtkRes = Abc_NtkBalance( pNtk, fDuplicate );
pNtkRes = Abc_NtkBalance( pNtk, fDuplicate, fSelective );
}
else
{
@ -1620,7 +1783,7 @@ int Abc_CommandBalance( Abc_Frame_t * pAbc, int argc, char ** argv )
fprintf( pErr, "Strashing before balancing has failed.\n" );
return 1;
}
pNtkRes = Abc_NtkBalance( pNtkTemp, fDuplicate );
pNtkRes = Abc_NtkBalance( pNtkTemp, fDuplicate, fSelective );
Abc_NtkDelete( pNtkTemp );
}
@ -1635,9 +1798,10 @@ int Abc_CommandBalance( Abc_Frame_t * pAbc, int argc, char ** argv )
return 0;
usage:
fprintf( pErr, "usage: balance [-dh]\n" );
fprintf( pErr, "usage: balance [-dsh]\n" );
fprintf( pErr, "\t transforms the current network into a well-balanced AIG\n" );
fprintf( pErr, "\t-d : toggle duplication of logic [default = %s]\n", fDuplicate? "yes": "no" );
fprintf( pErr, "\t-s : toggle duplication on the critical paths [default = %s]\n", fSelective? "yes": "no" );
fprintf( pErr, "\t-h : print the command usage\n");
return 1;
}
@ -1662,7 +1826,7 @@ int Abc_CommandRenode( Abc_Frame_t * pAbc, int argc, char ** argv )
int fMulti;
int fSimple;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -1769,7 +1933,7 @@ int Abc_CommandCleanup( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Ntk_t * pNtk;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -1824,7 +1988,7 @@ int Abc_CommandSweep( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Ntk_t * pNtk;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -1883,7 +2047,7 @@ int Abc_CommandFastExtract( Abc_Frame_t * pAbc, int argc, char ** argv )
extern bool Abc_NtkFastExtract( Abc_Ntk_t * pNtk, Fxu_Data_t * p );
extern void Abc_NtkFxuFreeInfo( Fxu_Data_t * p );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -2010,7 +2174,7 @@ int Abc_CommandDisjoint( Abc_Frame_t * pAbc, int argc, char ** argv )
extern Abc_Ntk_t * Abc_NtkDsdGlobal( Abc_Ntk_t * pNtk, bool fVerbose, bool fPrint, bool fShort );
extern int Abc_NtkDsdLocal( Abc_Ntk_t * pNtk, bool fVerbose, bool fRecursive );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -2136,7 +2300,7 @@ int Abc_CommandRewrite( Abc_Frame_t * pAbc, int argc, char ** argv )
extern void Rwr_Precompute();
extern int Abc_NtkRewrite( Abc_Ntk_t * pNtk, int fUpdateLevel, int fUseZeros, int fVerbose );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -2233,7 +2397,7 @@ int Abc_CommandRefactor( Abc_Frame_t * pAbc, int argc, char ** argv )
bool fVerbose;
extern int Abc_NtkRefactor( Abc_Ntk_t * pNtk, int nNodeSizeMax, int nConeSizeMax, bool fUpdateLevel, bool fUseZeros, bool fUseDcs, bool fVerbose );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -2351,7 +2515,7 @@ int Abc_CommandLogic( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Ntk_t * pNtk, * pNtkRes;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -2420,7 +2584,7 @@ int Abc_CommandMiter( Abc_Frame_t * pAbc, int argc, char ** argv )
int fCheck;
int fComb;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -2491,7 +2655,7 @@ int Abc_CommandFrames( Abc_Frame_t * pAbc, int argc, char ** argv )
int nFrames;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -2575,7 +2739,7 @@ int Abc_CommandSop( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Ntk_t * pNtk;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -2635,7 +2799,7 @@ int Abc_CommandBdd( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Ntk_t * pNtk;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -2696,7 +2860,7 @@ int Abc_CommandReorder( Abc_Frame_t * pAbc, int argc, char ** argv )
int fVerbose;
extern void Abc_NtkBddReorder( Abc_Ntk_t * pNtk, int fVerbose );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -2757,7 +2921,7 @@ int Abc_CommandMuxes( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Ntk_t * pNtk, * pNtkRes;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -2825,7 +2989,7 @@ int Abc_CommandSat( Abc_Frame_t * pAbc, int argc, char ** argv )
int fVerbose;
int nSeconds;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -2887,7 +3051,7 @@ int Abc_CommandSat( Abc_Frame_t * pAbc, int argc, char ** argv )
*/
if ( Abc_NtkIsStrash(pNtk) )
{
RetValue = Abc_NtkMiterSat2( pNtk, nSeconds, fVerbose );
RetValue = Abc_NtkMiterSat( pNtk, nSeconds, fVerbose );
if ( RetValue == -1 )
printf( "The miter is UNDECIDED (SAT solver timed out).\n" );
else if ( RetValue == 0 )
@ -2899,7 +3063,7 @@ int Abc_CommandSat( Abc_Frame_t * pAbc, int argc, char ** argv )
{
Abc_Ntk_t * pTemp;
pTemp = Abc_NtkStrash( pNtk, 0, 0 );
RetValue = Abc_NtkMiterSat2( pTemp, nSeconds, fVerbose );
RetValue = Abc_NtkMiterSat( pTemp, nSeconds, fVerbose );
if ( RetValue == -1 )
printf( "The miter is UNDECIDED (SAT solver timed out).\n" );
else if ( RetValue == 0 )
@ -2939,7 +3103,7 @@ int Abc_CommandExtSeqDcs( Abc_Frame_t * pAbc, int argc, char ** argv )
int fVerbose;
extern int Abc_NtkExtractSequentialDcs( Abc_Ntk_t * pNet, bool fVerbose );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -3010,7 +3174,7 @@ int Abc_CommandOneOutput( Abc_Frame_t * pAbc, int argc, char ** argv )
int fUseAllCis;
int Output;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -3122,7 +3286,7 @@ int Abc_CommandOneNode( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Obj_t * pNode;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -3202,7 +3366,7 @@ int Abc_CommandShortNames( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Ntk_t * pNtk;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -3251,7 +3415,7 @@ int Abc_CommandExdcFree( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Ntk_t * pNtk, * pNtkRes;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -3311,7 +3475,7 @@ int Abc_CommandExdcGet( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Ntk_t * pNtk, * pNtkRes;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -3369,7 +3533,7 @@ int Abc_CommandExdcSet( Abc_Frame_t * pAbc, int argc, char ** argv )
char * FileName;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -3461,7 +3625,7 @@ int Abc_CommandCut( Abc_Frame_t * pAbc, int argc, char ** argv )
extern Cut_Man_t * Abc_NtkCuts( Abc_Ntk_t * pNtk, Cut_Params_t * pParams );
extern void Abc_NtkCutsOracle( Abc_Ntk_t * pNtk, Cut_Oracle_t * pCutOracle );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -3591,7 +3755,7 @@ int Abc_CommandScut( Abc_Frame_t * pAbc, int argc, char ** argv )
int c;
extern Cut_Man_t * Abc_NtkSeqCuts( Abc_Ntk_t * pNtk, Cut_Params_t * pParams );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -3696,7 +3860,7 @@ int Abc_CommandXyz( Abc_Frame_t * pAbc, int argc, char ** argv )
int nFaninMax;
extern Abc_Ntk_t * Abc_NtkXyz( Abc_Ntk_t * pNtk, int nFaninMax, bool fUseEsop, bool fUseSop, bool fUseInvs, bool fVerbose );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -3784,9 +3948,9 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
FILE * pOut, * pErr;
Abc_Ntk_t * pNtk, * pNtkRes;
int c;
extern Abc_Ntk_t * Abc_NtkNewAig( Abc_Ntk_t * pNtk );
// extern Abc_Ntk_t * Abc_NtkNewAig( Abc_Ntk_t * pNtk );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -3819,7 +3983,9 @@ int Abc_CommandTest( Abc_Frame_t * pAbc, int argc, char ** argv )
// printf( "This command is currently not used.\n" );
// run the command
// pNtkRes = Abc_NtkMiterForCofactors( pNtk, 0, 0, -1 );
pNtkRes = Abc_NtkNewAig( pNtk );
// pNtkRes = Abc_NtkNewAig( pNtk );
pNtkRes = NULL;
if ( pNtkRes == NULL )
{
fprintf( pErr, "Command has failed.\n" );
@ -3859,7 +4025,7 @@ int Abc_CommandFraig( Abc_Frame_t * pAbc, int argc, char ** argv )
int fExdc;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -4017,7 +4183,7 @@ int Abc_CommandFraigTrust( Abc_Frame_t * pAbc, int argc, char ** argv )
int c;
int fDuplicate;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -4081,7 +4247,7 @@ int Abc_CommandFraigStore( Abc_Frame_t * pAbc, int argc, char ** argv )
int c;
int fDuplicate;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -4142,7 +4308,7 @@ int Abc_CommandFraigRestore( Abc_Frame_t * pAbc, int argc, char ** argv )
int c;
int fDuplicate;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -4206,7 +4372,7 @@ int Abc_CommandFraigClean( Abc_Frame_t * pAbc, int argc, char ** argv )
int c;
int fDuplicate;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -4258,7 +4424,7 @@ int Abc_CommandFraigSweep( Abc_Frame_t * pAbc, int argc, char ** argv )
int fVerbose;
extern bool Abc_NtkFraigSweep( Abc_Ntk_t * pNtk, int fUseInv, int fExdc, int fVerbose );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -4345,7 +4511,7 @@ int Abc_CommandMap( Abc_Frame_t * pAbc, int argc, char ** argv )
extern Abc_Ntk_t * Abc_NtkMap( Abc_Ntk_t * pNtk, double DelayTarget, int fRecovery, int fSwitching, int fVerbose );
extern bool Abc_NtkFraigSweep( Abc_Ntk_t * pNtk, int fUseInv, int fExdc, int fVerbose );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -4410,7 +4576,7 @@ int Abc_CommandMap( Abc_Frame_t * pAbc, int argc, char ** argv )
fprintf( pErr, "Strashing before mapping has failed.\n" );
return 1;
}
pNtk = Abc_NtkBalance( pNtkRes = pNtk, 0 );
pNtk = Abc_NtkBalance( pNtkRes = pNtk, 0, 0 );
Abc_NtkDelete( pNtkRes );
if ( pNtk == NULL )
{
@ -4481,7 +4647,7 @@ int Abc_CommandUnmap( Abc_Frame_t * pAbc, int argc, char ** argv )
int c;
extern int Abc_NtkUnmap( Abc_Ntk_t * pNtk );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -4542,7 +4708,7 @@ int Abc_CommandAttach( Abc_Frame_t * pAbc, int argc, char ** argv )
int c;
extern int Abc_NtkUnmap( Abc_Ntk_t * pNtk );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -4605,7 +4771,7 @@ int Abc_CommandSuperChoice( Abc_Frame_t * pAbc, int argc, char ** argv )
int c;
extern Abc_Ntk_t * Abc_NtkSuperChoice( Abc_Ntk_t * pNtk );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -4678,7 +4844,7 @@ int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
extern Abc_Ntk_t * Abc_NtkFpga( Abc_Ntk_t * pNtk, float DelayTarget, int fRecovery, int fSwitching, int fVerbose );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -4740,7 +4906,7 @@ int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
fprintf( pErr, "Strashing before FPGA mapping has failed.\n" );
return 1;
}
pNtk = Abc_NtkBalance( pNtkRes = pNtk, 0 );
pNtk = Abc_NtkBalance( pNtkRes = pNtk, 0, 0 );
Abc_NtkDelete( pNtkRes );
if ( pNtk == NULL )
{
@ -4806,7 +4972,7 @@ int Abc_CommandPga( Abc_Frame_t * pAbc, int argc, char ** argv )
int c;
extern Abc_Ntk_t * Abc_NtkPga( Pga_Params_t * pParams );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -4863,7 +5029,7 @@ int Abc_CommandPga( Abc_Frame_t * pAbc, int argc, char ** argv )
fprintf( pErr, "Strashing before FPGA mapping has failed.\n" );
return 1;
}
pNtk = Abc_NtkBalance( pNtkRes = pNtk, 0 );
pNtk = Abc_NtkBalance( pNtkRes = pNtk, 0, 0 );
Abc_NtkDelete( pNtkRes );
if ( pNtk == NULL )
{
@ -4931,7 +5097,7 @@ int Abc_CommandInit( Abc_Frame_t * pAbc, int argc, char ** argv )
int fRandom;
int fDontCare;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -5039,7 +5205,7 @@ int Abc_CommandPipe( Abc_Frame_t * pAbc, int argc, char ** argv )
int nLatches;
extern void Abc_NtkLatchPipe( Abc_Ntk_t * pNtk, int nLatches );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -5115,7 +5281,7 @@ int Abc_CommandSeq( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Ntk_t * pNtk, * pNtkRes;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -5192,7 +5358,7 @@ int Abc_CommandUnseq( Abc_Frame_t * pAbc, int argc, char ** argv )
int c;
int fShare;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -5269,7 +5435,7 @@ int Abc_CommandRetime( Abc_Frame_t * pAbc, int argc, char ** argv )
int fInitial;
int fVerbose;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -5395,7 +5561,7 @@ int Abc_CommandSeqFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
int c, nMaxIters;
int fVerbose;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -5459,7 +5625,7 @@ int Abc_CommandSeqFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
return 1;
}
pNtkNew = Abc_NtkBalance( pNtkRes = pNtkNew, 0 );
pNtkNew = Abc_NtkBalance( pNtkRes = pNtkNew, 0, 0 );
Abc_NtkDelete( pNtkRes );
if ( pNtkNew == NULL )
{
@ -5519,7 +5685,7 @@ int Abc_CommandSeqMap( Abc_Frame_t * pAbc, int argc, char ** argv )
int c, nMaxIters;
int fVerbose;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -5583,7 +5749,7 @@ int Abc_CommandSeqMap( Abc_Frame_t * pAbc, int argc, char ** argv )
return 1;
}
pNtkNew = Abc_NtkBalance( pNtkRes = pNtkNew, 0 );
pNtkNew = Abc_NtkBalance( pNtkRes = pNtkNew, 0, 0 );
Abc_NtkDelete( pNtkRes );
if ( pNtkNew == NULL )
{
@ -5649,7 +5815,7 @@ int Abc_CommandSeqSweep( Abc_Frame_t * pAbc, int argc, char ** argv )
extern Abc_Ntk_t * Abc_NtkVanEijk( Abc_Ntk_t * pNtk, int nFrames, int fExdc, int fVerbose );
extern Abc_Ntk_t * Abc_NtkVanImp( Abc_Ntk_t * pNtk, int nFrames, int fExdc, int fVerbose );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -5756,7 +5922,7 @@ int Abc_CommandSeqCleanup( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Ntk_t * pNtk;
int c;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -5822,7 +5988,7 @@ int Abc_CommandCec( Abc_Frame_t * pAbc, int argc, char ** argv )
extern void Abc_NtkCecFraig( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int nSeconds, int fVerbose );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -5914,7 +6080,7 @@ int Abc_CommandSec( Abc_Frame_t * pAbc, int argc, char ** argv )
extern void Abc_NtkSecFraig( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int nSeconds, int nFrames, int fVerbose );
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);

229
src/base/abci/abcAuto.c Normal file
View File

@ -0,0 +1,229 @@
/**CFile****************************************************************
FileName [abcAuto.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Network and node package.]
Synopsis [Computation of autosymmetries.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: abcAuto.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "abc.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
static void Abc_NtkAutoPrintAll( DdManager * dd, int nInputs, DdNode * pbOutputs[], int nOutputs, char * pInputNames[], char * pOutputNames[], int fNaive );
static void Abc_NtkAutoPrintOne( DdManager * dd, int nInputs, DdNode * pbOutputs[], int Output, char * pInputNames[], char * pOutputNames[], int fNaive );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkAutoPrint( Abc_Ntk_t * pNtk, int Output, int fNaive, int fVerbose )
{
DdManager * dd; // the BDD manager used to hold shared BDDs
DdNode ** pbGlobal; // temporary storage for global BDDs
char ** pInputNames; // pointers to the CI names
char ** pOutputNames; // pointers to the CO names
int nOutputs, nInputs, i;
// compute the global BDDs
if ( Abc_NtkGlobalBdds(pNtk, 0) == NULL )
return;
// get information about the network
nInputs = Abc_NtkCiNum(pNtk);
nOutputs = Abc_NtkCoNum(pNtk);
dd = pNtk->pManGlob;
pbGlobal = (DdNode **)Vec_PtrArray( pNtk->vFuncsGlob );
// get the network names
pInputNames = Abc_NtkCollectCioNames( pNtk, 0 );
pOutputNames = Abc_NtkCollectCioNames( pNtk, 1 );
// print the size of the BDDs
if ( fVerbose )
printf( "The shared BDD size is %d nodes.\n", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
// allocate additional variables
for ( i = 0; i < nInputs; i++ )
Cudd_bddNewVar( dd );
assert( Cudd_ReadSize(dd) == 2 * nInputs );
// create ZDD variables in the manager
Cudd_zddVarsFromBddVars( dd, 2 );
// perform the analysis of the primary output functions for auto-symmetry
if ( Output == -1 )
Abc_NtkAutoPrintAll( dd, nInputs, pbGlobal, nOutputs, pInputNames, pOutputNames, fNaive );
else
Abc_NtkAutoPrintOne( dd, nInputs, pbGlobal, Output, pInputNames, pOutputNames, fNaive );
// deref the PO functions
Abc_NtkFreeGlobalBdds( pNtk );
// stop the global BDD manager
Extra_StopManager( pNtk->pManGlob );
pNtk->pManGlob = NULL;
free( pInputNames );
free( pOutputNames );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkAutoPrintAll( DdManager * dd, int nInputs, DdNode * pbOutputs[], int nOutputs, char * pInputNames[], char * pOutputNames[], int fNaive )
{
DdNode * bSpace1, * bSpace2, * bCanVars, * bReduced, * zEquations;
double nMints;
int nSupp, SigCounter, o;
int nAutos;
int nAutoSyms;
int nAutoSymsMax;
int nAutoSymsMaxSupp;
int nAutoSymOuts;
int nSuppSizeMax;
int clk;
nAutoSymOuts = 0;
nAutoSyms = 0;
nAutoSymsMax = 0;
nAutoSymsMaxSupp = 0;
nSuppSizeMax = 0;
clk = clock();
SigCounter = 0;
for ( o = 0; o < nOutputs; o++ )
{
bSpace1 = Extra_bddSpaceFromFunctionFast( dd, pbOutputs[o] ); Cudd_Ref( bSpace1 );
// bSpace1 = Extra_bddSpaceFromFunction( dd, pbOutputs[o], pbOutputs[o] ); Cudd_Ref( bSpace1 );
bCanVars = Extra_bddSpaceCanonVars( dd, bSpace1 ); Cudd_Ref( bCanVars );
bReduced = Extra_bddSpaceReduce( dd, pbOutputs[o], bCanVars ); Cudd_Ref( bReduced );
zEquations = Extra_bddSpaceEquations( dd, bSpace1 ); Cudd_Ref( zEquations );
nSupp = Cudd_SupportSize( dd, bSpace1 );
nMints = Cudd_CountMinterm( dd, bSpace1, nSupp );
nAutos = Extra_Base2LogDouble(nMints);
printf( "Output #%3d: Inputs = %2d. AutoK = %2d.\n", o, nSupp, nAutos );
if ( nAutos > 0 )
{
nAutoSymOuts++;
nAutoSyms += nAutos;
if ( nAutoSymsMax < nAutos )
{
nAutoSymsMax = nAutos;
nAutoSymsMaxSupp = nSupp;
}
}
if ( nSuppSizeMax < nSupp )
nSuppSizeMax = nSupp;
//PRB( dd, bCanVars );
//PRB( dd, bReduced );
//Cudd_PrintMinterm( dd, bReduced );
//printf( "The equations are:\n" );
//Cudd_zddPrintCover( dd, zEquations );
//printf( "\n" );
//fflush( stdout );
bSpace2 = Extra_bddSpaceFromMatrixPos( dd, zEquations ); Cudd_Ref( bSpace2 );
//PRB( dd, bSpace1 );
//PRB( dd, bSpace2 );
if ( bSpace1 != bSpace2 )
printf( "Spaces are NOT EQUAL!\n" );
// else
// printf( "Spaces are equal.\n" );
Cudd_RecursiveDeref( dd, bSpace1 );
Cudd_RecursiveDeref( dd, bSpace2 );
Cudd_RecursiveDeref( dd, bCanVars );
Cudd_RecursiveDeref( dd, bReduced );
Cudd_RecursiveDerefZdd( dd, zEquations );
}
printf( "The cumulative statistics for all outputs:\n" );
printf( "Ins=%3d ", nInputs );
printf( "InMax=%3d ", nSuppSizeMax );
printf( "Outs=%3d ", nOutputs );
printf( "Auto=%3d ", nAutoSymOuts );
printf( "SumK=%3d ", nAutoSyms );
printf( "KMax=%2d ", nAutoSymsMax );
printf( "Supp=%3d ", nAutoSymsMaxSupp );
printf( "Time=%4.2f ", (float)(clock() - clk)/(float)(CLOCKS_PER_SEC) );
printf( "\n" );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkAutoPrintOne( DdManager * dd, int nInputs, DdNode * pbOutputs[], int Output, char * pInputNames[], char * pOutputNames[], int fNaive )
{
DdNode * bSpace1, * bCanVars, * bReduced, * zEquations;
double nMints;
int nSupp, SigCounter;
int nAutos;
SigCounter = 0;
bSpace1 = Extra_bddSpaceFromFunctionFast( dd, pbOutputs[Output] ); Cudd_Ref( bSpace1 );
// bSpace1 = Extra_bddSpaceFromFunction( dd, pbOutputs[Output], pbOutputs[Output] ); Cudd_Ref( bSpace1 );
bCanVars = Extra_bddSpaceCanonVars( dd, bSpace1 ); Cudd_Ref( bCanVars );
bReduced = Extra_bddSpaceReduce( dd, pbOutputs[Output], bCanVars ); Cudd_Ref( bReduced );
zEquations = Extra_bddSpaceEquations( dd, bSpace1 ); Cudd_Ref( zEquations );
nSupp = Cudd_SupportSize( dd, bSpace1 );
nMints = Cudd_CountMinterm( dd, bSpace1, nSupp );
nAutos = Extra_Base2LogDouble(nMints);
printf( "Output #%3d: Inputs = %2d. AutoK = %2d.\n", Output, nSupp, nAutos );
Cudd_RecursiveDeref( dd, bSpace1 );
Cudd_RecursiveDeref( dd, bCanVars );
Cudd_RecursiveDeref( dd, bReduced );
Cudd_RecursiveDerefZdd( dd, zEquations );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

71
src/base/abci/abcBalance.c
View File

@ -24,10 +24,11 @@
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
static void Abc_NtkBalancePerform( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkAig, bool fDuplicate );
static Abc_Obj_t * Abc_NodeBalance_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNode, Vec_Vec_t * vStorage, int Level, bool fDuplicate );
static Vec_Ptr_t * Abc_NodeBalanceCone( Abc_Obj_t * pNode, Vec_Vec_t * vSuper, int Level, int fDuplicate );
static int Abc_NodeBalanceCone_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vSuper, bool fFirst, bool fDuplicate );
static void Abc_NtkBalancePerform( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkAig, bool fDuplicate, bool fSelective );
static Abc_Obj_t * Abc_NodeBalance_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNode, Vec_Vec_t * vStorage, int Level, bool fDuplicate, bool fSelective );
static Vec_Ptr_t * Abc_NodeBalanceCone( Abc_Obj_t * pNode, Vec_Vec_t * vSuper, int Level, int fDuplicate, bool fSelective );
static int Abc_NodeBalanceCone_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vSuper, bool fFirst, bool fDuplicate, bool fSelective );
static void Abc_NtkMarkCriticalNodes( Abc_Ntk_t * pNtk );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
@ -44,14 +45,26 @@ static int Abc_NodeBalanceCone_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vSupe
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkBalance( Abc_Ntk_t * pNtk, bool fDuplicate )
Abc_Ntk_t * Abc_NtkBalance( Abc_Ntk_t * pNtk, bool fDuplicate, bool fSelective )
{
Abc_Ntk_t * pNtkAig;
assert( Abc_NtkIsStrash(pNtk) );
// compute the required times
if ( fSelective )
{
Abc_NtkStartReverseLevels( pNtk );
Abc_NtkMarkCriticalNodes( pNtk );
}
// perform balancing
pNtkAig = Abc_NtkStartFrom( pNtk, ABC_NTK_STRASH, ABC_FUNC_AIG );
Abc_NtkBalancePerform( pNtk, pNtkAig, fDuplicate );
Abc_NtkBalancePerform( pNtk, pNtkAig, fDuplicate, fSelective );
Abc_NtkFinalize( pNtk, pNtkAig );
// undo the required times
if ( fSelective )
{
Abc_NtkStopReverseLevels( pNtk );
Abc_NtkCleanMarkA( pNtk );
}
if ( pNtk->pExdc )
pNtkAig->pExdc = Abc_NtkDup( pNtk->pExdc );
// make sure everything is okay
@ -75,7 +88,7 @@ Abc_Ntk_t * Abc_NtkBalance( Abc_Ntk_t * pNtk, bool fDuplicate )
SeeAlso []
***********************************************************************/
void Abc_NtkBalancePerform( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkAig, bool fDuplicate )
void Abc_NtkBalancePerform( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkAig, bool fDuplicate, bool fSelective )
{
int fCheck = 1;
ProgressBar * pProgress;
@ -94,7 +107,7 @@ void Abc_NtkBalancePerform( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkAig, bool fDuplica
Extra_ProgressBarUpdate( pProgress, i, NULL );
// strash the driver node
pDriver = Abc_ObjFanin0(pNode);
Abc_NodeBalance_rec( pNtkAig, pDriver, vStorage, 0, fDuplicate );
Abc_NodeBalance_rec( pNtkAig, pDriver, vStorage, 0, fDuplicate, fSelective );
}
Extra_ProgressBarStop( pProgress );
Vec_VecFree( vStorage );
@ -147,7 +160,7 @@ void Abc_NodeBalanceRandomize( Vec_Ptr_t * vSuper )
SeeAlso []
***********************************************************************/
Abc_Obj_t * Abc_NodeBalance_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld, Vec_Vec_t * vStorage, int Level, bool fDuplicate )
Abc_Obj_t * Abc_NodeBalance_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld, Vec_Vec_t * vStorage, int Level, bool fDuplicate, bool fSelective )
{
Abc_Aig_t * pMan = pNtkNew->pManFunc;
Abc_Obj_t * pNodeNew, * pNode1, * pNode2;
@ -159,7 +172,7 @@ Abc_Obj_t * Abc_NodeBalance_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld, Vec_
return pNodeOld->pCopy;
assert( Abc_ObjIsNode(pNodeOld) );
// get the implication supergate
vSuper = Abc_NodeBalanceCone( pNodeOld, vStorage, Level, fDuplicate );
vSuper = Abc_NodeBalanceCone( pNodeOld, vStorage, Level, fDuplicate, fSelective );
if ( vSuper->nSize == 0 )
{ // it means that the supergate contains two nodes in the opposite polarity
pNodeOld->pCopy = Abc_ObjNot(Abc_NtkConst1(pNtkNew));
@ -168,7 +181,7 @@ Abc_Obj_t * Abc_NodeBalance_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld, Vec_
// for each old node, derive the new well-balanced node
for ( i = 0; i < vSuper->nSize; i++ )
{
pNodeNew = Abc_NodeBalance_rec( pNtkNew, Abc_ObjRegular(vSuper->pArray[i]), vStorage, Level + 1, fDuplicate );
pNodeNew = Abc_NodeBalance_rec( pNtkNew, Abc_ObjRegular(vSuper->pArray[i]), vStorage, Level + 1, fDuplicate, fSelective );
vSuper->pArray[i] = Abc_ObjNotCond( pNodeNew, Abc_ObjIsComplement(vSuper->pArray[i]) );
}
if ( vSuper->nSize < 2 )
@ -207,7 +220,7 @@ Abc_Obj_t * Abc_NodeBalance_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld, Vec_
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Abc_NodeBalanceCone( Abc_Obj_t * pNode, Vec_Vec_t * vStorage, int Level, int fDuplicate )
Vec_Ptr_t * Abc_NodeBalanceCone( Abc_Obj_t * pNode, Vec_Vec_t * vStorage, int Level, int fDuplicate, bool fSelective )
{
Vec_Ptr_t * vNodes;
int RetValue, i;
@ -219,7 +232,7 @@ Vec_Ptr_t * Abc_NodeBalanceCone( Abc_Obj_t * pNode, Vec_Vec_t * vStorage, int Le
vNodes = Vec_VecEntry( vStorage, Level );
Vec_PtrClear( vNodes );
// collect the nodes in the implication supergate
RetValue = Abc_NodeBalanceCone_rec( pNode, vNodes, 1, fDuplicate );
RetValue = Abc_NodeBalanceCone_rec( pNode, vNodes, 1, fDuplicate, fSelective );
assert( vNodes->nSize > 1 );
// unmark the visited nodes
for ( i = 0; i < vNodes->nSize; i++ )
@ -245,7 +258,7 @@ Vec_Ptr_t * Abc_NodeBalanceCone( Abc_Obj_t * pNode, Vec_Vec_t * vStorage, int Le
SeeAlso []
***********************************************************************/
int Abc_NodeBalanceCone_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vSuper, bool fFirst, bool fDuplicate )
int Abc_NodeBalanceCone_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vSuper, bool fFirst, bool fDuplicate, bool fSelective )
{
int RetValue1, RetValue2, i;
// check if the node is visited
@ -263,7 +276,7 @@ int Abc_NodeBalanceCone_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vSuper, bool fFirst,
return 0;
}
// if the new node is complemented or a PI, another gate begins
if ( !fFirst && (Abc_ObjIsComplement(pNode) || !Abc_ObjIsNode(pNode) || !fDuplicate && (Abc_ObjFanoutNum(pNode) > 1)) )
if ( !fFirst && (Abc_ObjIsComplement(pNode) || !Abc_ObjIsNode(pNode) || !fDuplicate && !fSelective && (Abc_ObjFanoutNum(pNode) > 1)) )
{
Vec_PtrPush( vSuper, pNode );
Abc_ObjRegular(pNode)->fMarkB = 1;
@ -272,8 +285,8 @@ int Abc_NodeBalanceCone_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vSuper, bool fFirst,
assert( !Abc_ObjIsComplement(pNode) );
assert( Abc_ObjIsNode(pNode) );
// go through the branches
RetValue1 = Abc_NodeBalanceCone_rec( Abc_ObjChild0(pNode), vSuper, 0, fDuplicate );
RetValue2 = Abc_NodeBalanceCone_rec( Abc_ObjChild1(pNode), vSuper, 0, fDuplicate );
RetValue1 = Abc_NodeBalanceCone_rec( Abc_ObjChild0(pNode), vSuper, 0, fDuplicate, fSelective );
RetValue2 = Abc_NodeBalanceCone_rec( Abc_ObjChild1(pNode), vSuper, 0, fDuplicate, fSelective );
if ( RetValue1 == -1 || RetValue2 == -1 )
return -1;
// return 1 if at least one branch has a duplicate
@ -315,7 +328,7 @@ Vec_Ptr_t * Abc_NodeFindCone_rec( Abc_Obj_t * pNode )
else
{
// collect the nodes in the implication supergate
RetValue = Abc_NodeBalanceCone_rec( pNode, vNodes, 1, 1 );
RetValue = Abc_NodeBalanceCone_rec( pNode, vNodes, 1, 1, 0 );
assert( vNodes->nSize > 1 );
// unmark the visited nodes
Vec_PtrForEachEntry( vNodes, pNode, i )
@ -442,6 +455,28 @@ void Abc_NtkBalanceLevel( Abc_Ntk_t * pNtk )
}
/**Function*************************************************************
Synopsis [Marks the nodes on the critical and near critical paths.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkMarkCriticalNodes( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode;
int i, Counter = 0;
Abc_NtkForEachNode( pNtk, pNode, i )
if ( Abc_NodeReadRequiredLevel(pNode) - pNode->Level <= 1 )
pNode->fMarkA = 1, Counter++;
printf( "The number of nodes on the critical paths = %6d (%5.2f %%)\n", Counter, 100.0 * Counter / Abc_NtkNodeNum(pNtk) );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

1
src/base/abci/abcDsd.c
View File

@ -172,6 +172,7 @@ void Abc_NtkDsdConstruct( Dsd_Manager_t * pManDsd, Abc_Ntk_t * pNtk, Abc_Ntk_t *
int i, nNodesDsd;
// save the CI nodes in the DSD nodes
Dsd_NodeSetMark( Dsd_ManagerReadConst1(pManDsd), (int)Abc_NtkConst1(pNtk)->pCopy );
Abc_NtkForEachCi( pNtk, pNode, i )
{
pNodeDsd = Dsd_ManagerReadInput( pManDsd, i );

2
src/base/abci/abcMap.c
View File

@ -105,7 +105,7 @@ clk = clock();
Map_ManFree( pMan );
return NULL;
}
// Map_ManPrintStatsToFile( pNtk->pSpec, Map_ManReadAreaFinal(pMan), Map_ManReadRequiredGlo(pMan), clock()-clk );
Map_ManPrintStatsToFile( pNtk->pSpec, Map_ManReadAreaFinal(pMan), Map_ManReadRequiredGlo(pMan), clock()-clk );
// reconstruct the network after mapping
pNtkNew = Abc_NtkFromMap( pMan, pNtk );

2
src/base/abci/abcRenode.c
View File

@ -173,6 +173,8 @@ Abc_Obj_t * Abc_NtkRenode_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld )
assert( !Abc_NodeIsConst(pNodeOld) );
assert( pNodeOld->fMarkA );
//printf( "%d ", Abc_NodeMffcSizeSupp(pNodeOld) );
// collect the renoding cone
vCone = Vec_PtrAlloc( 10 );
Abc_NtkRenodeCone( pNodeOld, vCone );

31
src/base/abci/abcSat.c
View File

@ -29,6 +29,8 @@ static int Abc_NodeAddClausesTop( solver * pSat, Abc_Obj_t * pNode, Vec_Int_t *
static solver * Abc_NtkMiterSatCreate2( Abc_Ntk_t * pNtk );
static Vec_Int_t * Abc_NtkGetCiSatVarNums( Abc_Ntk_t * pNtk );
static nMuxes;
////////////////////////////////////////////////////////////////////////
@ -46,7 +48,7 @@ static nMuxes;
SeeAlso []
***********************************************************************/
int Abc_NtkMiterSat( Abc_Ntk_t * pNtk, int nSeconds, int fVerbose )
int Abc_NtkMiterSat_OldAndRusty( Abc_Ntk_t * pNtk, int nSeconds, int fVerbose )
{
solver * pSat;
lbool status;
@ -317,7 +319,7 @@ int Abc_NodeAddClausesTop( solver * pSat, Abc_Obj_t * pNode, Vec_Int_t * vVars )
SeeAlso []
***********************************************************************/
int Abc_NtkMiterSat2( Abc_Ntk_t * pNtk, int nSeconds, int fVerbose )
int Abc_NtkMiterSat( Abc_Ntk_t * pNtk, int nSeconds, int fVerbose )
{
solver * pSat;
lbool status;
@ -376,7 +378,8 @@ int Abc_NtkMiterSat2( Abc_Ntk_t * pNtk, int nSeconds, int fVerbose )
// if the problem is SAT, get the counterexample
if ( status == l_True )
{
Vec_Int_t * vCiIds = Abc_NtkGetCiIds( pNtk );
// Vec_Int_t * vCiIds = Abc_NtkGetCiIds( pNtk );
Vec_Int_t * vCiIds = Abc_NtkGetCiSatVarNums( pNtk );
pNtk->pModel = solver_get_model( pSat, vCiIds->pArray, vCiIds->nSize );
Vec_IntFree( vCiIds );
}
@ -385,6 +388,28 @@ int Abc_NtkMiterSat2( Abc_Ntk_t * pNtk, int nSeconds, int fVerbose )
return RetValue;
}
/**Function*************************************************************
Synopsis [Returns the array of CI IDs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Abc_NtkGetCiSatVarNums( Abc_Ntk_t * pNtk )
{
Vec_Int_t * vCiIds;
Abc_Obj_t * pObj;
int i;
vCiIds = Vec_IntAlloc( Abc_NtkCiNum(pNtk) );
Abc_NtkForEachCi( pNtk, pObj, i )
Vec_IntPush( vCiIds, (int)pObj->pCopy );
return vCiIds;
}

150
src/base/abci/abcUnate.c Normal file
View File

@ -0,0 +1,150 @@
/**CFile****************************************************************
FileName [abcUnate.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Network and node package.]
Synopsis []
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: abcUnate.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "abc.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
static void Abc_NtkPrintUnateBdd( Abc_Ntk_t * pNtk, int fUseNaive, int fVerbose );
static void Abc_NtkPrintUnateSat( Abc_Ntk_t * pNtk, int fVerbose );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Detects unate variables of the multi-output function.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkPrintUnate( Abc_Ntk_t * pNtk, int fUseBdds, int fUseNaive, int fVerbose )
{
if ( fUseBdds || fUseNaive )
Abc_NtkPrintUnateBdd( pNtk, fUseNaive, fVerbose );
else
Abc_NtkPrintUnateSat( pNtk, fVerbose );
}
/**Function*************************************************************
Synopsis [Detects unate variables using BDDs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkPrintUnateBdd( Abc_Ntk_t * pNtk, int fUseNaive, int fVerbose )
{
Abc_Obj_t * pNode;
Extra_UnateInfo_t * p;
DdManager * dd; // the BDD manager used to hold shared BDDs
DdNode ** pbGlobal; // temporary storage for global BDDs
int TotalSupps = 0;
int TotalUnate = 0;
int i, clk = clock();
int clkBdd, clkUnate;
// compute the global BDDs
if ( Abc_NtkGlobalBdds(pNtk, 0) == NULL )
return;
clkBdd = clock() - clk;
// get information about the network
dd = pNtk->pManGlob;
pbGlobal = (DdNode **)Vec_PtrArray( pNtk->vFuncsGlob );
// print the size of the BDDs
printf( "The shared BDD size is %d nodes.\n", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
// perform naive BDD-based computation
if ( fUseNaive )
{
Abc_NtkForEachCo( pNtk, pNode, i )
{
p = Extra_UnateComputeSlow( dd, pbGlobal[i] );
if ( fVerbose )
Extra_UnateInfoPrint( p );
TotalSupps += p->nVars;
TotalUnate += p->nUnate;
Extra_UnateInfoDissolve( p );
}
}
// perform smart BDD-based computation
else
{
// create ZDD variables in the manager
Cudd_zddVarsFromBddVars( dd, 2 );
Abc_NtkForEachCo( pNtk, pNode, i )
{
p = Extra_UnateComputeFast( dd, pbGlobal[i] );
if ( fVerbose )
Extra_UnateInfoPrint( p );
TotalSupps += p->nVars;
TotalUnate += p->nUnate;
Extra_UnateInfoDissolve( p );
}
}
clkUnate = clock() - clk - clkBdd;
// print stats
printf( "Ins/Outs = %4d/%4d. Total supp = %5d. Total unate = %5d.\n",
Abc_NtkCiNum(pNtk), Abc_NtkCoNum(pNtk), TotalSupps, TotalUnate );
PRT( "Glob BDDs", clkBdd );
PRT( "Unateness", clkUnate );
PRT( "Total ", clock() - clk );
// deref the PO functions
Abc_NtkFreeGlobalBdds( pNtk );
// stop the global BDD manager
Extra_StopManager( pNtk->pManGlob );
pNtk->pManGlob = NULL;
}
/**Function*************************************************************
Synopsis [Detects unate variables using SAT.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkPrintUnateSat( Abc_Ntk_t * pNtk, int fVerbose )
{
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

12
src/base/abci/abcVerify.c
View File

@ -148,9 +148,9 @@ void Abc_NtkCecFraig( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int nSeconds, int fV
Fraig_ParamsSetDefault( &Params );
Params.fVerbose = fVerbose;
Params.nSeconds = nSeconds;
Params.fFuncRed = 0;
Params.nPatsRand = 0;
Params.nPatsDyna = 0;
// Params.fFuncRed = 0;
// Params.nPatsRand = 0;
// Params.nPatsDyna = 0;
pMan = Abc_NtkToFraig( pMiter, &Params, 0, 0 );
Fraig_ManProveMiter( pMan );
@ -328,9 +328,9 @@ void Abc_NtkSecFraig( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int nSeconds, int nF
Fraig_ParamsSetDefault( &Params );
Params.fVerbose = fVerbose;
Params.nSeconds = nSeconds;
Params.fFuncRed = 0;
Params.nPatsRand = 0;
Params.nPatsDyna = 0;
// Params.fFuncRed = 0;
// Params.nPatsRand = 0;
// Params.nPatsDyna = 0;
pMan = Abc_NtkToFraig( pFrames, &Params, 0, 0 );
Fraig_ManProveMiter( pMan );

2
src/base/abci/module.make
View File

@ -1,5 +1,6 @@
SRC += src/base/abci/abc.c \
src/base/abci/abcAttach.c \
src/base/abci/abcAuto.c \
src/base/abci/abcBalance.c \
src/base/abci/abcCollapse.c \
src/base/abci/abcCut.c \
@ -21,6 +22,7 @@ SRC += src/base/abci/abc.c \
src/base/abci/abcSweep.c \
src/base/abci/abcSymm.c \
src/base/abci/abcTiming.c \
src/base/abci/abcUnate.c \
src/base/abci/abcUnreach.c \
src/base/abci/abcVanEijk.c \
src/base/abci/abcVanImp.c \

4
src/base/cmd/cmd.c
View File

@ -1204,7 +1204,7 @@ int CmdCommandSis( Abc_Frame_t * pAbc, int argc, char **argv )
char * pSisName;
int i;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -1340,7 +1340,7 @@ int CmdCommandMvsis( Abc_Frame_t * pAbc, int argc, char **argv )
char * pMvsisName;
int i;
pNtk = Abc_FrameReadNet(pAbc);
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);

1
src/base/io/io.h
View File

@ -69,6 +69,7 @@ extern Abc_Obj_t * Io_ReadCreateNode( Abc_Ntk_t * pNtk, char * pNameOut,
extern Abc_Obj_t * Io_ReadCreateConst( Abc_Ntk_t * pNtk, char * pName, bool fConst1 );
extern Abc_Obj_t * Io_ReadCreateInv( Abc_Ntk_t * pNtk, char * pNameIn, char * pNameOut );
extern Abc_Obj_t * Io_ReadCreateBuf( Abc_Ntk_t * pNtk, char * pNameIn, char * pNameOut );
extern FILE * Io_FileOpen( const char * FileName, const char * PathVar, const char * Mode, int fVerbose );
/*=== abcWriteBaf.c ==========================================================*/
extern void Io_WriteBaf( Abc_Ntk_t * pNtk, char * pFileName );
/*=== abcWriteBlif.c ==========================================================*/

2
src/base/io/ioReadBench.c
View File

@ -47,7 +47,7 @@ Abc_Ntk_t * Io_ReadBench( char * pFileName, int fCheck )
Abc_Ntk_t * pNtk;
// start the file
p = Extra_FileReaderAlloc( pFileName, "#", "\n", " \t\r,()=" );
p = Extra_FileReaderAlloc( pFileName, "#", "\n\r", " \t,()=" );
if ( p == NULL )
return NULL;

3
src/base/io/ioReadBlif.c
View File

@ -135,7 +135,8 @@ Io_ReadBlif_t * Io_ReadBlifFile( char * pFileName )
Io_ReadBlif_t * p;
// start the reader
pReader = Extra_FileReaderAlloc( pFileName, "#", "\n", " \t\r" );
pReader = Extra_FileReaderAlloc( pFileName, "#", "\n\r", " \t" );
if ( pReader == NULL )
return NULL;

2
src/base/io/ioReadEdif.c
View File

@ -47,7 +47,7 @@ Abc_Ntk_t * Io_ReadEdif( char * pFileName, int fCheck )
Abc_Ntk_t * pNtk;
// start the file
p = Extra_FileReaderAlloc( pFileName, "#", "\n", " \t\r()" );
p = Extra_FileReaderAlloc( pFileName, "#", "\n\r", " \t()" );
if ( p == NULL )
return NULL;

2
src/base/io/ioReadPla.c
View File

@ -47,7 +47,7 @@ Abc_Ntk_t * Io_ReadPla( char * pFileName, int fCheck )
Abc_Ntk_t * pNtk;
// start the file
p = Extra_FileReaderAlloc( pFileName, "#", "\n", " \t\r|" );
p = Extra_FileReaderAlloc( pFileName, "#", "\n\r", " \t|" );
if ( p == NULL )
return NULL;

55
src/base/io/ioUtil.c
View File

@ -194,6 +194,61 @@ Abc_Obj_t * Io_ReadCreateBuf( Abc_Ntk_t * pNtk, char * pNameIn, char * pNameOut
return pNet;
}
/**Function*************************************************************
Synopsis [Provide an fopen replacement with path lookup]
Description [Provide an fopen replacement where the path stored
in pathvar MVSIS variable is used to look up the path
for name. Returns NULL if file cannot be opened.]
SideEffects []
SeeAlso []
***********************************************************************/
FILE * Io_FileOpen( const char * FileName, const char * PathVar, const char * Mode, int fVerbose )
{
char * t = 0, * c = 0, * i;
extern char * Abc_FrameReadFlag( char * pFlag );
if ( PathVar == 0 )
{
return fopen( FileName, Mode );
}
else
{
if ( c = Abc_FrameReadFlag( (char*)PathVar ) )
{
char ActualFileName[4096];
FILE * fp = 0;
t = util_strsav( c );
for (i = strtok( t, ":" ); i != 0; i = strtok( 0, ":") )
{
#ifdef WIN32
_snprintf ( ActualFileName, 4096, "%s/%s", i, FileName );
#else
snprintf ( ActualFileName, 4096, "%s/%s", i, FileName );
#endif
if ( ( fp = fopen ( ActualFileName, Mode ) ) )
{
if ( fVerbose )
fprintf ( stdout, "Using file %s\n", ActualFileName );
free( t );
return fp;
}
}
free( t );
return 0;
}
else
{
return fopen( FileName, Mode );
}
}
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

3
src/base/io/module.make
View File

@ -16,4 +16,5 @@ SRC += src/base/io/io.c \
src/base/io/ioWriteEqn.c \
src/base/io/ioWriteGml.c \
src/base/io/ioWriteList.c \
src/base/io/ioWritePla.c
src/base/io/ioWritePla.c \
src/base/io/ioWriteVerilog.c

2
src/base/main/main.c
View File

@ -217,7 +217,7 @@ int main( int argc, char * argv[] )
break;
}
}
// if the memory should be freed, quit packages
if ( fStatus < 0 )
{

2
src/base/main/main.h
View File

@ -78,7 +78,7 @@ extern void Abc_Start();
extern void Abc_Stop();
/*=== mainFrame.c ===========================================================*/
extern Abc_Ntk_t * Abc_FrameReadNet( Abc_Frame_t * p );
extern Abc_Ntk_t * Abc_FrameReadNtk( Abc_Frame_t * p );
extern FILE * Abc_FrameReadOut( Abc_Frame_t * p );
extern FILE * Abc_FrameReadErr( Abc_Frame_t * p );
extern bool Abc_FrameReadMode( Abc_Frame_t * p );

2
src/base/main/mainFrame.c
View File

@ -164,7 +164,7 @@ void Abc_FrameRestart( Abc_Frame_t * p )
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_FrameReadNet( Abc_Frame_t * p )
Abc_Ntk_t * Abc_FrameReadNtk( Abc_Frame_t * p )
{
return p->pNtkCur;
}

6
src/base/seq/seqAigCore.c
View File

@ -351,11 +351,13 @@ int Seq_NtkImplementRetimingBackward( Abc_Ntk_t * pNtk, Vec_Ptr_t * vMoves, int
printf( "The number of ANDs in the AIG = %5d.\n", Abc_NtkNodeNum(pNtkMiter) );
// transform the miter into a logic network for efficient CNF construction
pNtkCnf = Abc_NtkRenode( pNtkMiter, 0, 100, 1, 0, 0 );
Abc_NtkDelete( pNtkMiter );
// pNtkCnf = Abc_NtkRenode( pNtkMiter, 0, 100, 1, 0, 0 );
// Abc_NtkDelete( pNtkMiter );
pNtkCnf = pNtkMiter;
// solve the miter
clk = clock();
// RetValue = Abc_NtkMiterSat_OldAndRusty( pNtkCnf, 30, 0 );
RetValue = Abc_NtkMiterSat( pNtkCnf, 30, 0 );
if ( fVerbose )
if ( clock() - clk > 100 )

1
src/bdd/dsd/dsd.h
View File

@ -91,6 +91,7 @@ extern void Dsd_NodeSetMark( Dsd_Node_t * p, int Mark );
extern DdManager * Dsd_ManagerReadDd( Dsd_Manager_t * pMan );
extern Dsd_Node_t * Dsd_ManagerReadRoot( Dsd_Manager_t * pMan, int i );
extern Dsd_Node_t * Dsd_ManagerReadInput( Dsd_Manager_t * pMan, int i );
extern Dsd_Node_t * Dsd_ManagerReadConst1( Dsd_Manager_t * pMan );
/*=== dsdMan.c =======================================================*/
extern Dsd_Manager_t * Dsd_ManagerStart( DdManager * dd, int nSuppMax, int fVerbose );
extern void Dsd_ManagerStop( Dsd_Manager_t * dMan );

1
src/bdd/dsd/dsdApi.c
View File

@ -89,6 +89,7 @@ void Dsd_NodeSetMark( Dsd_Node_t * p, int Mark ){ p->Mark = Mark; }
***********************************************************************/
Dsd_Node_t * Dsd_ManagerReadRoot( Dsd_Manager_t * pMan, int i ) { return pMan->pRoots[i]; }
Dsd_Node_t * Dsd_ManagerReadInput( Dsd_Manager_t * pMan, int i ) { return pMan->pInputs[i]; }
Dsd_Node_t * Dsd_ManagerReadConst1( Dsd_Manager_t * pMan ) { return pMan->pConst1; }
DdManager * Dsd_ManagerReadDd( Dsd_Manager_t * pMan ) { return pMan->dd; }
////////////////////////////////////////////////////////////////////////

1
src/bdd/dsd/dsdInt.h
View File

@ -42,6 +42,7 @@ struct Dsd_Manager_t_
int nRootsAlloc;// the number of primary outputs
Dsd_Node_t ** pInputs; // the primary input nodes
Dsd_Node_t ** pRoots; // the primary output nodes
Dsd_Node_t * pConst1; // the constant node
int fVerbose; // the verbosity level
};

1
src/bdd/dsd/dsdMan.c
View File

@ -73,6 +73,7 @@ Dsd_Manager_t * Dsd_ManagerStart( DdManager * dd, int nSuppMax, int fVerbose )
pNode->G = b1; Cudd_Ref( pNode->G );
pNode->S = b1; Cudd_Ref( pNode->S );
st_insert( dMan->Table, (char*)b1, (char*)pNode );
dMan->pConst1 = pNode;
Dsd_CheckCacheAllocate( 5000 );
return dMan;

4
src/map/fpga/fpga.c
View File

@ -105,7 +105,7 @@ int Fpga_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
int fVerbose;
int c;
pNet = Abc_FrameReadNet(pAbc);
pNet = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -195,7 +195,7 @@ int Fpga_CommandPrintLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
int fVerbose;
int c;
pNet = Abc_FrameReadNet(pAbc);
pNet = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);

6
src/map/mapper/mapper.c
View File

@ -87,7 +87,7 @@ int Map_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
int fAlgorithm;
int c;
pNet = Abc_FrameReadNet(pAbc);
pNet = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -128,8 +128,8 @@ int Map_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
// get the input file name
FileName = argv[util_optind];
// if ( (pFile = Io_FileOpen( FileName, "open_path", "r" )) == NULL )
if ( (pFile = fopen( FileName, "r" )) == NULL )
if ( (pFile = Io_FileOpen( FileName, "open_path", "r", 0 )) == NULL )
// if ( (pFile = fopen( FileName, "r" )) == NULL )
{
fprintf( pErr, "Cannot open input file \"%s\". ", FileName );
if ( FileName = Extra_FileGetSimilarName( FileName, ".genlib", ".lib", ".gen", ".g", NULL ) )

2
src/map/mapper/mapperCreate.c
View File

@ -314,7 +314,7 @@ void Map_ManPrintTimeStats( Map_Man_t * p )
void Map_ManPrintStatsToFile( char * pName, float Area, float Delay, int Time )
{
FILE * pTable;
pTable = fopen( "stats.txt", "a+" );
pTable = fopen( "map_stats.txt", "a+" );
fprintf( pTable, "%s ", pName );
fprintf( pTable, "%4.2f ", Area );
fprintf( pTable, "%4.2f ", Delay );

8
src/map/mapper/mapperTree.c
View File

@ -60,8 +60,8 @@ int Map_LibraryReadTree( Map_SuperLib_t * pLib, char * pFileName, char * pExclud
// read the beginning of the file
assert( pLib->pGenlib == NULL );
// pFile = Io_FileOpen( pFileName, "open_path", "r" );
pFile = fopen( pFileName, "r" );
pFile = Io_FileOpen( pFileName, "open_path", "r", 1 );
// pFile = fopen( pFileName, "r" );
if ( pFile == NULL )
{
printf( "Cannot open input file \"%s\".\n", pFileName );
@ -149,8 +149,8 @@ int Map_LibraryReadFileTree( Map_SuperLib_t * pLib, FILE * pFile, char *pFileNam
}
#endif
// pFileGen = Io_FileOpen( pLibFile, "open_path", "r" );
pFileGen = fopen( pLibFile, "r" );
pFileGen = Io_FileOpen( pLibFile, "open_path", "r", 1 );
// pFileGen = fopen( pLibFile, "r" );
if ( pFileGen == NULL )
{
printf( "Cannot open the GENLIB file \"%s\".\n", pLibFile );

6
src/map/mio/mio.c
View File

@ -133,7 +133,7 @@ int Mio_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
int fVerbose;
int c;
pNet = Abc_FrameReadNet(pAbc);
pNet = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
@ -163,7 +163,7 @@ int Mio_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
// get the input file name
FileName = argv[util_optind];
if ( (pFile = fopen( FileName, "r" )) == NULL )
if ( (pFile = Io_FileOpen( FileName, "open_path", "r", 0 )) == NULL )
{
fprintf( pErr, "Cannot open input file \"%s\". ", FileName );
if ( (FileName = Extra_FileGetSimilarName( FileName, ".genlib", ".lib", ".gen", ".g", NULL )) )
@ -223,7 +223,7 @@ int Mio_CommandPrintLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
int fVerbose;
int c;
pNet = Abc_FrameReadNet(pAbc);
pNet = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);

4
src/map/mio/mioRead.c
View File

@ -114,8 +114,8 @@ Mio_Library_t * Mio_LibraryReadOne( Abc_Frame_t * pAbc, char * FileName, bool fE
int nFileSize;
// open the BLIF file for binary reading
// pFile = Io_FileOpen( FileName, "open_path", "rb" );
pFile = fopen( FileName, "rb" );
pFile = Io_FileOpen( FileName, "open_path", "rb", 1 );
// pFile = fopen( FileName, "rb" );
// if we got this far, file should be okay otherwise would
// have been detected by caller
assert ( pFile != NULL );

4
src/map/super/super.c
View File

@ -245,8 +245,8 @@ int Super_CommandSupergates( Abc_Frame_t * pAbc, int argc, char **argv )
// get the input file name
FileName = argv[util_optind];
// if ( (pFile = Io_FileOpen( FileName, "open_path", "r" )) == NULL )
if ( (pFile = fopen( FileName, "r" )) == NULL )
if ( (pFile = Io_FileOpen( FileName, "open_path", "r", 0 )) == NULL )
// if ( (pFile = fopen( FileName, "r" )) == NULL )
{
fprintf( pErr, "Cannot open input file \"%s\". ", FileName );
if (( FileName = Extra_FileGetSimilarName( FileName, ".genlib", ".lib", ".gen", ".g", NULL ) ))

69
src/misc/extra/extra.h
View File

@ -106,7 +106,35 @@ typedef unsigned long long uint64;
/* Various Utilities */
/*===========================================================================*/
/*=== extraBddAuto.c ========================================================*/
extern DdNode * Extra_bddSpaceFromFunctionFast( DdManager * dd, DdNode * bFunc );
extern DdNode * Extra_bddSpaceFromFunction( DdManager * dd, DdNode * bF, DdNode * bG );
extern DdNode * extraBddSpaceFromFunction( DdManager * dd, DdNode * bF, DdNode * bG );
extern DdNode * Extra_bddSpaceFromFunctionPos( DdManager * dd, DdNode * bFunc );
extern DdNode * extraBddSpaceFromFunctionPos( DdManager * dd, DdNode * bFunc );
extern DdNode * Extra_bddSpaceFromFunctionNeg( DdManager * dd, DdNode * bFunc );
extern DdNode * extraBddSpaceFromFunctionNeg( DdManager * dd, DdNode * bFunc );
extern DdNode * Extra_bddSpaceCanonVars( DdManager * dd, DdNode * bSpace );
extern DdNode * extraBddSpaceCanonVars( DdManager * dd, DdNode * bSpace );
extern DdNode * Extra_bddSpaceEquations( DdManager * dd, DdNode * bSpace );
extern DdNode * Extra_bddSpaceEquationsNeg( DdManager * dd, DdNode * bSpace );
extern DdNode * extraBddSpaceEquationsNeg( DdManager * dd, DdNode * bSpace );
extern DdNode * Extra_bddSpaceEquationsPos( DdManager * dd, DdNode * bSpace );
extern DdNode * extraBddSpaceEquationsPos( DdManager * dd, DdNode * bSpace );
extern DdNode * Extra_bddSpaceFromMatrixPos( DdManager * dd, DdNode * zA );
extern DdNode * extraBddSpaceFromMatrixPos( DdManager * dd, DdNode * zA );
extern DdNode * Extra_bddSpaceFromMatrixNeg( DdManager * dd, DdNode * zA );
extern DdNode * extraBddSpaceFromMatrixNeg( DdManager * dd, DdNode * zA );
extern DdNode * Extra_bddSpaceReduce( DdManager * dd, DdNode * bFunc, DdNode * bCanonVars );
extern DdNode ** Extra_bddSpaceExorGates( DdManager * dd, DdNode * bFuncRed, DdNode * zEquations );
/*=== extraBddMisc.c ========================================================*/
extern DdNode * Extra_TransferPermute( DdManager * ddSource, DdManager * ddDestination, DdNode * f, int * Permute );
extern DdNode * Extra_TransferLevelByLevel( DdManager * ddSource, DdManager * ddDestination, DdNode * f );
extern DdNode * Extra_bddRemapUp( DdManager * dd, DdNode * bF );
@ -126,6 +154,7 @@ extern DdNode * Extra_bddFindOneCube( DdManager * dd, DdNode * bF );
extern DdNode * Extra_bddGetOneCube( DdManager * dd, DdNode * bFunc );
extern DdNode * Extra_bddComputeRangeCube( DdManager * dd, int iStart, int iStop );
extern DdNode * Extra_bddBitsToCube( DdManager * dd, int Code, int CodeWidth, DdNode ** pbVars, int fMsbFirst );
extern DdNode * Extra_bddSupportNegativeCube( DdManager * dd, DdNode * f );
/*=== extraBddKmap.c ================================================================*/
@ -185,6 +214,46 @@ extern DdNode * extraZddTuplesFromBdd( DdManager * dd, DdNode * bVarsK, DdNo
extern DdNode * Extra_zddSelectOneSubset( DdManager * dd, DdNode * zS );
extern DdNode * extraZddSelectOneSubset( DdManager * dd, DdNode * zS );
/*=== extraBddUnate.c =================================================================*/
typedef struct Extra_UnateVar_t_ Extra_UnateVar_t;
struct Extra_UnateVar_t_ {
unsigned iVar : 30; // index of the variable
unsigned Pos : 1; // 1 if positive unate
unsigned Neg : 1; // 1 if negative unate
};
typedef struct Extra_UnateInfo_t_ Extra_UnateInfo_t;
struct Extra_UnateInfo_t_ {
int nVars; // the number of variables in the support
int nVarsMax; // the number of variables in the DD manager
int nUnate; // the number of unate variables
Extra_UnateVar_t * pVars; // the array of variables present in the support
};
/* allocates the data structure */
extern Extra_UnateInfo_t * Extra_UnateInfoAllocate( int nVars );
/* deallocates the data structure */
extern void Extra_UnateInfoDissolve( Extra_UnateInfo_t * );
/* print the contents the data structure */
extern void Extra_UnateInfoPrint( Extra_UnateInfo_t * );
/* converts the ZDD into the Extra_SymmInfo_t structure */
extern Extra_UnateInfo_t * Extra_UnateInfoCreateFromZdd( DdManager * dd, DdNode * zUnate, DdNode * bVars );
/* naive check of unateness of one variable */
extern int Extra_bddCheckUnateNaive( DdManager * dd, DdNode * bF, int iVar );
/* computes the unateness information for the function */
extern Extra_UnateInfo_t * Extra_UnateComputeFast( DdManager * dd, DdNode * bFunc );
extern Extra_UnateInfo_t * Extra_UnateComputeSlow( DdManager * dd, DdNode * bFunc );
/* computes the classical symmetry information as a ZDD */
extern DdNode * Extra_zddUnateInfoCompute( DdManager * dd, DdNode * bF, DdNode * bVars );
extern DdNode * extraZddUnateInfoCompute( DdManager * dd, DdNode * bF, DdNode * bVars );
/* converts a set of variables into a set of singleton subsets */
extern DdNode * Extra_zddGetSingletonsBoth( DdManager * dd, DdNode * bVars );
extern DdNode * extraZddGetSingletonsBoth( DdManager * dd, DdNode * bVars );
/*=== extraUtilBitMatrix.c ================================================================*/
typedef struct Extra_BitMat_t_ Extra_BitMat_t;

1558
src/misc/extra/extraBddAuto.c Normal file
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File diff suppressed because it is too large Load Diff

77
src/misc/extra/extraBddMisc.c
View File

@ -719,6 +719,83 @@ DdNode * Extra_bddBitsToCube( DdManager * dd, int Code, int CodeWidth, DdNode **
return bResult;
} /* end of Extra_bddBitsToCube */
/**Function********************************************************************
Synopsis [Finds the support as a negative polarity cube.]
Description [Finds the variables on which a DD depends. Returns a BDD
consisting of the product of the variables in the negative polarity
if successful; NULL otherwise.]
SideEffects [None]
SeeAlso [Cudd_VectorSupport Cudd_Support]
******************************************************************************/
DdNode * Extra_bddSupportNegativeCube( DdManager * dd, DdNode * f )
{
int *support;
DdNode *res, *tmp, *var;
int i, j;
int size;
/* Allocate and initialize support array for ddSupportStep. */
size = ddMax( dd->size, dd->sizeZ );
support = ALLOC( int, size );
if ( support == NULL )
{
dd->errorCode = CUDD_MEMORY_OUT;
return ( NULL );
}
for ( i = 0; i < size; i++ )
{
support[i] = 0;
}
/* Compute support and clean up markers. */
ddSupportStep( Cudd_Regular( f ), support );
ddClearFlag( Cudd_Regular( f ) );
/* Transform support from array to cube. */
do
{
dd->reordered = 0;
res = DD_ONE( dd );
cuddRef( res );
for ( j = size - 1; j >= 0; j-- )
{ /* for each level bottom-up */
i = ( j >= dd->size ) ? j : dd->invperm[j];
if ( support[i] == 1 )
{
var = cuddUniqueInter( dd, i, dd->one, Cudd_Not( dd->one ) );
//////////////////////////////////////////////////////////////////
var = Cudd_Not(var);
//////////////////////////////////////////////////////////////////
cuddRef( var );
tmp = cuddBddAndRecur( dd, res, var );
if ( tmp == NULL )
{
Cudd_RecursiveDeref( dd, res );
Cudd_RecursiveDeref( dd, var );
res = NULL;
break;
}
cuddRef( tmp );
Cudd_RecursiveDeref( dd, res );
Cudd_RecursiveDeref( dd, var );
res = tmp;
}
}
}
while ( dd->reordered == 1 );
FREE( support );
if ( res != NULL )
cuddDeref( res );
return ( res );
} /* end of Extra_SupportNeg */
/*---------------------------------------------------------------------------*/
/* Definition of internal functions */
/*---------------------------------------------------------------------------*/

641
src/misc/extra/extraBddUnate.c Normal file
View File

@ -0,0 +1,641 @@
/**CFile****************************************************************
FileName [extraBddUnate.c]
PackageName [extra]
Synopsis [Efficient methods to compute the information about
unate variables using an algorithm that is conceptually similar to
the algorithm for two-variable symmetry computation presented in:
A. Mishchenko. Fast Computation of Symmetries in Boolean Functions.
Transactions on CAD, Nov. 2003.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 2.0. Started - September 1, 2003.]
Revision [$Id: extraBddUnate.c,v 1.0 2003/09/01 00:00:00 alanmi Exp $]
***********************************************************************/
#include "extra.h"
/*---------------------------------------------------------------------------*/
/* Constant declarations */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/* Stucture declarations */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/* Type declarations */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/* Variable declarations */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/* Macro declarations */
/*---------------------------------------------------------------------------*/
/**AutomaticStart*************************************************************/
/*---------------------------------------------------------------------------*/
/* Static function prototypes */
/*---------------------------------------------------------------------------*/
/**AutomaticEnd***************************************************************/
/*---------------------------------------------------------------------------*/
/* Definition of exported functions */
/*---------------------------------------------------------------------------*/
/**Function********************************************************************
Synopsis [Computes the classical symmetry information for the function.]
Description [Returns the symmetry information in the form of Extra_UnateInfo_t structure.]
SideEffects [If the ZDD variables are not derived from BDD variables with
multiplicity 2, this function may derive them in a wrong way.]
SeeAlso []
******************************************************************************/
Extra_UnateInfo_t * Extra_UnateComputeFast(
DdManager * dd, /* the manager */
DdNode * bFunc) /* the function whose symmetries are computed */
{
DdNode * bSupp;
DdNode * zRes;
Extra_UnateInfo_t * p;
bSupp = Cudd_Support( dd, bFunc ); Cudd_Ref( bSupp );
zRes = Extra_zddUnateInfoCompute( dd, bFunc, bSupp ); Cudd_Ref( zRes );
p = Extra_UnateInfoCreateFromZdd( dd, zRes, bSupp );
Cudd_RecursiveDeref( dd, bSupp );
Cudd_RecursiveDerefZdd( dd, zRes );
return p;
} /* end of Extra_UnateInfoCompute */
/**Function********************************************************************
Synopsis [Computes the classical symmetry information as a ZDD.]
Description []
SideEffects []
SeeAlso []
******************************************************************************/
DdNode * Extra_zddUnateInfoCompute(
DdManager * dd, /* the DD manager */
DdNode * bF,
DdNode * bVars)
{
DdNode * res;
do {
dd->reordered = 0;
res = extraZddUnateInfoCompute( dd, bF, bVars );
} while (dd->reordered == 1);
return(res);
} /* end of Extra_zddUnateInfoCompute */
/**Function********************************************************************
Synopsis [Converts a set of variables into a set of singleton subsets.]
Description []
SideEffects []
SeeAlso []
******************************************************************************/
DdNode * Extra_zddGetSingletonsBoth(
DdManager * dd, /* the DD manager */
DdNode * bVars) /* the set of variables */
{
DdNode * res;
do {
dd->reordered = 0;
res = extraZddGetSingletonsBoth( dd, bVars );
} while (dd->reordered == 1);
return(res);
} /* end of Extra_zddGetSingletonsBoth */
/**Function********************************************************************
Synopsis [Allocates unateness information structure.]
Description []
SideEffects []
SeeAlso []
******************************************************************************/
Extra_UnateInfo_t * Extra_UnateInfoAllocate( int nVars )
{
Extra_UnateInfo_t * p;
// allocate and clean the storage for unateness info
p = ALLOC( Extra_UnateInfo_t, 1 );
memset( p, 0, sizeof(Extra_UnateInfo_t) );
p->nVars = nVars;
p->pVars = ALLOC( Extra_UnateVar_t, nVars );
memset( p->pVars, 0, nVars * sizeof(Extra_UnateVar_t) );
return p;
} /* end of Extra_UnateInfoAllocate */
/**Function********************************************************************
Synopsis [Deallocates symmetry information structure.]
Description []
SideEffects []
SeeAlso []
******************************************************************************/
void Extra_UnateInfoDissolve( Extra_UnateInfo_t * p )
{
free( p->pVars );
free( p );
} /* end of Extra_UnateInfoDissolve */
/**Function********************************************************************
Synopsis [Allocates symmetry information structure.]
Description []
SideEffects []
SeeAlso []
******************************************************************************/
void Extra_UnateInfoPrint( Extra_UnateInfo_t * p )
{
char * pBuffer;
int i;
pBuffer = ALLOC( char, p->nVarsMax+1 );
memset( pBuffer, ' ', p->nVarsMax );
pBuffer[p->nVarsMax] = 0;
for ( i = 0; i < p->nVars; i++ )
if ( p->pVars[i].Neg )
pBuffer[ p->pVars[i].iVar ] = 'n';
else if ( p->pVars[i].Pos )
pBuffer[ p->pVars[i].iVar ] = 'p';
else
pBuffer[ p->pVars[i].iVar ] = '.';
printf( "%s\n", pBuffer );
free( pBuffer );
} /* end of Extra_UnateInfoPrint */
/**Function********************************************************************
Synopsis [Creates the symmetry information structure from ZDD.]
Description [ZDD representation of symmetries is the set of cubes, each
of which has two variables in the positive polarity. These variables correspond
to the symmetric variable pair.]
SideEffects []
SeeAlso []
******************************************************************************/
Extra_UnateInfo_t * Extra_UnateInfoCreateFromZdd( DdManager * dd, DdNode * zPairs, DdNode * bSupp )
{
Extra_UnateInfo_t * p;
DdNode * bTemp, * zSet, * zCube, * zTemp;
int * pMapVars2Nums;
int i, nSuppSize;
nSuppSize = Extra_bddSuppSize( dd, bSupp );
// allocate and clean the storage for symmetry info
p = Extra_UnateInfoAllocate( nSuppSize );
// allocate the storage for the temporary map
pMapVars2Nums = ALLOC( int, dd->size );
memset( pMapVars2Nums, 0, dd->size * sizeof(int) );
// assign the variables
p->nVarsMax = dd->size;
for ( i = 0, bTemp = bSupp; bTemp != b1; bTemp = cuddT(bTemp), i++ )
{
p->pVars[i].iVar = bTemp->index;
pMapVars2Nums[bTemp->index] = i;
}
// write the symmetry info into the structure
zSet = zPairs; Cudd_Ref( zSet );
// Cudd_zddPrintCover( dd, zPairs ); printf( "\n" );
while ( zSet != z0 )
{
// get the next cube
zCube = Extra_zddSelectOneSubset( dd, zSet ); Cudd_Ref( zCube );
// add this var to the data structure
assert( cuddT(zCube) == z1 && cuddE(zCube) == z0 );
if ( zCube->index & 1 ) // neg
p->pVars[ pMapVars2Nums[zCube->index/2] ].Neg = 1;
else
p->pVars[ pMapVars2Nums[zCube->index/2] ].Pos = 1;
// count the unate vars
p->nUnate++;
// update the cuver and deref the cube
zSet = Cudd_zddDiff( dd, zTemp = zSet, zCube ); Cudd_Ref( zSet );
Cudd_RecursiveDerefZdd( dd, zTemp );
Cudd_RecursiveDerefZdd( dd, zCube );
} // for each cube
Cudd_RecursiveDerefZdd( dd, zSet );
FREE( pMapVars2Nums );
return p;
} /* end of Extra_UnateInfoCreateFromZdd */
/**Function********************************************************************
Synopsis [Computes the classical unateness information for the function.]
Description [Uses the naive way of comparing cofactors.]
SideEffects []
SeeAlso []
******************************************************************************/
Extra_UnateInfo_t * Extra_UnateComputeSlow( DdManager * dd, DdNode * bFunc )
{
int nSuppSize;
DdNode * bSupp, * bTemp;
Extra_UnateInfo_t * p;
int i, Res;
// compute the support
bSupp = Cudd_Support( dd, bFunc ); Cudd_Ref( bSupp );
nSuppSize = Extra_bddSuppSize( dd, bSupp );
//printf( "Support = %d. ", nSuppSize );
//Extra_bddPrint( dd, bSupp );
//printf( "%d ", nSuppSize );
// allocate the storage for symmetry info
p = Extra_UnateInfoAllocate( nSuppSize );
// assign the variables
p->nVarsMax = dd->size;
for ( i = 0, bTemp = bSupp; bTemp != b1; bTemp = cuddT(bTemp), i++ )
{
Res = Extra_bddCheckUnateNaive( dd, bFunc, bTemp->index );
p->pVars[i].iVar = bTemp->index;
if ( Res == -1 )
p->pVars[i].Neg = 1;
else if ( Res == 1 )
p->pVars[i].Pos = 1;
p->nUnate += (Res != 0);
}
Cudd_RecursiveDeref( dd, bSupp );
return p;
} /* end of Extra_UnateComputeSlow */
/**Function********************************************************************
Synopsis [Checks if the two variables are symmetric.]
Description [Returns 0 if vars are not unate. Return -1/+1 if the var is neg/pos unate.]
SideEffects []
SeeAlso []
******************************************************************************/
int Extra_bddCheckUnateNaive(
DdManager * dd, /* the DD manager */
DdNode * bF,
int iVar)
{
DdNode * bCof0, * bCof1;
int Res;
assert( iVar < dd->size );
bCof0 = Cudd_Cofactor( dd, bF, Cudd_Not(Cudd_bddIthVar(dd,iVar)) ); Cudd_Ref( bCof0 );
bCof1 = Cudd_Cofactor( dd, bF, Cudd_bddIthVar(dd,iVar) ); Cudd_Ref( bCof1 );
if ( Cudd_bddLeq( dd, bCof0, bCof1 ) )
Res = 1;
else if ( Cudd_bddLeq( dd, bCof1, bCof0 ) )
Res =-1;
else
Res = 0;
Cudd_RecursiveDeref( dd, bCof0 );
Cudd_RecursiveDeref( dd, bCof1 );
return Res;
} /* end of Extra_bddCheckUnateNaive */
/*---------------------------------------------------------------------------*/
/* Definition of internal functions */
/*---------------------------------------------------------------------------*/
/**Function********************************************************************
Synopsis [Performs a recursive step of Extra_UnateInfoCompute.]
Description [Returns the set of symmetric variable pairs represented as a set
of two-literal ZDD cubes. Both variables always appear in the positive polarity
in the cubes. This function works without building new BDD nodes. Some relatively
small number of ZDD nodes may be built to ensure proper bookkeeping of the
symmetry information.]
SideEffects []
SeeAlso []
******************************************************************************/
DdNode *
extraZddUnateInfoCompute(
DdManager * dd, /* the manager */
DdNode * bFunc, /* the function whose symmetries are computed */
DdNode * bVars ) /* the set of variables on which this function depends */
{
DdNode * zRes;
DdNode * bFR = Cudd_Regular(bFunc);
if ( cuddIsConstant(bFR) )
{
if ( cuddIsConstant(bVars) )
return z0;
return extraZddGetSingletonsBoth( dd, bVars );
}
assert( bVars != b1 );
if ( zRes = cuddCacheLookup2Zdd(dd, extraZddUnateInfoCompute, bFunc, bVars) )
return zRes;
else
{
DdNode * zRes0, * zRes1;
DdNode * zTemp, * zPlus;
DdNode * bF0, * bF1;
DdNode * bVarsNew;
int nVarsExtra;
int LevelF;
int AddVar;
// every variable in bF should be also in bVars, therefore LevelF cannot be above LevelV
// if LevelF is below LevelV, scroll through the vars in bVars to the same level as F
// count how many extra vars are there in bVars
nVarsExtra = 0;
LevelF = dd->perm[bFR->index];
for ( bVarsNew = bVars; LevelF > dd->perm[bVarsNew->index]; bVarsNew = cuddT(bVarsNew) )
nVarsExtra++;
// the indexes (level) of variables should be synchronized now
assert( bFR->index == bVarsNew->index );
// cofactor the function
if ( bFR != bFunc ) // bFunc is complemented
{
bF0 = Cudd_Not( cuddE(bFR) );
bF1 = Cudd_Not( cuddT(bFR) );
}
else
{
bF0 = cuddE(bFR);
bF1 = cuddT(bFR);
}
// solve subproblems
zRes0 = extraZddUnateInfoCompute( dd, bF0, cuddT(bVarsNew) );
if ( zRes0 == NULL )
return NULL;
cuddRef( zRes0 );
// if there is no symmetries in the negative cofactor
// there is no need to test the positive cofactor
if ( zRes0 == z0 )
zRes = zRes0; // zRes takes reference
else
{
zRes1 = extraZddUnateInfoCompute( dd, bF1, cuddT(bVarsNew) );
if ( zRes1 == NULL )
{
Cudd_RecursiveDerefZdd( dd, zRes0 );
return NULL;
}
cuddRef( zRes1 );
// only those variables are pair-wise symmetric
// that are pair-wise symmetric in both cofactors
// therefore, intersect the solutions
zRes = cuddZddIntersect( dd, zRes0, zRes1 );
if ( zRes == NULL )
{
Cudd_RecursiveDerefZdd( dd, zRes0 );
Cudd_RecursiveDerefZdd( dd, zRes1 );
return NULL;
}
cuddRef( zRes );
Cudd_RecursiveDerefZdd( dd, zRes0 );
Cudd_RecursiveDerefZdd( dd, zRes1 );
}
// consider the current top-most variable
AddVar = -1;
if ( Cudd_bddLeq( dd, bF0, bF1 ) ) // pos
AddVar = 0;
else if ( Cudd_bddLeq( dd, bF1, bF0 ) ) // neg
AddVar = 1;
if ( AddVar >= 0 )
{
// create the singleton
zPlus = cuddZddGetNode( dd, 2*bFR->index + AddVar, z1, z0 );
if ( zPlus == NULL )
{
Cudd_RecursiveDerefZdd( dd, zRes );
return NULL;
}
cuddRef( zPlus );
// add these to the result
zRes = cuddZddUnion( dd, zTemp = zRes, zPlus );
if ( zRes == NULL )
{
Cudd_RecursiveDerefZdd( dd, zTemp );
Cudd_RecursiveDerefZdd( dd, zPlus );
return NULL;
}
cuddRef( zRes );
Cudd_RecursiveDerefZdd( dd, zTemp );
Cudd_RecursiveDerefZdd( dd, zPlus );
}
// only zRes is referenced at this point
// if we skipped some variables, these variables cannot be symmetric with
// any variables that are currently in the support of bF, but they can be
// symmetric with the variables that are in bVars but not in the support of bF
for ( bVarsNew = bVars; LevelF > dd->perm[bVarsNew->index]; bVarsNew = cuddT(bVarsNew) )
{
// create the negative singleton
zPlus = cuddZddGetNode( dd, 2*bVarsNew->index+1, z1, z0 );
if ( zPlus == NULL )
{
Cudd_RecursiveDerefZdd( dd, zRes );
return NULL;
}
cuddRef( zPlus );
// add these to the result
zRes = cuddZddUnion( dd, zTemp = zRes, zPlus );
if ( zRes == NULL )
{
Cudd_RecursiveDerefZdd( dd, zTemp );
Cudd_RecursiveDerefZdd( dd, zPlus );
return NULL;
}
cuddRef( zRes );
Cudd_RecursiveDerefZdd( dd, zTemp );
Cudd_RecursiveDerefZdd( dd, zPlus );
// create the positive singleton
zPlus = cuddZddGetNode( dd, 2*bVarsNew->index, z1, z0 );
if ( zPlus == NULL )
{
Cudd_RecursiveDerefZdd( dd, zRes );
return NULL;
}
cuddRef( zPlus );
// add these to the result
zRes = cuddZddUnion( dd, zTemp = zRes, zPlus );
if ( zRes == NULL )
{
Cudd_RecursiveDerefZdd( dd, zTemp );
Cudd_RecursiveDerefZdd( dd, zPlus );
return NULL;
}
cuddRef( zRes );
Cudd_RecursiveDerefZdd( dd, zTemp );
Cudd_RecursiveDerefZdd( dd, zPlus );
}
cuddDeref( zRes );
/* insert the result into cache */
cuddCacheInsert2(dd, extraZddUnateInfoCompute, bFunc, bVars, zRes);
return zRes;
}
} /* end of extraZddUnateInfoCompute */
/**Function********************************************************************
Synopsis [Performs a recursive step of Extra_zddGetSingletons.]
Description [Returns the set of ZDD singletons, containing those pos/neg
polarity ZDD variables that correspond to the BDD variables in bVars.]
SideEffects []
SeeAlso []
******************************************************************************/
DdNode * extraZddGetSingletonsBoth(
DdManager * dd, /* the DD manager */
DdNode * bVars) /* the set of variables */
{
DdNode * zRes;
if ( bVars == b1 )
return z1;
if ( zRes = cuddCacheLookup1Zdd(dd, extraZddGetSingletonsBoth, bVars) )
return zRes;
else
{
DdNode * zTemp, * zPlus;
// solve subproblem
zRes = extraZddGetSingletonsBoth( dd, cuddT(bVars) );
if ( zRes == NULL )
return NULL;
cuddRef( zRes );
// create the negative singleton
zPlus = cuddZddGetNode( dd, 2*bVars->index+1, z1, z0 );
if ( zPlus == NULL )
{
Cudd_RecursiveDerefZdd( dd, zRes );
return NULL;
}
cuddRef( zPlus );
// add these to the result
zRes = cuddZddUnion( dd, zTemp = zRes, zPlus );
if ( zRes == NULL )
{
Cudd_RecursiveDerefZdd( dd, zTemp );
Cudd_RecursiveDerefZdd( dd, zPlus );
return NULL;
}
cuddRef( zRes );
Cudd_RecursiveDerefZdd( dd, zTemp );
Cudd_RecursiveDerefZdd( dd, zPlus );
// create the positive singleton
zPlus = cuddZddGetNode( dd, 2*bVars->index, z1, z0 );
if ( zPlus == NULL )
{
Cudd_RecursiveDerefZdd( dd, zRes );
return NULL;
}
cuddRef( zPlus );
// add these to the result
zRes = cuddZddUnion( dd, zTemp = zRes, zPlus );
if ( zRes == NULL )
{
Cudd_RecursiveDerefZdd( dd, zTemp );
Cudd_RecursiveDerefZdd( dd, zPlus );
return NULL;
}
cuddRef( zRes );
Cudd_RecursiveDerefZdd( dd, zTemp );
Cudd_RecursiveDerefZdd( dd, zPlus );
cuddDeref( zRes );
cuddCacheInsert1( dd, extraZddGetSingletonsBoth, bVars, zRes );
return zRes;
}
} /* end of extraZddGetSingletonsBoth */
/*---------------------------------------------------------------------------*/
/* Definition of static Functions */
/*---------------------------------------------------------------------------*/

24
src/misc/extra/extraUtilCanon.c
View File

@ -99,7 +99,8 @@ int Extra_TruthCanonFastN( int nVarsMax, int nVarsReal, unsigned * pt, unsigned
Description []
SideEffects []
SideEffects [This procedure has a bug, which shows on Solaris.
Most likely has something to do with the casts, i.g *((unsigned *)pt0)]
SeeAlso []
@ -129,21 +130,22 @@ int Extra_TruthCanonN_rec( int nVars, unsigned char * pt, unsigned ** pptRes, ch
pt0 = pt;
pt1 = pt + (1 << nVarsN) / 8;
// 5-var truth tables for this call
uInit0 = *((unsigned *)pt0);
uInit1 = *((unsigned *)pt1);
// uInit0 = *((unsigned *)pt0);
// uInit1 = *((unsigned *)pt1);
if ( nVarsN == 3 )
{
uInit0 &= 0xFF;
uInit1 &= 0xFF;
uInit0 = (uInit0 << 24) | (uInit0 << 16) | (uInit0 << 8) | uInit0;
uInit1 = (uInit1 << 24) | (uInit1 << 16) | (uInit1 << 8) | uInit1;
uInit0 = (pt0[0] << 24) | (pt0[0] << 16) | (pt0[0] << 8) | pt0[0];
uInit1 = (pt1[0] << 24) | (pt1[0] << 16) | (pt1[0] << 8) | pt1[0];
}
else if ( nVarsN == 4 )
{
uInit0 &= 0xFFFF;
uInit1 &= 0xFFFF;
uInit0 = (uInit0 << 16) | uInit0;
uInit1 = (uInit1 << 16) | uInit1;
uInit0 = (pt0[1] << 24) | (pt0[0] << 16) | (pt0[1] << 8) | pt0[0];
uInit1 = (pt1[1] << 24) | (pt1[0] << 16) | (pt1[1] << 8) | pt1[0];
}
else
{
uInit0 = (pt0[3] << 24) | (pt0[2] << 16) | (pt0[1] << 8) | pt0[0];
uInit1 = (pt1[3] << 24) | (pt1[2] << 16) | (pt1[1] << 8) | pt1[0];
}
// storage for truth tables and phases

15
src/misc/extra/extraUtilReader.c
View File

@ -262,6 +262,9 @@ void * Extra_FileReaderGetTokens_int( Extra_FileReader_t * p )
// check if the new data should to be loaded
if ( p->pBufferCur > p->pBufferStop )
Extra_FileReaderReload( p );
// printf( "%d\n", p->pBufferEnd - p->pBufferCur );
// process the string starting from the current position
for ( pChar = p->pBufferCur; pChar < p->pBufferEnd; pChar++ )
{
@ -270,6 +273,10 @@ void * Extra_FileReaderGetTokens_int( Extra_FileReader_t * p )
p->nLineCounter++;
// switch depending on the character
MapValue = p->pCharMap[*pChar];
// printf( "Char value = %d. Map value = %d.\n", *pChar, MapValue );
switch ( MapValue )
{
case EXTRA_CHAR_COMMENT:
@ -326,6 +333,14 @@ void * Extra_FileReaderGetTokens_int( Extra_FileReader_t * p )
return p->vTokens;
}
printf( "Extra_FileReader failed to parse the file \"%s\".\n", p->pFileName );
/*
{
int i;
for ( i = 0; i < p->vTokens->nSize; i++ )
printf( "%s ", p->vTokens->pArray[i] );
printf( "\n" );
}
*/
return NULL;
}

3
src/misc/extra/module.make
View File

@ -1,4 +1,5 @@
SRC += src/misc/extra/extraBddKmap.c \
SRC += src/misc/extra/extraBddAuto.c \
src/misc/extra/extraBddKmap.c \
src/misc/extra/extraBddMisc.c \
src/misc/extra/extraBddSymm.c \
src/misc/extra/extraUtilBitMatrix.c \

1
src/misc/vec/vecInt.h
View File

@ -345,6 +345,7 @@ static inline void Vec_IntGrow( Vec_Int_t * p, int nCapMin )
if ( p->nCap >= nCapMin )
return;
p->pArray = REALLOC( int, p->pArray, nCapMin );
assert( p->pArray );
p->nCap = nCapMin;
}

4
src/opt/dec/decAbc.c
View File

@ -18,7 +18,7 @@
#include "abc.h"
#include "dec.h"
#include "aig.h"
//#include "aig.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
@ -214,6 +214,7 @@ void Dec_GraphUpdateNetwork( Abc_Obj_t * pRoot, Dec_Graph_t * pGraph, bool fUpda
SeeAlso []
***********************************************************************/
/*
Aig_Node_t * Dec_GraphToNetworkAig( Aig_Man_t * pMan, Dec_Graph_t * pGraph )
{
Dec_Node_t * pNode;
@ -235,6 +236,7 @@ Aig_Node_t * Dec_GraphToNetworkAig( Aig_Man_t * pMan, Dec_Graph_t * pGraph )
// complement the result if necessary
return Aig_NotCond( pNode->pFunc, Dec_GraphIsComplement(pGraph) );
}
*/
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///

12
src/sat/aig/aig.h
View File

@ -160,6 +160,7 @@ struct Aig_Man_t_
Aig_SimInfo_t * pInfo; // random and systematic sim info for PIs
Aig_SimInfo_t * pInfoPi; // temporary sim info for the PI nodes
Aig_SimInfo_t * pInfoTemp; // temporary sim info for all nodes
Aig_Pattern_t * pPatMask; // the mask which shows what patterns are used
// simulation patterns
int nPiWords; // the number of words in the PI info
int nPatsMax; // the max number of patterns
@ -169,6 +170,7 @@ struct Aig_Man_t_
// temporary data
Vec_Ptr_t * vFanouts; // temporary storage for fanouts of a node
Vec_Ptr_t * vToReplace; // the nodes to replace
Vec_Int_t * vClassTemp; // temporary class representatives
};
// the simulation patter
@ -254,6 +256,7 @@ static inline int Aig_NodeWhatFanin( Aig_Node_t * pNode, Aig_Node_t * p
static inline int Aig_NodeGetLevelNew( Aig_Node_t * pNode ) { return 1 + AIG_MAX(Aig_NodeFanin0(pNode)->Level, Aig_NodeFanin1(pNode)->Level); }
static inline int Aig_NodeRequiredLevel( Aig_Node_t * pNode ) { return pNode->pMan->nLevelMax + 1 - pNode->LevelR; }
static inline unsigned * Aig_SimInfoForNodeId( Aig_SimInfo_t * p, int NodeId ) { assert( p->Type ); return p->pData + p->nWords * NodeId; }
static inline unsigned * Aig_SimInfoForNode( Aig_SimInfo_t * p, Aig_Node_t * pNode ) { assert( p->Type ); return p->pData + p->nWords * pNode->Id; }
static inline unsigned * Aig_SimInfoForPi( Aig_SimInfo_t * p, int Num ) { assert( !p->Type ); return p->pData + p->nWords * Num; }
@ -332,15 +335,16 @@ extern Aig_Node_t * Aig_NodeRecognizeMux( Aig_Node_t * pNode, Aig_Node_t
extern Aig_ProofType_t Aig_FraigProve( Aig_Man_t * pMan );
/*=== fraigClasses.c ==========================================================*/
extern Vec_Vec_t * Aig_ManDeriveClassesFirst( Aig_Man_t * p, Aig_SimInfo_t * pInfoAll );
extern void Aig_ManUpdateClasses( Aig_Man_t * p, Aig_SimInfo_t * pInfo, Vec_Vec_t * vClasses );
extern int Aig_ManUpdateClasses( Aig_Man_t * p, Aig_SimInfo_t * pInfo, Vec_Vec_t * vClasses, Aig_Pattern_t * pPatMask );
extern void Aig_ManCollectPatterns( Aig_Man_t * p, Aig_SimInfo_t * pInfo, Aig_Pattern_t * pMask, Vec_Ptr_t * vPats );
/*=== fraigCnf.c ==========================================================*/
extern Aig_ProofType_t Aig_ClauseSolverStart( Aig_Man_t * pMan );
/*=== fraigEngine.c ==========================================================*/
extern void Aig_EngineSimulateRandomFirst( Aig_Man_t * p );
extern void Aig_EngineSimulateFirst( Aig_Man_t * p );
extern int Aig_EngineSimulate( Aig_Man_t * p );
extern void Aig_EngineSimulateRandomFirst( Aig_Man_t * p );
/*=== fraigSim.c ==========================================================*/
extern Aig_SimInfo_t * Aig_SimInfoAlloc( int nNodes, int nWords, int Type );
extern Aig_SimInfo_t * Aig_SimInfoAlloc( int nNodes, int nBits, int Type );
extern void Aig_SimInfoClean( Aig_SimInfo_t * p );
extern void Aig_SimInfoRandom( Aig_SimInfo_t * p );
extern void Aig_SimInfoFromPattern( Aig_SimInfo_t * p, Aig_Pattern_t * pPat );
@ -349,6 +353,8 @@ extern void Aig_SimInfoFree( Aig_SimInfo_t * p );
extern void Aig_ManSimulateInfo( Aig_Man_t * p, Aig_SimInfo_t * pInfoPi, Aig_SimInfo_t * pInfoAll );
extern Aig_Pattern_t * Aig_PatternAlloc( int nBits );
extern void Aig_PatternClean( Aig_Pattern_t * pPat );
extern void Aig_PatternFill( Aig_Pattern_t * pPat );
extern int Aig_PatternCount( Aig_Pattern_t * pPat );
extern void Aig_PatternRandom( Aig_Pattern_t * pPat );
extern void Aig_PatternFree( Aig_Pattern_t * pPat );

12
src/sat/aig/aigMan.c
View File

@ -42,7 +42,7 @@
void Aig_ManSetDefaultParams( Aig_Param_t * pParam )
{
memset( pParam, 0, sizeof(Aig_Param_t) );
pParam->nPatsRand = 1024; // the number of random patterns
pParam->nPatsRand = 4096; // the number of random patterns
pParam->nBTLimit = 99; // backtrack limit at the intermediate nodes
pParam->nSeconds = 1; // the timeout for the final miter in seconds
}
@ -67,8 +67,8 @@ Aig_Man_t * Aig_ManStart( Aig_Param_t * pParam )
p = ALLOC( Aig_Man_t, 1 );
memset( p, 0, sizeof(Aig_Man_t) );
p->pParam = &p->Param;
p->nTravIds = 1;
p->nPatsMax = 20;
p->nTravIds = 1;
p->nPatsMax = 25;
// set the defaults
*p->pParam = *pParam;
// start memory managers
@ -84,6 +84,8 @@ Aig_Man_t * Aig_ManStart( Aig_Param_t * pParam )
// initialize other variables
p->vFanouts = Vec_PtrAlloc( 10 );
p->vToReplace = Vec_PtrAlloc( 10 );
p->vClassTemp = Vec_IntAlloc( 10 );
p->vPats = Vec_PtrAlloc( p->nPatsMax );
return p;
}
@ -132,6 +134,9 @@ void Aig_ManStop( Aig_Man_t * p )
if ( p->vFanFans0 ) Vec_PtrFree( p->vFanFans0 );
if ( p->vFanFans1 ) Vec_PtrFree( p->vFanFans1 );
if ( p->vClasses ) Vec_VecFree( p->vClasses );
// patterns
if ( p->vPats ) Vec_PtrFree( p->vPats );
if ( p->pPatMask ) Aig_PatternFree( p->pPatMask );
// nodes
Aig_MemFixedStop( p->mmNodes, 0 );
Vec_PtrFree( p->vNodes );
@ -140,6 +145,7 @@ void Aig_ManStop( Aig_Man_t * p )
// temporary
Vec_PtrFree( p->vFanouts );
Vec_PtrFree( p->vToReplace );
Vec_IntFree( p->vClassTemp );
Aig_TableFree( p->pTable );
free( p );
}

182
src/sat/aig/fraigClass.c
View File

@ -80,7 +80,7 @@ Vec_Vec_t * Aig_ManDeriveClassesFirst( Aig_Man_t * p, Aig_SimInfo_t * pInfo )
}
}
stmm_free_table( tSim2Node );
/*
// print the classes
{
Vec_Ptr_t * vVec;
@ -93,6 +93,8 @@ Vec_Vec_t * Aig_ManDeriveClassesFirst( Aig_Man_t * p, Aig_SimInfo_t * pInfo )
printf( "%d ", Vec_PtrSize(vVec) );
printf( "\n" );
}
*/
printf( "Classes = %6d. Pairs = %6d.\n", Vec_VecSize(vClasses), Vec_VecSizeSize(vClasses) - Vec_VecSize(vClasses) );
return vClasses;
}
@ -115,14 +117,86 @@ unsigned Aig_ManHashKey( unsigned * pData, int nWords, bool fPhase )
uKey = 0;
if ( fPhase )
for ( i = 0; i < nWords; i++ )
uKey ^= Primes[i%10] * pData[i];
uKey ^= i * Primes[i%10] * pData[i];
else
for ( i = 0; i < nWords; i++ )
uKey ^= Primes[i%10] * ~pData[i];
uKey ^= i * Primes[i%10] * ~pData[i];
return uKey;
}
/**Function*************************************************************
Synopsis [Splits the equivalence class.]
Description [Given an equivalence class (vClass) and the simulation info,
split the class into two based on the info.]
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_ManSplitClass( Aig_Man_t * p, Aig_SimInfo_t * pInfo, Vec_Int_t * vClass, Vec_Int_t * vClass2, Aig_Pattern_t * pPat )
{
int NodeId, i, k, w;
Aig_Node_t * pRoot, * pTemp;
unsigned * pRootData, * pTempData;
assert( Vec_IntSize(vClass) > 1 );
assert( pInfo->nPatsCur == pPat->nBits );
// printf( "Class = %5d. --> ", Vec_IntSize(vClass) );
// clear storage for the new classes
Vec_IntClear( vClass2 );
// get the root member of the class
pRoot = Aig_ManNode( p, Vec_IntEntry(vClass, 0) );
pRootData = Aig_SimInfoForNode( pInfo, pRoot );
// sort the class members:
// (1) with the same siminfo as pRoot remain in vClass
// (2) nodes with other siminfo go to vClass2
k = 1;
Vec_IntForEachEntryStart( vClass, NodeId, i, 1 )
{
NodeId = Vec_IntEntry(vClass, i);
pTemp = Aig_ManNode( p, NodeId );
pTempData = Aig_SimInfoForNode( pInfo, pTemp );
if ( pRoot->fPhase == pTemp->fPhase )
{
for ( w = 0; w < pInfo->nWords; w++ )
if ( pRootData[w] != pTempData[w] )
break;
if ( w == pInfo->nWords ) // the same info
Vec_IntWriteEntry( vClass, k++, NodeId );
else
{
Vec_IntPush( vClass2, NodeId );
// record the diffs if they are not distinguished by the first pattern
if ( ((pRootData[0] ^ pTempData[0]) & 1) == 0 )
for ( w = 0; w < pInfo->nWords; w++ )
pPat->pData[w] |= (pRootData[w] ^ pTempData[w]);
}
}
else
{
for ( w = 0; w < pInfo->nWords; w++ )
if ( pRootData[w] != ~pTempData[w] )
break;
if ( w == pInfo->nWords ) // the same info
Vec_IntWriteEntry( vClass, k++, NodeId );
else
{
Vec_IntPush( vClass2, NodeId );
// record the diffs if they are not distinguished by the first pattern
if ( ((pRootData[0] ^ ~pTempData[0]) & 1) == 0 )
for ( w = 0; w < pInfo->nWords; w++ )
pPat->pData[w] |= (pRootData[w] ^ ~pTempData[w]);
}
}
}
Vec_IntShrink( vClass, k );
// printf( "Class1 = %5d. Class2 = %5d.\n", Vec_IntSize(vClass), Vec_IntSize(vClass2) );
}
/**Function*************************************************************
Synopsis [Updates the equivalence classes using the simulation info.]
@ -135,8 +209,108 @@ unsigned Aig_ManHashKey( unsigned * pData, int nWords, bool fPhase )
SeeAlso []
***********************************************************************/
void Aig_ManUpdateClasses( Aig_Man_t * p, Aig_SimInfo_t * pInfo, Vec_Vec_t * vClasses )
int Aig_ManUpdateClasses( Aig_Man_t * p, Aig_SimInfo_t * pInfo, Vec_Vec_t * vClasses, Aig_Pattern_t * pPatMask )
{
Vec_Ptr_t * vClass;
int i, k, fSplit = 0;
assert( Vec_VecSize(vClasses) > 0 );
// collect patterns that lead to changes
Aig_PatternClean( pPatMask );
// split the classes using the new symmetry info
Vec_VecForEachLevel( vClasses, vClass, i )
{
if ( i == 0 )
continue;
// split vClass into two parts (vClass and vClassTemp)
Aig_ManSplitClass( p, pInfo, (Vec_Int_t *)vClass, p->vClassTemp, pPatMask );
// check if there is any splitting
if ( Vec_IntSize(p->vClassTemp) > 0 )
fSplit = 1;
// skip the new class if it is empty or trivial
if ( Vec_IntSize(p->vClassTemp) < 2 )
continue;
// consider replacing the current class with the new one
if ( Vec_PtrSize(vClass) == 1 )
{
assert( vClasses->pArray[i] == vClass );
vClasses->pArray[i] = p->vClassTemp;
p->vClassTemp = (Vec_Int_t *)vClass;
i--;
continue;
}
// add the new non-trival class in the end
Vec_PtrPush( (Vec_Ptr_t *)vClasses, p->vClassTemp );
p->vClassTemp = Vec_IntAlloc( 10 );
}
// free trivial classes
k = 0;
Vec_VecForEachLevel( vClasses, vClass, i )
{
assert( Vec_PtrSize(vClass) > 0 );
if ( Vec_PtrSize(vClass) == 1 )
Vec_PtrFree(vClass);
else
vClasses->pArray[k++] = vClass;
}
Vec_PtrShrink( (Vec_Ptr_t *)vClasses, k );
// catch the patterns which led to splitting
printf( "Classes = %6d. Pairs = %6d. Patterns = %3d.\n",
Vec_VecSize(vClasses),
Vec_VecSizeSize(vClasses) - Vec_VecSize(vClasses),
Vec_PtrSize(p->vPats) );
return fSplit;
}
/**Function*************************************************************
Synopsis [Collects useful patterns.]
Description [If the flag fAddToVector is 1, creates and adds new patterns
to the internal storage of patterns.]
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_ManCollectPatterns( Aig_Man_t * p, Aig_SimInfo_t * pInfo, Aig_Pattern_t * pMask, Vec_Ptr_t * vPats )
{
Aig_SimInfo_t * pInfoRes = p->pInfo;
Aig_Pattern_t * pPatNew;
Aig_Node_t * pNode;
int i, k;
assert( Aig_InfoHasBit(pMask->pData, 0) == 0 );
for ( i = 0; i < pMask->nBits; i++ )
{
if ( vPats && Vec_PtrSize(vPats) >= p->nPatsMax )
break;
if ( i == 0 || Aig_InfoHasBit(pMask->pData, i) )
{
// expand storage if needed
if ( pInfoRes->nPatsCur == pInfoRes->nPatsMax )
Aig_SimInfoResize( pInfoRes );
// create a new pattern
if ( vPats )
{
pPatNew = Aig_PatternAlloc( Aig_ManPiNum(p) );
Aig_PatternClean( pPatNew );
}
// go through the PIs
Aig_ManForEachPi( p, pNode, k )
{
if ( Aig_InfoHasBit( Aig_SimInfoForNode(pInfo, pNode), i ) )
{
Aig_InfoSetBit( Aig_SimInfoForPi(pInfoRes, k), pInfoRes->nPatsCur );
if ( vPats ) Aig_InfoSetBit( pPatNew->pData, k );
}
}
// store the new pattern
if ( vPats ) Vec_PtrPush( vPats, pPatNew );
// increment the number of patterns stored
pInfoRes->nPatsCur++;
}
}
}
////////////////////////////////////////////////////////////////////////

2
src/sat/aig/fraigCore.c
View File

@ -68,6 +68,8 @@ Aig_ProofType_t Aig_FraigProve( Aig_Man_t * pMan )
// create equivalence classes
Aig_EngineSimulateRandomFirst( pMan );
// reduce equivalence classes using simulation
Aig_EngineSimulateFirst( pMan );
return RetValue;
}

127
src/sat/aig/fraigEngine.c
View File

@ -28,6 +28,39 @@
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Simulates all nodes using random simulation for the first time.]
Description [Assigns the original simulation info and the storage for the
future simulation info.]
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_EngineSimulateRandomFirst( Aig_Man_t * p )
{
Aig_SimInfo_t * pInfoPi, * pInfoAll;
assert( !p->pInfo && !p->pInfoTemp );
// create random PI info
pInfoPi = Aig_SimInfoAlloc( Aig_ManPiNum(p), p->pParam->nPatsRand, 0 );
Aig_SimInfoRandom( pInfoPi );
// allocate sim info for all nodes
pInfoAll = Aig_SimInfoAlloc( Aig_ManNodeNum(p), p->pParam->nPatsRand, 1 );
// simulate though the circuit
Aig_ManSimulateInfo( p, pInfoPi, pInfoAll );
// detect classes
p->vClasses = Aig_ManDeriveClassesFirst( p, pInfoAll );
Aig_SimInfoFree( pInfoAll );
// save simulation info
p->pInfo = pInfoPi;
p->pInfoPi = Aig_SimInfoAlloc( Aig_ManPiNum(p), Aig_ManPiNum(p)+1, 0 );
p->pInfoTemp = Aig_SimInfoAlloc( Aig_ManNodeNum(p), Aig_ManPiNum(p)+1, 1 );
p->pPatMask = Aig_PatternAlloc( Aig_ManPiNum(p)+1 );
}
/**Function*************************************************************
Synopsis [Starts the simulation engine for the first time.]
@ -43,15 +76,55 @@
void Aig_EngineSimulateFirst( Aig_Man_t * p )
{
Aig_Pattern_t * pPat;
int i;
assert( Vec_PtrSize(p->vPats) == 0 );
for ( i = 0; i < p->nPatsMax; i++ )
{
pPat = Aig_PatternAlloc( Aig_ManPiNum(p) );
Aig_PatternRandom( pPat );
Vec_PtrPush( p->vPats, pPat );
if ( !Aig_EngineSimulate( p ) )
int i, Counter;
// simulate the pattern of all zeros
pPat = Aig_PatternAlloc( Aig_ManPiNum(p) );
Aig_PatternClean( pPat );
Vec_PtrPush( p->vPats, pPat );
if ( !Aig_EngineSimulate( p ) )
return;
// simulate the pattern of all ones
pPat = Aig_PatternAlloc( Aig_ManPiNum(p) );
Aig_PatternFill( pPat );
Vec_PtrPush( p->vPats, pPat );
if ( !Aig_EngineSimulate( p ) )
return;
// simulate random until the number of new patterns is reasonable
do {
// generate random PI siminfo
Aig_SimInfoRandom( p->pInfoPi );
// simulate this info
Aig_ManSimulateInfo( p, p->pInfoPi, p->pInfoTemp );
// split the classes and collect the new patterns
if ( Aig_ManUpdateClasses( p, p->pInfoTemp, p->vClasses, p->pPatMask ) )
Aig_ManCollectPatterns( p, p->pInfoTemp, p->pPatMask, NULL );
if ( Vec_VecSize(p->vClasses) == 0 )
return;
// count the number of useful patterns
Counter = Aig_PatternCount(p->pPatMask);
}
while ( Counter > p->nPatsMax/2 );
// perform targetted simulation
for ( i = 0; i < 3; i++ )
{
assert( Vec_PtrSize(p->vPats) == 0 );
// generate random PI siminfo
Aig_SimInfoRandom( p->pInfoPi );
// simulate this info
Aig_ManSimulateInfo( p, p->pInfoPi, p->pInfoTemp );
// split the classes and collect the new patterns
if ( Aig_ManUpdateClasses( p, p->pInfoTemp, p->vClasses, p->pPatMask ) )
Aig_ManCollectPatterns( p, p->pInfoTemp, p->pPatMask, p->vPats );
if ( Vec_VecSize(p->vClasses) == 0 )
return;
// simulate the remaining patters
if ( Vec_PtrSize(p->vPats) > 0 )
if ( !Aig_EngineSimulate( p ) )
return;
}
}
@ -79,51 +152,21 @@ int Aig_EngineSimulate( Aig_Man_t * p )
{
// get the pattern and create new siminfo
pPat = Vec_PtrPop(p->vPats);
assert( pPat->nBits == Aig_ManPiNum(p) );
// create the new siminfo
Aig_SimInfoFromPattern( p->pInfoPi, pPat );
// free the patter
// free the pattern
Aig_PatternFree( pPat );
// simulate this info
Aig_ManSimulateInfo( p, p->pInfoPi, p->pInfoTemp );
// split the classes and collect the new patterns
Aig_ManUpdateClasses( p, p->pInfoTemp, p->vClasses );
if ( Aig_ManUpdateClasses( p, p->pInfoTemp, p->vClasses, p->pPatMask ) )
Aig_ManCollectPatterns( p, p->pInfoTemp, p->pPatMask, p->vPats );
}
return Vec_VecSize(p->vClasses) > 0;
}
/**Function*************************************************************
Synopsis [Simulates all nodes using random simulation for the first time.]
Description [Assigns the original simulation info and the storage for the
future simulation info.]
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_EngineSimulateRandomFirst( Aig_Man_t * p )
{
Aig_SimInfo_t * pInfoPi, * pInfoAll;
assert( !p->pInfo && !p->pInfoTemp );
// create random PI info
pInfoPi = Aig_SimInfoAlloc( p->vPis->nSize, Aig_BitWordNum(p->pParam->nPatsRand), 0 );
Aig_SimInfoRandom( pInfoPi );
// allocate sim info for all nodes
pInfoAll = Aig_SimInfoAlloc( p->vNodes->nSize, pInfoPi->nWords, 1 );
// simulate though the circuit
Aig_ManSimulateInfo( p, pInfoPi, pInfoAll );
// detect classes
p->vClasses = Aig_ManDeriveClassesFirst( p, pInfoAll );
Aig_SimInfoFree( pInfoAll );
// save simulation info
p->pInfo = pInfoPi;
p->pInfoPi = Aig_SimInfoAlloc( p->vPis->nSize, Aig_BitWordNum(p->vPis->nSize), 0 );
p->pInfoTemp = Aig_SimInfoAlloc( p->vNodes->nSize, Aig_BitWordNum(p->vPis->nSize), 1 );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

55
src/sat/aig/fraigSim.c
View File

@ -80,7 +80,7 @@ void Aig_ManSimulateInfo( Aig_Man_t * p, Aig_SimInfo_t * pInfoPi, Aig_SimInfo_t
pDataAnd[k] = pData0[k] & pData1[k];
}
// derive the PO siminfo
Aig_ManForEachPi( p, pNode, i )
Aig_ManForEachPo( p, pNode, i )
{
pDataPo = Aig_SimInfoForNode( pInfoAll, pNode );
pDataAnd = Aig_SimInfoForNode( pInfoAll, Aig_NodeFanin0(pNode) );
@ -106,16 +106,17 @@ void Aig_ManSimulateInfo( Aig_Man_t * p, Aig_SimInfo_t * pInfoPi, Aig_SimInfo_t
SeeAlso []
***********************************************************************/
Aig_SimInfo_t * Aig_SimInfoAlloc( int nNodes, int nWords, int Type )
Aig_SimInfo_t * Aig_SimInfoAlloc( int nNodes, int nBits, int Type )
{
Aig_SimInfo_t * p;
p = ALLOC( Aig_SimInfo_t, 1 );
memset( p, 0, sizeof(Aig_SimInfo_t) );
p->Type = Type;
p->nNodes = nNodes;
p->nWords = nWords;
p->nPatsMax = nWords * sizeof(unsigned) * 8;
p->pData = ALLOC( unsigned, nNodes * nWords );
p->nWords = Aig_BitWordNum(nBits);
p->nPatsCur = nBits;
p->nPatsMax = p->nWords * sizeof(unsigned) * 8;
p->pData = ALLOC( unsigned, nNodes * p->nWords );
return p;
}
@ -161,7 +162,6 @@ void Aig_SimInfoRandom( Aig_SimInfo_t * p )
pData = p->pData + p->nWords * i;
*pData <<= 1;
}
p->nPatsCur = p->nPatsMax;
}
/**Function*************************************************************
@ -180,8 +180,8 @@ void Aig_SimInfoFromPattern( Aig_SimInfo_t * p, Aig_Pattern_t * pPat )
unsigned * pData;
int i, k;
assert( p->Type == 0 );
assert( p->nNodes == pPat->nBits );
for ( i = 0; i < p->nNodes; i++ )
assert( p->nPatsCur == pPat->nBits+1 );
for ( i = 0; i < p->nPatsCur; i++ )
{
// get the pointer to the bitdata for node i
pData = p->pData + p->nWords * i;
@ -192,8 +192,8 @@ void Aig_SimInfoFromPattern( Aig_SimInfo_t * p, Aig_Pattern_t * pPat )
else
for ( k = 0; k < p->nWords; k++ )
pData[k] = 0;
// flip one bit
Aig_InfoXorBit( pData, i );
// flip one bit, starting from the first pattern
if ( i ) Aig_InfoXorBit( pData, i-1 );
}
}
@ -283,6 +283,22 @@ void Aig_PatternClean( Aig_Pattern_t * pPat )
memset( pPat->pData, 0, sizeof(unsigned) * pPat->nWords );
}
/**Function*************************************************************
Synopsis [Cleans the pattern.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_PatternFill( Aig_Pattern_t * pPat )
{
memset( pPat->pData, 0xff, sizeof(unsigned) * pPat->nWords );
}
/**Function*************************************************************
Synopsis [Sets the random pattern.]
@ -301,6 +317,25 @@ void Aig_PatternRandom( Aig_Pattern_t * pPat )
pPat->pData[i] = ((((unsigned)rand()) << 24) ^ (((unsigned)rand()) << 12) ^ ((unsigned)rand()));
}
/**Function*************************************************************
Synopsis [Counts the number of 1s in the pattern.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Aig_PatternCount( Aig_Pattern_t * pPat )
{
int i, Counter = 0;
for ( i = 0; i < pPat->nBits; i++ )
Counter += Aig_InfoHasBit( pPat->pData, i );
return Counter;
}
/**Function*************************************************************
Synopsis [Deallocates the pattern.]

454
src/sat/aig/rwrTruth.c Normal file
View File

@ -0,0 +1,454 @@
/**CFile****************************************************************
FileName [rwrTruth.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [And-Inverter Graph package.]
Synopsis []
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: rwrTruth.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "aig.h"
/* The code in this file was written with portability to 64-bits in mind.
The type "unsigned" is assumed to be 32-bit on any platform.
*/
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
#define ABCTMAX 8 // the max number of vars
typedef struct Aig_Truth_t_ Aig_Truth_t;
struct Aig_Truth_t_
{
short nVars; // the number of variables
short nWords; // the number of 32-bit words
unsigned Truth[1<<(ABCTMAX-5)]; // the truth table
unsigned Cofs[2][1<<(ABCTMAX-6)]; // the truth table of cofactors
unsigned Data[4][1<<(ABCTMAX-7)]; // the truth table of cofactors
short Counts[ABCTMAX][2]; // the minterm counters
Aig_Node_t * pLeaves[ABCTMAX]; // the pointers to leaves
Aig_Man_t * pMan; // the AIG manager
};
static void Aig_TruthCount( Aig_Truth_t * p );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Creates the function given the truth table.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Truth_t * Aig_TruthCreate( int nVars, unsigned * pTruth, Aig_Node_t ** pLeaves )
{
Aig_Truth_t * p;
int i;
p = ALLOC( Aig_Truth_t, 1 );
memset( p, 0, sizeof(Aig_Truth_t) );
p->nVars = nVars;
p->nWords = (nVars < 5)? 1 : (1 << (nVars-5));
for ( i = 0; i < p->nWords; i++ )
p->Truth[i] = pTruth[i];
if ( nVars < 5 )
p->Truth[0] &= (~0u >> (32-(1<<nVars)));
for ( i = 0; i < p->nVars; i++ )
p->pLeaves[i] = pLeaves[i];
Aig_TruthCount( p );
return p;
}
/**Function*************************************************************
Synopsis [Counts the number of miterms in the cofactors.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline int Aig_WordCountOnes( unsigned val )
{
val = (val & 0x55555555) + ((val>>1) & 0x55555555);
val = (val & 0x33333333) + ((val>>2) & 0x33333333);
val = (val & 0x0F0F0F0F) + ((val>>4) & 0x0F0F0F0F);
val = (val & 0x00FF00FF) + ((val>>8) & 0x00FF00FF);
return (val & 0x0000FFFF) + (val>>8);
}
/**Function*************************************************************
Synopsis [Counts the number of miterms in the cofactors.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_TruthCount( Aig_Truth_t * p )
{
static unsigned Masks[5][2] = {
{ 0x33333333, 0xAAAAAAAA },
{ 0x55555555, 0xCCCCCCCC },
{ 0x0F0F0F0F, 0xF0F0F0F0 },
{ 0x00FF00FF, 0xFF00FF00 },
{ 0x0000FFFF, 0xFFFF0000 }
};
int i, k;
assert( p->Counts[0][0] == 0 && p->Counts[0][1] == 0 );
for ( i = 0; i < p->nVars; i++ )
{
p->Counts[i][0] = p->Counts[i][1] = 0;
if ( i < 5 )
{
for ( k = 0; k < p->nWords; k++ )
{
p->Counts[i][0] += Aig_WordCountOnes( p->Truth[k] & Masks[i][0] );
p->Counts[i][1] += Aig_WordCountOnes( p->Truth[k] & Masks[i][1] );
}
}
else
{
for ( k = 0; k < p->nWords; k++ )
if ( i & (1 << (k-5)) )
p->Counts[i][1] += Aig_WordCountOnes( p->Truth[k] );
else
p->Counts[i][0] += Aig_WordCountOnes( p->Truth[k] );
}
}
/*
// normalize the variables
for ( i = 0; i < p->nVars; i++ )
if ( p->Counts[i][0] > p->Counts[i][1] )
{
k = p->Counts[i][0];
p->Counts[i][0] = p->Counts[i][1];
p->Counts[i][1] = k;
p->pLeaves[i] = Aig_Not( p->pLeaves[i] );
}
*/
}
/**Function*************************************************************
Synopsis [Extracts one part of the bitstring.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline unsigned Aig_WordGetPart( unsigned * p, int Start, int Size )
{
return (p[Start/5] >> (Start%32)) & (~0u >> (32-Size));
}
/**Function*************************************************************
Synopsis [Inserts one part of the bitstring.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void Aig_WordSetPart( unsigned * p, int Start, unsigned Part )
{
p[Start/5] |= (Part << (Start%32));
}
/**Function*************************************************************
Synopsis [Computes the cofactor with respect to one variable.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_TruthCofactor( int Var, int Pol, int nVars, unsigned * pTruth, unsigned * pResult )
{
if ( Var < 5 )
{
int nPartSize = ( 1 << Var );
int nParts = ( 1 << (nVars-Var-1) );
unsigned uPart;
int i;
for ( i = 0; i < nParts; i++ )
{
uPart = Aig_WordGetPart( pTruth, (2*i+Pol)*nPartSize, nPartSize );
Aig_WordSetPart( pResult, i*nPartSize, uPart );
}
if ( nVars <= 5 )
pResult[0] &= (~0u >> (32-(1<<(nVars-1))));
}
else
{
int nWords = (1 << (nVars-5));
int i, k = 0;
for ( i = 0; i < nWords; i++ )
if ( (i & (1 << (Var-5))) == Pol )
pResult[k++] = pTruth[i];
assert( k == nWords/2 );
}
}
/**Function*************************************************************
Synopsis [Computes the BDD of the truth table.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
DdNode * Aig_TruthToBdd_rec( DdManager * dd, unsigned * pTruth, int Shift, int nVars, int iVar )
{
DdNode * bCof0, * bCof1, * bRes;
if ( nVars == 1 )
return Cudd_NotCond( Cudd_ReadOne(dd), !Aig_WordGetPart(pTruth, Shift, 1) );
if ( nVars == 3 )
{
unsigned char * pChar = ((char *)pTruth) + Shift/8;
assert( Shift % 8 == 0 );
if ( *pChar == 0 )
return Cudd_ReadLogicZero(dd);
if ( *pChar == 0xFF )
return Cudd_ReadOne(dd);
}
if ( nVars == 5 )
{
unsigned * pWord = pTruth + Shift/32;
assert( Shift % 32 == 0 );
if ( *pWord == 0 )
return Cudd_ReadLogicZero(dd);
if ( *pWord == 0xFFFFFFFF )
return Cudd_ReadOne(dd);
}
bCof0 = Aig_TruthToBdd_rec( dd, pTruth, Shift, nVars-1, iVar+1 ); Cudd_Ref( bCof0 );
bCof1 = Aig_TruthToBdd_rec( dd, pTruth, Shift + (1 << (nVars-1)), nVars-1, iVar+1 ); Cudd_Ref( bCof1 );
bRes = Cudd_bddIte( dd, Cudd_bddIthVar(dd, iVar), bCof1, bCof0 ); Cudd_Ref( bRes );
Cudd_RecursiveDeref( dd, bCof0 );
Cudd_RecursiveDeref( dd, bCof1 );
Cudd_Deref( bRes );
return bRes;
}
/**Function*************************************************************
Synopsis [Computes the BDD of the truth table.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
DdNode * Aig_TruthToBdd( DdManager * dd, Aig_Truth_t * p )
{
return Aig_TruthToBdd_rec( dd, p->Truth, 0, p->nVars, 0 );
}
/**Function*************************************************************
Synopsis [Compare bistrings.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline int Aig_WordCompare( unsigned * p0, unsigned * p1, int nWords )
{
int i;
for ( i = 0; i < nWords; i++ )
if ( p0[i] != p1[i] )
return 0;
return 1;
}
/**Function*************************************************************
Synopsis [Compare bistrings.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline int Aig_WordCompareCompl( unsigned * p0, unsigned * p1, int nWords )
{
int i;
for ( i = 0; i < nWords; i++ )
if ( p0[i] != ~p1[i] )
return 0;
return 1;
}
/**Function*************************************************************
Synopsis [Computes the cofactor with respect to one variable.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_TruthReplaceByCofactor( Aig_Truth_t * p, int iVar, unsigned * pTruth )
{
}
/**Function*************************************************************
Synopsis [Computes the cofactor with respect to one variable.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Node_t * Aig_TruthDecompose( Aig_Truth_t * p )
{
Aig_Node_t * pVar;
int nOnesCof = ( 1 << (p->nVars-1) );
int nWordsCof = (p->nWords == 1 ? 1 : p->nWords/2);
int i;
// check for constant function
if ( p->nVars == 0 )
return Aig_NotCond( Aig_ManConst1(p->pMan), (p->Truth[0]&1)==0 );
// count the number of minterms in the cofactors
Aig_TruthCount( p );
// remove redundant variables and EXORs
for ( i = p->nVars - 1; i >= 0; i-- )
{
if ( p->Counts[i][0] == p->Counts[i][1] )
{
// compute cofactors
Aig_TruthCofactor( i, 0, p->nVars, p->Truth, p->Cofs[0] );
Aig_TruthCofactor( i, 1, p->nVars, p->Truth, p->Cofs[1] );
if ( Aig_WordCompare( p->Cofs[0], p->Cofs[1], nWordsCof ) )
{ // equal
// remove redundant variable
Aig_TruthReplaceByCofactor( p, i, p->Cofs[0] );
return Aig_TruthDecompose( p );
}
}
// check the case of EXOR
if ( p->Counts[i][0] == nOnesCof - p->Counts[i][1] )
{
// compute cofactors
Aig_TruthCofactor( i, 0, p->nVars, p->Truth, p->Cofs[0] );
Aig_TruthCofactor( i, 1, p->nVars, p->Truth, p->Cofs[1] );
if ( Aig_WordCompareCompl( p->Cofs[0], p->Cofs[1], nWordsCof ) )
{ // equal
pVar = p->pLeaves[i];
// remove redundant variable
Aig_TruthReplaceByCofactor( p, i, p->Cofs[0] );
// F = x' * F0 + x * F1 = x <+> F0 assuming that F0 == ~F1
return Aig_Xor( p->pMan, pVar, Aig_TruthDecompose( p ) );
}
}
}
// process variables with constant cofactors
for ( i = p->nVars - 1; i >= 0; i-- )
{
if ( p->Counts[i][0] != 0 && p->Counts[i][1] != 0 &&
p->Counts[i][0] != nOnesCof && p->Counts[i][1] != nOnesCof )
continue;
pVar = p->pLeaves[i];
if ( p->Counts[i][0] == 0 )
{
Aig_TruthCofactor( i, 1, p->nVars, p->Truth, p->Cofs[1] );
// remove redundant variable
Aig_TruthReplaceByCofactor( p, i, p->Cofs[1] );
// F = x' * 0 + x * F1 = x * F1
return Aig_And( p->pMan, pVar, Aig_TruthDecompose( p ) );
}
if ( p->Counts[i][1] == 0 )
{
Aig_TruthCofactor( i, 0, p->nVars, p->Truth, p->Cofs[0] );
// remove redundant variable
Aig_TruthReplaceByCofactor( p, i, p->Cofs[0] );
// F = x' * F0 + x * 0 = x' * F0
return Aig_And( p->pMan, Aig_Not(pVar), Aig_TruthDecompose( p ) );
}
if ( p->Counts[i][0] == nOnesCof )
{
Aig_TruthCofactor( i, 1, p->nVars, p->Truth, p->Cofs[1] );
// remove redundant variable
Aig_TruthReplaceByCofactor( p, i, p->Cofs[1] );
// F = x' * 1 + x * F1 = x' + F1
return Aig_Or( p->pMan, Aig_Not(pVar), Aig_TruthDecompose( p ) );
}
if ( p->Counts[i][1] == nOnesCof )
{
Aig_TruthCofactor( i, 0, p->nVars, p->Truth, p->Cofs[0] );
// remove redundant variable
Aig_TruthReplaceByCofactor( p, i, p->Cofs[0] );
// F = x' * F0 + x * 1 = x + F0
return Aig_Or( p->pMan, pVar, Aig_TruthDecompose( p ) );
}
assert( 0 );
}
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

108
src/sat/csat/csat_apis.c
View File

@ -34,6 +34,7 @@ struct ABC_ManagerStruct_t
Abc_Ntk_t * pNtk; // the starting ABC network
Abc_Ntk_t * pTarget; // the AIG representing the target
char * pDumpFileName; // the name of the file to dump the target network
Extra_MmFlex_t * pMmNames; // memory manager for signal names
// solving parameters
int mode; // 0 = brute-force SAT; 1 = resource-aware FRAIG
int nSeconds; // time limit for pure SAT solving
@ -76,6 +77,7 @@ ABC_Manager ABC_InitManager()
mng->pNtk->pName = util_strsav("csat_network");
mng->tName2Node = stmm_init_table(strcmp, stmm_strhash);
mng->tNode2Name = stmm_init_table(stmm_ptrcmp, stmm_ptrhash);
mng->pMmNames = Extra_MmFlexStart();
mng->vNodes = Vec_PtrAlloc( 100 );
mng->vValues = Vec_IntAlloc( 100 );
mng->nSeconds = ABC_DEFAULT_TIMEOUT;
@ -97,6 +99,7 @@ void ABC_QuitManager( ABC_Manager mng )
{
if ( mng->tNode2Name ) stmm_free_table( mng->tNode2Name );
if ( mng->tName2Node ) stmm_free_table( mng->tName2Node );
if ( mng->pMmNames ) Extra_MmFlexStop( mng->pMmNames, 0 );
if ( mng->pNtk ) Abc_NtkDelete( mng->pNtk );
if ( mng->pTarget ) Abc_NtkDelete( mng->pTarget );
if ( mng->vNodes ) Vec_PtrFree( mng->vNodes );
@ -146,9 +149,15 @@ void ABC_SetSolveOption( ABC_Manager mng, enum ABC_OptionT option )
int ABC_AddGate( ABC_Manager mng, enum GateType type, char * name, int nofi, char ** fanins, int dc_attr )
{
Abc_Obj_t * pObj, * pFanin;
char * pSop;
char * pSop, * pNewName;
int i;
// save the name in the local memory manager
pNewName = Extra_MmFlexEntryFetch( mng->pMmNames, strlen(name) + 1 );
strcpy( pNewName, name );
name = pNewName;
// consider different cases, create the node, and map the node into the name
switch( type )
{
case ABC_BPI:
@ -250,6 +259,8 @@ int ABC_AddGate( ABC_Manager mng, enum GateType type, char * name, int nofi, cha
printf( "ABC_AddGate: Unknown gate type.\n" );
break;
}
// map the name into the node
if ( stmm_insert( mng->tName2Node, name, (char *)pObj ) )
{ printf( "ABC_AddGate: The same gate \"%s\" is added twice.\n", name ); return 0; }
return 1;
@ -690,6 +701,101 @@ char * ABC_GetNodeName( ABC_Manager mng, Abc_Obj_t * pNode )
return pName;
}
/**Function*************************************************************
Synopsis [This procedure applies a rewriting script to the network.]
Description [Rewriting is performed without regard for the number of
logic levels. This corresponds to "circuit compression for formal
verification" (Per Bjesse et al, ICCAD 2004) but implemented in a more
exhaustive way than in the above paper.]
SideEffects []
SeeAlso []
***********************************************************************/
void ABC_PerformRewriting( ABC_Manager mng )
{
void * pAbc;
char Command[1000];
int clkBalan, clkResyn, clk;
int fPrintStats = 1;
int fUseResyn = 1;
// procedures to get the ABC framework and execute commands in it
extern void * Abc_FrameGetGlobalFrame();
extern void Abc_FrameReplaceCurrentNetwork( void * p, Abc_Ntk_t * pNtk );
extern int Cmd_CommandExecute( void * p, char * sCommand );
extern Abc_Ntk_t * Abc_FrameReadNtk( void * p );
// get the pointer to the ABC framework
pAbc = Abc_FrameGetGlobalFrame();
assert( pAbc != NULL );
// replace the current network by the target network
Abc_FrameReplaceCurrentNetwork( pAbc, mng->pTarget );
clk = clock();
//////////////////////////////////////////////////////////////////////////
// balance
sprintf( Command, "balance" );
if ( Cmd_CommandExecute( pAbc, Command ) )
{
fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
return;
}
clkBalan = clock() - clk;
//////////////////////////////////////////////////////////////////////////
// print stats
if ( fPrintStats )
{
sprintf( Command, "print_stats" );
if ( Cmd_CommandExecute( pAbc, Command ) )
{
fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
return;
}
}
clk = clock();
//////////////////////////////////////////////////////////////////////////
// synthesize
if ( fUseResyn )
{
sprintf( Command, "balance; rewrite -l; rewrite -lz; balance; rewrite -lz; balance" );
if ( Cmd_CommandExecute( pAbc, Command ) )
{
fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
return;
}
}
clkResyn = clock() - clk;
//////////////////////////////////////////////////////////////////////////
// print stats
if ( fPrintStats )
{
sprintf( Command, "print_stats" );
if ( Cmd_CommandExecute( pAbc, Command ) )
{
fprintf( stdout, "Cannot execute command \"%s\".\n", Command );
return;
}
}
printf( "Balancing = %6.2f sec ", (float)(clkBalan)/(float)(CLOCKS_PER_SEC) );
printf( "Rewriting = %6.2f sec ", (float)(clkResyn)/(float)(CLOCKS_PER_SEC) );
printf( "\n" );
// read the target network from the current network
mng->pTarget = Abc_NtkDup( Abc_FrameReadNtk(pAbc) );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

2
src/sat/csat/csat_apis.h
View File

@ -171,6 +171,8 @@ extern void ABC_Dump_Bench_File(ABC_Manager mng);
extern void ABC_QuitManager( ABC_Manager mng );
extern void ABC_TargetResFree( ABC_Target_ResultT * p );
extern void ABC_PerformRewriting( ABC_Manager mng );
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

2
src/sat/fraig/fraigMan.c
View File

@ -185,7 +185,7 @@ void Fraig_ManFree( Fraig_Man_t * p )
// Fraig_TablePrintStatsF( p );
// Fraig_TablePrintStatsF0( p );
}
for ( i = 0; i < p->vNodes->nSize; i++ )
if ( p->vNodes->pArray[i]->vFanins )
{

133
src/sat/fraig/fraigSat.c
View File

@ -154,6 +154,132 @@ int Fraig_ManCheckMiter( Fraig_Man_t * p )
}
/**Function*************************************************************
Synopsis [Returns 1 if pOld is in the TFI of pNew.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Fraig_MarkTfi_rec( Fraig_Man_t * pMan, Fraig_Node_t * pNode )
{
// skip the visited node
if ( pNode->TravId == pMan->nTravIds )
return 0;
pNode->TravId = pMan->nTravIds;
// skip the PI node
if ( pNode->NumPi >= 0 )
return 1;
// check the children
return Fraig_MarkTfi_rec( pMan, Fraig_Regular(pNode->p1) ) +
Fraig_MarkTfi_rec( pMan, Fraig_Regular(pNode->p2) );
}
/**Function*************************************************************
Synopsis [Returns 1 if pOld is in the TFI of pNew.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Fraig_MarkTfi2_rec( Fraig_Man_t * pMan, Fraig_Node_t * pNode )
{
// skip the visited node
if ( pNode->TravId == pMan->nTravIds )
return 0;
// skip the boundary node
if ( pNode->TravId == pMan->nTravIds-1 )
{
pNode->TravId = pMan->nTravIds;
return 1;
}
pNode->TravId = pMan->nTravIds;
// skip the PI node
if ( pNode->NumPi >= 0 )
return 1;
// check the children
return Fraig_MarkTfi2_rec( pMan, Fraig_Regular(pNode->p1) ) +
Fraig_MarkTfi2_rec( pMan, Fraig_Regular(pNode->p2) );
}
/**Function*************************************************************
Synopsis [Returns 1 if pOld is in the TFI of pNew.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Fraig_MarkTfi3_rec( Fraig_Man_t * pMan, Fraig_Node_t * pNode )
{
// skip the visited node
if ( pNode->TravId == pMan->nTravIds )
return 1;
// skip the boundary node
if ( pNode->TravId == pMan->nTravIds-1 )
{
pNode->TravId = pMan->nTravIds;
return 1;
}
pNode->TravId = pMan->nTravIds;
// skip the PI node
if ( pNode->NumPi >= 0 )
return 0;
// check the children
return Fraig_MarkTfi3_rec( pMan, Fraig_Regular(pNode->p1) ) *
Fraig_MarkTfi3_rec( pMan, Fraig_Regular(pNode->p2) );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_VarsStudy( Fraig_Man_t * p, Fraig_Node_t * pOld, Fraig_Node_t * pNew )
{
int NumPis, NumCut, fContain;
// mark the TFI of pNew
p->nTravIds++;
NumPis = Fraig_MarkTfi_rec( p, pNew );
printf( "(%d)(%d,%d):", NumPis, pOld->Level, pNew->Level );
// check if the old is in the TFI
if ( pOld->TravId == p->nTravIds )
{
printf( "* " );
return;
}
// count the boundary of nodes in pOld
p->nTravIds++;
NumCut = Fraig_MarkTfi2_rec( p, pOld );
printf( "%d", NumCut );
// check if the new is contained in the old's support
p->nTravIds++;
fContain = Fraig_MarkTfi3_rec( p, pNew );
printf( "%c ", fContain? '+':'-' );
}
/**Function*************************************************************
Synopsis [Checks whether two nodes are functinally equivalent.]
@ -202,6 +328,7 @@ int Fraig_NodeIsEquivalent( Fraig_Man_t * p, Fraig_Node_t * pOld, Fraig_Node_t *
// get the logic cone
clk = clock();
// Fraig_VarsStudy( p, pOld, pNew );
Fraig_OrderVariables( p, pOld, pNew );
// Fraig_PrepareCones( p, pOld, pNew );
p->timeTrav += clock() - clk;
@ -223,18 +350,20 @@ if ( fVerbose )
Msat_SolverPrepare( p->pSat, p->vVarsInt );
//p->time3 += clock() - clk;
// solve under assumptions
// A = 1; B = 0 OR A = 1; B = 1
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pOld->Num, 0) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNew->Num, !fComp) );
//Msat_SolverWriteDimacs( p->pSat, "temp_fraig.cnf" );
// run the solver
clk = clock();
RetValue1 = Msat_SolverSolve( p->pSat, p->vProj, nBTLimit, nTimeLimit );
p->timeSat += clock() - clk;
//Msat_SolverWriteDimacs( p->pSat, "temp_fraig.cnf" );
if ( RetValue1 == MSAT_FALSE )
{
//p->time1 += clock() - clk;

2
src/sat/msat/msatClause.c
View File

@ -194,7 +194,7 @@ bool Msat_ClauseCreate( Msat_Solver_t * p, Msat_IntVec_t * vLits, bool fLearned,
{
Msat_SolverVarBumpActivity( p, pLits[i] );
// Msat_SolverVarBumpActivity( p, pLits[i] );
p->pFreq[ MSAT_LIT2VAR(pLits[i]) ]++;
// p->pFreq[ MSAT_LIT2VAR(pLits[i]) ]++;
}
}

4
src/sat/msat/msatSolverCore.c
View File

@ -140,8 +140,8 @@ bool Msat_SolverSolve( Msat_Solver_t * p, Msat_IntVec_t * vAssumps, int nBackTra
int64 nConflictsOld = p->Stats.nConflicts;
int64 nDecisionsOld = p->Stats.nDecisions;
p->pFreq = ALLOC( int, p->nVarsAlloc );
memset( p->pFreq, 0, sizeof(int) * p->nVarsAlloc );
// p->pFreq = ALLOC( int, p->nVarsAlloc );
// memset( p->pFreq, 0, sizeof(int) * p->nVarsAlloc );
if ( vAssumps )
{

47
todo.txt Normal file
View File

@ -0,0 +1,47 @@
Minor things:
- add required time support
- clean end-of-line markers (CR is more preferable than CR-LF)
- mysterious Mac problem (fixed?)
- mysterious Solaris problem (fixed)
- QR's compilation problems
- add storage for internal memory for node names in the ABC_ package
- prevent node name clash between PO and internal names (i.e. [484])
- add the output of ABC version/platform in the output files
- fix gcc compiler warnings
- update CVS regularly
Major things:
- substantially improving performance of FRAIGing
(used in equivalence checking and lossless synthesis)
- developing a new (much more efficient and faster) AIG rewriting package
- implementing additional rewriting options for delay optimization
- making technology mapping applicable to very large designs by adding
on-demand cut computation currenlty available as a stand-alone command "cut"
- experimenting with yield-aware standard-cell mapping
- developing a hybrid mapper for arbitrary programmable macrocell
architecture specified using a configuration file (this mapper should work
for both cell-evalution and mainstream FPGA mapping)
- developing incremental retiming and incremental integrated sequential
synthesis
- developing sequential verification combined with integrated sequential
synthesis
- add hierarchical BLIF interface (for designs with black boxes)