mirror of https://github.com/YosysHQ/abc.git
Integration of timing manager.
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@ -826,7 +826,7 @@ extern Gia_Man_t * Gia_ManDupDfsCone( Gia_Man_t * p, Gia_Obj_t * pObj );
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extern Gia_Man_t * Gia_ManDupDfsLitArray( Gia_Man_t * p, Vec_Int_t * vLits );
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extern Gia_Man_t * Gia_ManDupNormalize( Gia_Man_t * p );
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extern Gia_Man_t * Gia_ManDupUnnomalize( Gia_Man_t * p );
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extern Gia_Man_t * Gia_ManDupWithHierarchy( Gia_Man_t * p );
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extern Gia_Man_t * Gia_ManDupWithHierarchy( Gia_Man_t * p, Vec_Int_t ** pvNodes );
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extern Gia_Man_t * Gia_ManDupTrimmed( Gia_Man_t * p, int fTrimCis, int fTrimCos, int fDualOut, int OutValue );
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extern Gia_Man_t * Gia_ManDupOntop( Gia_Man_t * p, Gia_Man_t * p2 );
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extern Gia_Man_t * Gia_ManDupWithNewPo( Gia_Man_t * p1, Gia_Man_t * p2 );
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@ -701,13 +701,14 @@ Gia_Man_t * Gia_AigerReadFromMemory( char * pContents, int nFileSize, int fSkipS
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if ( fHieOnly )
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{
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Tim_ManPrint( (Tim_Man_t *)pNew->pManTime );
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// Tim_ManPrint( (Tim_Man_t *)pNew->pManTime );
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if ( Abc_FrameReadLibBox() == NULL )
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printf( "Cannot create TIM manager because box library is not available.\n" );
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else
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{
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Tim_ManCreate( (Tim_Man_t *)pNew->pManTime, Abc_FrameReadLibBox(), pNew->vInArrs, pNew->vOutReqs );
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Tim_ManPrint( (Tim_Man_t *)pNew->pManTime );
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// Tim_ManPrint( (Tim_Man_t *)pNew->pManTime );
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printf( "Created timing manager using Tim_ManCreate().\n" );
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}
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}
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Vec_FltFreeP( &pNew->vInArrs );
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@ -1089,12 +1090,12 @@ void Gia_AigerWrite( Gia_Man_t * pInit, char * pFileName, int fWriteSymbols, int
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fprintf( pFile, "i" );
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Gia_FileWriteBufferSize( pFile, 4*Tim_ManPiNum((Tim_Man_t *)p->pManTime) );
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assert( Vec_FltSize(vArrTimes) == Tim_ManPiNum((Tim_Man_t *)p->pManTime) );
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fwrite( Vec_FltArray(vArrTimes), 1, 4*Gia_ManPiNum(p), pFile );
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fwrite( Vec_FltArray(vArrTimes), 1, 4*Tim_ManPiNum((Tim_Man_t *)p->pManTime), pFile );
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fprintf( pFile, "o" );
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Gia_FileWriteBufferSize( pFile, 4*Tim_ManPoNum((Tim_Man_t *)p->pManTime) );
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assert( Vec_FltSize(vReqTimes) == Tim_ManPoNum((Tim_Man_t *)p->pManTime) );
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fwrite( Vec_FltArray(vReqTimes), 1, 4*Gia_ManPoNum(p), pFile );
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fwrite( Vec_FltArray(vReqTimes), 1, 4*Tim_ManPoNum((Tim_Man_t *)p->pManTime), pFile );
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Vec_FltFree( vArrTimes );
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Vec_FltFree( vReqTimes );
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@ -1182,11 +1182,13 @@ Vec_Int_t * Gia_ManDupFindOrderWithHie( Gia_Man_t * p )
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curCo = 0;
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for ( i = 0; i < Tim_ManBoxNum(pTime); i++ )
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{
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//printf( "Box %d:\n", i );
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// add internal nodes
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for ( k = 0; k < Tim_ManBoxInputNum(pTime, i); k++ )
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{
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pObj = Gia_ManPo( p, curCo + k );
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//Gia_ObjPrint( p, pObj );
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//printf( "Fanin " );
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//Gia_ObjPrint( p, Gia_ObjFanin0(pObj) );
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Gia_ManDupFindOrderWithHie_rec( p, Gia_ObjFanin0(pObj), vNodes );
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}
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@ -1201,7 +1203,9 @@ Vec_Int_t * Gia_ManDupFindOrderWithHie( Gia_Man_t * p )
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for ( k = 0; k < Tim_ManBoxOutputNum(pTime, i); k++ )
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{
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pObj = Gia_ManPi( p, curCi + k );
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//Gia_ObjPrint( p, pObj );
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Vec_IntPush( vNodes, Gia_ObjId(p, pObj) );
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Gia_ObjSetTravIdCurrent( p, pObj );
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}
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curCi += Tim_ManBoxOutputNum(pTime, i);
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}
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@ -1236,7 +1240,7 @@ Vec_Int_t * Gia_ManDupFindOrderWithHie( Gia_Man_t * p )
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SeeAlso []
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***********************************************************************/
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Gia_Man_t * Gia_ManDupWithHierarchy( Gia_Man_t * p )
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Gia_Man_t * Gia_ManDupWithHierarchy( Gia_Man_t * p, Vec_Int_t ** pvNodes )
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{
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Vec_Int_t * vNodes;
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Gia_Man_t * pNew;
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@ -1260,7 +1264,10 @@ Gia_Man_t * Gia_ManDupWithHierarchy( Gia_Man_t * p )
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else assert( 0 );
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}
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Gia_ManSetRegNum( pNew, Gia_ManRegNum(p) );
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Vec_IntFree( vNodes );
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if ( pvNodes )
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*pvNodes = vNodes;
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else
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Vec_IntFree( vNodes );
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return pNew;
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}
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@ -594,8 +594,8 @@ Gia_Man_t * Gia_ManFromIf( If_Man_t * pIfMan )
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pNew->nOffset = iOffset;
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Gia_ManCleanMark0( pNew );
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// assert( iOffset == Gia_ManObjNum(pNew) + nItems );
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if ( pIfMan->pManTim )
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pNew->pManTime = Tim_ManDup( pIfMan->pManTim, 0 );
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// if ( pIfMan->pManTim )
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// pNew->pManTime = Tim_ManDup( pIfMan->pManTim, 0 );
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// verify that COs have mapping
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{
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Gia_Obj_t * pObj;
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@ -608,6 +608,110 @@ Gia_Man_t * Gia_ManFromIf( If_Man_t * pIfMan )
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return pNew;
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}
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/**Function*************************************************************
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Synopsis [Verifies mapping.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Gia_ManMappingVerify_rec( Gia_Man_t * p, Gia_Obj_t * pObj )
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{
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int Id, iFan, k, Result = 1;
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if ( Gia_ObjIsTravIdCurrent(p, pObj) )
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return 1;
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Gia_ObjSetTravIdCurrent(p, pObj);
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if ( !Gia_ObjIsAnd(pObj) )
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return 1;
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if ( !Gia_ObjIsLut(p, Gia_ObjId(p, pObj)) )
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{
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Abc_Print( -1, "Gia_ManMappingVerify: Internal node %d does not have mapping.\n", Gia_ObjId(p, pObj) );
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return 0;
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}
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Id = Gia_ObjId(p, pObj);
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Gia_LutForEachFanin( p, Id, iFan, k )
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if ( Result )
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Result &= Gia_ManMappingVerify_rec( p, Gia_ManObj(p, iFan) );
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return Result;
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}
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void Gia_ManMappingVerify( Gia_Man_t * p )
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{
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Gia_Obj_t * pObj, * pFanin;
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int i, Result = 1;
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/*
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if ( p->pMapping )
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{
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assert( p->nOffset != 0 );
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Vec_IntFreeP( p->vMapping );
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Vec_IntAlloc( p->vMapping, p->nOffset );
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memmove( Vec_IntArray(p->vMapping), p->pMapping, p->nOffset );
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}
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assert( p->vMapping );
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*/
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assert( p->pMapping );
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Gia_ManIncrementTravId( p );
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Gia_ManForEachCo( p, pObj, i )
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{
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pFanin = Gia_ObjFanin0(pObj);
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if ( !Gia_ObjIsAnd(pFanin) )
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continue;
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if ( !Gia_ObjIsLut(p, Gia_ObjId(p, pFanin)) )
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{
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Abc_Print( -1, "Gia_ManMappingVerify: CO driver %d does not have mapping.\n", Gia_ObjId(p, pFanin) );
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Result = 0;
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continue;
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}
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Result &= Gia_ManMappingVerify_rec( p, pFanin );
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}
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// if ( Result && Gia_NtkIsRoot(p) )
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// Abc_Print( 1, "Mapping verified correctly.\n" );
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}
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/**Function*************************************************************
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Synopsis [Transfers mapping from hie GIA to normalized GIA.]
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Description [Hie GIA (pGia) points to normalized GIA (p).]
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Gia_ManTransferMapping( Gia_Man_t * pGia, Gia_Man_t * p )
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{
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Gia_Obj_t * pObj;
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int i, k, iFan;
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assert( pGia->pMapping != NULL );
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Gia_ManMappingVerify( pGia );
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Vec_IntFreeP( &p->vMapping );
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p->vMapping = Vec_IntAlloc( 2 * Gia_ManObjNum(p) );
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Vec_IntFill( p->vMapping, Gia_ManObjNum(p), 0 );
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Gia_ManForEachLut( pGia, i )
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{
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assert( !Abc_LitIsCompl(Gia_ObjValue(Gia_ManObj(pGia, i))) );
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pObj = Gia_ManObj( p, Abc_Lit2Var(Gia_ObjValue(Gia_ManObj(pGia, i))) );
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Vec_IntWriteEntry( p->vMapping, Gia_ObjId(p, pObj), Vec_IntSize(p->vMapping) );
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Vec_IntPush( p->vMapping, Gia_ObjLutSize(pGia, i) );
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Gia_LutForEachFanin( pGia, i, iFan, k )
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Vec_IntPush( p->vMapping, Abc_Lit2Var(Gia_ObjValue(Gia_ManObj(pGia, iFan))) );
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Vec_IntPush( p->vMapping, Gia_ObjId(p, pObj) );
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}
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// create standard mapping
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assert( p->pMapping == NULL );
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p->pMapping = Vec_IntArray( p->vMapping );
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p->vMapping->pArray = NULL;
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p->nOffset = Vec_IntSize(p->vMapping);
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p->vMapping->nSize = 0;
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Gia_ManMappingVerify( p );
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}
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/**Function*************************************************************
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Synopsis [Interface of LUT mapping package.]
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@ -624,15 +728,20 @@ Gia_Man_t * Gia_ManPerformMapping( Gia_Man_t * p, void * pp )
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Gia_Man_t * pNew;
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If_Man_t * pIfMan;
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If_Par_t * pPars = (If_Par_t *)pp;
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Vec_Int_t * vNodes = NULL;
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// reconstruct GIA according to the hierarchy manager
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if ( p->pManTime )
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p = Gia_ManDupWithHierarchy( p );
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{
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pNew = Gia_ManDupWithHierarchy( p, &vNodes );
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pNew->pManTime = p->pManTime; p->pManTime = NULL;
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p = pNew;
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}
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else
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p = Gia_ManDup( p );
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Vec_IntFreeP( &vNodes );
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// set the arrival times
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assert( pPars->pTimesArr == NULL );
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pPars->pTimesArr = ABC_ALLOC( float, Gia_ManCiNum(p) );
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memset( pPars->pTimesArr, 0, sizeof(float) * Gia_ManCiNum(p) );
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pPars->pTimesArr = ABC_CALLOC( float, Gia_ManCiNum(p) );
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// translate into the mapper
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pIfMan = Gia_ManToIf( p, pPars );
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if ( pIfMan == NULL )
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@ -659,7 +768,14 @@ Gia_Man_t * Gia_ManPerformMapping( Gia_Man_t * p, void * pp )
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// unmap in case of SOP balancing
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// if ( pIfMan->pPars->fDelayOpt )
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// Vec_IntFreeP( &pNew->vMapping );
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return pNew;
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// return the original (unmodified by the mapper) timing manager
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pNew->pManTime = p->pManTime; p->pManTime = NULL;
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Gia_ManStop( p );
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// normalize and transfer mapping
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p = Gia_ManDupNormalize( pNew );
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Gia_ManTransferMapping( pNew, p );
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Gia_ManStop( pNew );
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return p;
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}
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////////////////////////////////////////////////////////////////////////
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@ -195,6 +195,7 @@ void Tim_ManCreate( Tim_Man_t * p, void * pLib, Vec_Flt_t * vInArrs, Vec_Flt_t *
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int i, k;
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assert( p->vDelayTables == NULL );
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p->vDelayTables = Vec_PtrStart( Vec_PtrSize(pLibBox->vBoxes) );
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if ( p->vBoxes )
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Tim_ManForEachBox( p, pBox, i )
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{
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if ( pBox->iDelayTable == -1 )
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