luke
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abc
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initial commit of public abc

This commit is contained in:
Alan Mishchenko 2010-11-01 01:35:04 -07:00
parent f0e77f6797
commit 6130e39b18
1119 changed files with 74755 additions and 20648 deletions
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41
.hgignore Normal file
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@ -0,0 +1,41 @@
syntax:glob
DebugLib/
DebugExe/
DebugExt/
ReleaseLib/
ReleaseExe/
ReleaseExt/
_TEST/
lib/
docs/
src/ext/
*~
*.orig
*.[od]
*.ncb
*.opt
*.plg
*.zip
abcspaceext.dsw
abcext.dsp
*.pyc
src/python/build
src/python/bdist
src/python/pyabc.py
src.python/pyabc_wrap.*
syntax: regexp
^libabc.a$
^abc$

16
Makefile
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@ -8,7 +8,7 @@ PROG := abc
MODULES := \ MODULES := \
src/base/abc src/base/abci src/base/cmd \ src/base/abc src/base/abci src/base/cmd \
src/base/io src/base/main src/base/ver \ src/base/io src/base/main src/base/ver src/base/dummy src/base/dummy2 \
src/bdd/cudd src/bdd/dsd src/bdd/epd src/bdd/mtr \ src/bdd/cudd src/bdd/dsd src/bdd/epd src/bdd/mtr \
src/bdd/parse src/bdd/reo src/bdd/cas \ src/bdd/parse src/bdd/reo src/bdd/cas \
src/map/fpga src/map/mapper src/map/mio src/map/super \ src/map/fpga src/map/mapper src/map/mio src/map/super \
@ -26,19 +26,25 @@ MODULES := \
src/aig/bdc src/aig/bar src/aig/ntl src/aig/nwk \ src/aig/bdc src/aig/bar src/aig/ntl src/aig/nwk \
src/aig/mfx src/aig/tim src/aig/saig src/aig/bbr \ src/aig/mfx src/aig/tim src/aig/saig src/aig/bbr \
src/aig/int src/aig/dch src/aig/ssw src/aig/cgt \ src/aig/int src/aig/dch src/aig/ssw src/aig/cgt \
src/aig/cec src/aig/gia src/aig/bbl src/aig/live src/aig/cec src/aig/gia src/aig/bbl src/aig/live \
src/aig/llb \
src/python \
src/ext/_sky src/ext/_rti src/ext/_nal src/ext/_bat src/ext/_lxp
all: $(PROG)
default: $(PROG) default: $(PROG)
#OPTFLAGS := -DNDEBUG -O3 -DLIN #OPTFLAGS := -DNDEBUG -O3 -DLIN
#OPTFLAGS := -DNDEBUG -O3 -DLIN64 #OPTFLAGS := -DNDEBUG -O3 -DLIN64
#OPTFLAGS := -g -O -DLIN #OPTFLAGS := -g -O -DLIN -m32
OPTFLAGS := -g -O -DLIN64 OPTFLAGS := -g -O -DLIN64 -DSIZEOF_VOID_P=8 -DSIZEOF_LONG=8 -DSIZEOF_INT=4 -DABC_NAMESPACE=xxx
CFLAGS += -Wall -Wno-unused-function $(OPTFLAGS) $(patsubst %, -I%, $(MODULES)) CFLAGS += -Wall -Wno-unused-function $(OPTFLAGS) $(patsubst %, -I%, $(MODULES))
CXXFLAGS += $(CFLAGS) CXXFLAGS += $(CFLAGS)
LIBS := -ldl -rdynamic -lreadline -ltermcap #LIBS := -m32 -ldl -rdynamic -lreadline -ltermcap
LIBS := -ldl /usr/lib64/libreadline.a /usr/lib64/libncurses.a -rdynamic
SRC := SRC :=
GARBAGE := core core.* *.stackdump ./tags $(PROG) GARBAGE := core core.* *.stackdump ./tags $(PROG)

7
abc.rc
View File

@ -1,10 +1,10 @@
# global parameters # global parameters
set check # checks intermediate networks set check # checks intermediate networks
#set checkfio # prints warnings when fanins/fanouts are duplicated #set checkfio # prints warnings when fanins/fanouts are duplicated
set checkread # checks new networks after reading from file #unset checkread # does not check new networks after reading from file
#set backup # saves backup networks retrived by "undo" and "recall" #set backup # saves backup networks retrived by "undo" and "recall"
#set savesteps 1 # sets the maximum number of backup networks to save #set savesteps 1 # sets the maximum number of backup networks to save
set progressbar # display the progress bar #set progressbar # display the progress bar
# program names for internal calls # program names for internal calls
set dotwin dot.exe set dotwin dot.exe
@ -20,6 +20,9 @@ set capounix MetaPl-Capo10.1
set gnuplotwin wgnuplot.exe set gnuplotwin wgnuplot.exe
set gnuplotunix gnuplot set gnuplotunix gnuplot
# Niklas Een's commands
load_plugin C:\_projects\abc\_TEST\bip\bip_2010-10-19.exe "BIP"
# standard aliases # standard aliases
alias b balance alias b balance
alias cg clockgate alias cg clockgate

8
abcexe.dsp
View File

@ -42,7 +42,7 @@ RSC=rc.exe
# PROP Ignore_Export_Lib 0 # PROP Ignore_Export_Lib 0
# PROP Target_Dir "" # PROP Target_Dir ""
# ADD BASE CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /c # ADD BASE CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /c
# ADD CPP /nologo /W3 /GX /O2 /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /I "src/aig/bbl" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /c # ADD CPP /nologo /MD /W3 /GX /O2 /I "src/ext/ext" /I "src/misc/ext" /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/cov" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /I "src/aig/bbl" /I "src/aig/llb" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /c
# ADD BASE RSC /l 0x409 /d "NDEBUG" # ADD BASE RSC /l 0x409 /d "NDEBUG"
# ADD RSC /l 0x409 /d "NDEBUG" # ADD RSC /l 0x409 /d "NDEBUG"
BSC32=bscmake.exe BSC32=bscmake.exe
@ -50,7 +50,7 @@ BSC32=bscmake.exe
# ADD BSC32 /nologo # ADD BSC32 /nologo
LINK32=link.exe LINK32=link.exe
# ADD BASE LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /machine:I386 # ADD BASE LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /machine:I386
# ADD LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib lib\abcr.lib /nologo /subsystem:console /incremental:yes /debug /machine:I386 /out:"_TEST/abc.exe" # ADD LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib lib\abcr.lib lib\abcextr.lib /nologo /subsystem:console /incremental:yes /debug /machine:I386 /out:"_TEST/abc.exe"
!ELSEIF "$(CFG)" == "abcexe - Win32 Debug" !ELSEIF "$(CFG)" == "abcexe - Win32 Debug"
@ -66,7 +66,7 @@ LINK32=link.exe
# PROP Ignore_Export_Lib 0 # PROP Ignore_Export_Lib 0
# PROP Target_Dir "" # PROP Target_Dir ""
# ADD BASE CPP /nologo /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /GZ /c # ADD BASE CPP /nologo /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /GZ /c
# ADD CPP /nologo /W3 /Gm /GX /ZI /Od /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /I "src/aig/bbl" /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /GZ /c # ADD CPP /nologo /MDd /W3 /Gm /GX /ZI /Od /I "src/ext/ext" /I "src/misc/ext" /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/cov" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /I "src/aig/bbl" /I "src/aig/llb" /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /GZ /c
# ADD BASE RSC /l 0x409 /d "_DEBUG" # ADD BASE RSC /l 0x409 /d "_DEBUG"
# ADD RSC /l 0x409 /d "_DEBUG" # ADD RSC /l 0x409 /d "_DEBUG"
BSC32=bscmake.exe BSC32=bscmake.exe
@ -74,7 +74,7 @@ BSC32=bscmake.exe
# ADD BSC32 /nologo # ADD BSC32 /nologo
LINK32=link.exe LINK32=link.exe
# ADD BASE LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /debug /machine:I386 /pdbtype:sept # ADD BASE LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /debug /machine:I386 /pdbtype:sept
# ADD LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib lib\abcd.lib /nologo /subsystem:console /debug /machine:I386 /out:"_TEST/abc.exe" # ADD LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib lib\abcd.lib lib\abcextd.lib /nologo /subsystem:console /debug /machine:I386 /out:"_TEST/abc.exe"
!ENDIF !ENDIF

206
abclib.dsp
View File

@ -41,7 +41,7 @@ RSC=rc.exe
# PROP Intermediate_Dir "ReleaseLib" # PROP Intermediate_Dir "ReleaseLib"
# PROP Target_Dir "" # PROP Target_Dir ""
# ADD BASE CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_MBCS" /D "_LIB" /YX /FD /c # ADD BASE CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_MBCS" /D "_LIB" /YX /FD /c
# ADD CPP /nologo /W3 /GX /O2 /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /I "src/aig/bbl" /I "src/aig/sky" /I "src/aig/nal2" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /c # ADD CPP /nologo /MD /W3 /GX /O2 /I "src/ext/ext" /I "src/misc/ext" /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/cov" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /I "src/aig/bbl" /I "src/aig/llb" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /c
# ADD BASE RSC /l 0x409 /d "NDEBUG" # ADD BASE RSC /l 0x409 /d "NDEBUG"
# ADD RSC /l 0x409 /d "NDEBUG" # ADD RSC /l 0x409 /d "NDEBUG"
BSC32=bscmake.exe BSC32=bscmake.exe
@ -64,7 +64,7 @@ LIB32=link.exe -lib
# PROP Intermediate_Dir "DebugLib" # PROP Intermediate_Dir "DebugLib"
# PROP Target_Dir "" # PROP Target_Dir ""
# ADD BASE CPP /nologo /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_MBCS" /D "_LIB" /YX /FD /GZ /c # ADD BASE CPP /nologo /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_MBCS" /D "_LIB" /YX /FD /GZ /c
# ADD CPP /nologo /W3 /Gm /GX /ZI /Od /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /I "src/aig/bbl" /I "src/aig/sky" /I "src/aig/nal2" /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /GZ /c # ADD CPP /nologo /MDd /W3 /Gm /GX /ZI /Od /I "src/ext/ext" /I "src/misc/ext" /I "src/base/abc" /I "src/base/abci" /I "src/base/cmd" /I "src/base/io" /I "src/base/main" /I "src/base/ver" /I "src/bdd/cudd" /I "src/bdd/dsd" /I "src/bdd/epd" /I "src/bdd/mtr" /I "src/bdd/parse" /I "src/bdd/reo" /I "src/bdd/cas" /I "src/map/cov" /I "src/map/fpga" /I "src/map/mapper" /I "src/map/mio" /I "src/map/super" /I "src/map/if" /I "src/map/pcm" /I "src/map/ply" /I "src/misc/extra" /I "src/misc/mvc" /I "src/misc/st" /I "src/misc/util" /I "src/misc/espresso" /I "src/misc/nm" /I "src/misc/vec" /I "src/misc/hash" /I "src/misc/bzlib" /I "src/misc/zlib" /I "src/opt/cut" /I "src/opt/dec" /I "src/opt/fxu" /I "src/opt/rwr" /I "src/opt/sim" /I "src/opt/ret" /I "src/opt/res" /I "src/opt/lpk" /I "src/sat/bsat" /I "src/sat/csat" /I "src/sat/msat" /I "src/sat/fraig" /I "src/sat/nsat" /I "src/sat/psat" /I "src/aig/ivy" /I "src/aig/hop" /I "src/aig/rwt" /I "src/aig/deco" /I "src/aig/mem" /I "src/aig/dar" /I "src/aig/fra" /I "src/aig/cnf" /I "src/aig/csw" /I "src/aig/ioa" /I "src/aig/aig" /I "src/aig/kit" /I "src/aig/bdc" /I "src/aig/bar" /I "src/aig/ntl" /I "src/aig/nwk" /I "src/aig/tim" /I "src/opt/mfs" /I "src/aig/mfx" /I "src/aig/saig" /I "src/aig/bbr" /I "src/aig/int" /I "src/aig/dch" /I "src/aig/ssw" /I "src/sat/lsat" /I "src/aig/cec" /I "src/aig/cgt" /I "src/aig/sec" /I "src/map/amap" /I "src/aig/fsim" /I "src/aig/gia" /I "src/aig/bbl" /I "src/aig/llb" /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /D ABC_DLL=ABC_DLLEXPORT /D "_CRT_SECURE_NO_DEPRECATE" /FR /YX /FD /GZ /c
# ADD BASE RSC /l 0x409 /d "_DEBUG" # ADD BASE RSC /l 0x409 /d "_DEBUG"
# ADD RSC /l 0x409 /d "_DEBUG" # ADD RSC /l 0x409 /d "_DEBUG"
BSC32=bscmake.exe BSC32=bscmake.exe
@ -199,6 +199,10 @@ SOURCE=.\src\base\abci\abcBidec.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\base\abci\abcBm.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcBmc.c SOURCE=.\src\base\abci\abcBmc.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -207,11 +211,11 @@ SOURCE=.\src\base\abci\abcCas.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\base\abci\abcClpBdd.c SOURCE=.\src\base\abci\abcCascade.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\base\abci\abcClpSop.c SOURCE=.\src\base\abci\abcCollapse.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -227,18 +231,14 @@ SOURCE=.\src\base\abci\abcDebug.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\base\abci\abcDelay.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcDprove2.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcDress.c SOURCE=.\src\base\abci\abcDress.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\base\abci\abcDress2.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcDsd.c SOURCE=.\src\base\abci\abcDsd.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -275,10 +275,18 @@ SOURCE=.\src\base\abci\abcIf.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\base\abci\abcIfMux.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcIvy.c SOURCE=.\src\base\abci\abcIvy.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\base\abci\abcLog.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcLut.c SOURCE=.\src\base\abci\abcLut.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -387,10 +395,18 @@ SOURCE=.\src\base\abci\abcSat.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\base\abci\abcScorr.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcSense.c SOURCE=.\src\base\abci\abcSense.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\base\abci\abcSpeedup.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcStrash.c SOURCE=.\src\base\abci\abcStrash.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -455,6 +471,14 @@ SOURCE=.\src\base\cmd\cmdInt.h
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\base\cmd\cmdLoad.c
# End Source File
# Begin Source File
SOURCE=.\src\base\cmd\cmdPlugin.c
# End Source File
# Begin Source File
SOURCE=.\src\base\cmd\cmdUtils.c SOURCE=.\src\base\cmd\cmdUtils.c
# End Source File # End Source File
# End Group # End Group
@ -579,6 +603,10 @@ SOURCE=.\src\base\io\ioWritePla.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\base\io\ioWriteSmv.c
# End Source File
# Begin Source File
SOURCE=.\src\base\io\ioWriteVerilog.c SOURCE=.\src\base\io\ioWriteVerilog.c
# End Source File # End Source File
# End Group # End Group
@ -607,6 +635,10 @@ SOURCE=.\src\base\main\mainInt.h
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\base\main\mainLib.c
# End Source File
# Begin Source File
SOURCE=.\src\base\main\mainUtils.c SOURCE=.\src\base\main\mainUtils.c
# End Source File # End Source File
# End Group # End Group
@ -2265,6 +2297,10 @@ SOURCE=.\src\misc\vec\vecStr.h
SOURCE=.\src\misc\vec\vecVec.h SOURCE=.\src\misc\vec\vecVec.h
# End Source File # End Source File
# Begin Source File
SOURCE=.\src\misc\vec\vecWrd.h
# End Source File
# End Group # End Group
# Begin Group "util" # Begin Group "util"
@ -2279,6 +2315,10 @@ SOURCE=.\src\misc\util\util_hack.h
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\misc\util\utilFile.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\util\utilMem.c SOURCE=.\src\misc\util\utilMem.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -2395,7 +2435,23 @@ SOURCE=.\src\misc\zlib\deflate.h
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\misc\zlib\gzio.c SOURCE=.\src\misc\zlib\gzclose.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\zlib\gzguts.h
# End Source File
# Begin Source File
SOURCE=.\src\misc\zlib\gzlib.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\zlib\gzread.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\zlib\gzwrite.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -3047,6 +3103,10 @@ SOURCE=.\src\aig\aig\aigShow.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\aig\aigSplit.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\aig\aigTable.c SOURCE=.\src\aig\aig\aigTable.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -3127,6 +3187,10 @@ SOURCE=.\src\aig\ntl\ntlNames.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\ntl\ntlnwk.h
# End Source File
# Begin Source File
SOURCE=.\src\aig\ntl\ntlObj.c SOURCE=.\src\aig\ntl\ntlObj.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -3315,6 +3379,10 @@ SOURCE=.\src\aig\saig\saigAbs.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\saig\saigAbs2.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\saig\saigBmc.c SOURCE=.\src\aig\saig\saigBmc.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -3323,10 +3391,22 @@ SOURCE=.\src\aig\saig\saigBmc2.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\saig\saigBmc3.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\saig\saigCone.c SOURCE=.\src\aig\saig\saigCone.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\saig\saigConstr.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\saig\saigConstr2.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\saig\saigDup.c SOURCE=.\src\aig\saig\saigDup.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -3347,6 +3427,10 @@ SOURCE=.\src\aig\saig\saigMiter.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\saig\saigPba.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\saig\saigPhase.c SOURCE=.\src\aig\saig\saigPhase.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -3531,6 +3615,10 @@ SOURCE=.\src\aig\ssw\sswCnf.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\ssw\sswConstr.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ssw\sswCore.c SOURCE=.\src\aig\ssw\sswCore.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -3539,6 +3627,10 @@ SOURCE=.\src\aig\ssw\sswDyn.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\ssw\sswFilter.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ssw\sswInt.h SOURCE=.\src\aig\ssw\sswInt.h
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -3649,6 +3741,10 @@ SOURCE=.\src\aig\cec\cecSolve.c
SOURCE=.\src\aig\cec\cecSweep.c SOURCE=.\src\aig\cec\cecSweep.c
# End Source File # End Source File
# Begin Source File
SOURCE=.\src\aig\cec\cecSynth.c
# End Source File
# End Group # End Group
# Begin Group "cgt" # Begin Group "cgt"
@ -3682,14 +3778,6 @@ SOURCE=.\src\aig\cgt\cgtMan.c
SOURCE=.\src\aig\cgt\cgtSat.c SOURCE=.\src\aig\cgt\cgtSat.c
# End Source File # End Source File
# End Group # End Group
# Begin Group "sec"
# PROP Default_Filter ""
# End Group
# Begin Group "nal"
# PROP Default_Filter ""
# End Group
# Begin Group "gia" # Begin Group "gia"
# PROP Default_Filter "" # PROP Default_Filter ""
@ -3719,6 +3807,10 @@ SOURCE=.\src\aig\gia\giaAiger.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\gia\giaBidec.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaCof.c SOURCE=.\src\aig\gia\giaCof.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -3795,11 +3887,15 @@ SOURCE=.\src\aig\gia\giaHcd.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\gia\giaIf.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaMan.c SOURCE=.\src\aig\gia\giaMan.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\gia\giaMap.c SOURCE=.\src\aig\gia\giaMem.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -3807,6 +3903,10 @@ SOURCE=.\src\aig\gia\giaPat.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\gia\giaReparam.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaRetime.c SOURCE=.\src\aig\gia\giaRetime.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -3815,6 +3915,10 @@ SOURCE=.\src\aig\gia\giaScl.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\gia\giaShrink.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaSim.c SOURCE=.\src\aig\gia\giaSim.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -3823,6 +3927,14 @@ SOURCE=.\src\aig\gia\giaSort.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\gia\giaSpeedup.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaSupMin.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\gia\giaSwitch.c SOURCE=.\src\aig\gia\giaSwitch.c
# End Source File # End Source File
# Begin Source File # Begin Source File
@ -3857,42 +3969,74 @@ SOURCE=.\src\aig\live\liveness.c
SOURCE=.\src\aig\live\liveness_sim.c SOURCE=.\src\aig\live\liveness_sim.c
# End Source File # End Source File
# Begin Source File
SOURCE=.\src\aig\live\ltl_parser.c
# End Source File
# End Group # End Group
# Begin Group "sky" # Begin Group "llb"
# PROP Default_Filter "" # PROP Default_Filter ""
# Begin Source File # Begin Source File
SOURCE=.\src\aig\sky\sky.c SOURCE=.\src\aig\llb\llb.h
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\sky\sky.h SOURCE=.\src\aig\llb\llbCex.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\sky\skyCheck.c SOURCE=.\src\aig\llb\llbCluster.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\sky\skyMan.c SOURCE=.\src\aig\llb\llbConstr.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\sky\skyName.c SOURCE=.\src\aig\llb\llbCore.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\sky\skyObj.c SOURCE=.\src\aig\llb\llbFlow.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\sky\skyReadBlif.c SOURCE=.\src\aig\llb\llbHint.c
# End Source File # End Source File
# Begin Source File # Begin Source File
SOURCE=.\src\aig\sky\skyUtil.c SOURCE=.\src\aig\llb\llbInt.h
# End Source File # End Source File
# Begin Source File
SOURCE=.\src\aig\llb\llbMan.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\llb\llbMatrix.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\llb\llbPart.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\llb\llbPivot.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\llb\llbReach.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\llb\llbSched.c
# End Source File
# End Group
# Begin Group "sky"
# PROP Default_Filter ""
# End Group # End Group
# End Group # End Group
# End Group # End Group

8
bug_report_template.txt Normal file
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@ -0,0 +1,8 @@
When reporting a problem, please include the following:
1. ABC version
2. Linux distribution and version
3. 32-bit or 64-bit
4. The exact error message when trying to run the tool
5. The output of the 'ldd' command run on the exeutable (e.g. 'ldd abc').
6. Versions of relevant tools or packages used.

0
depends.sh Executable file → Normal file
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2
link_command_line.txt Normal file
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@ -0,0 +1,2 @@
link.exe @<<
kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib lib\abcd.lib /nologo /subsystem:console /incremental:yes /pdb:".\DebugExe\abc.pdb" /debug /machine:I386 /out:"_TEST/abc.exe" ".\DebugExe\main.obj" ".\lib\abcd.lib"

15
readme
View File

@ -40,3 +40,18 @@ in Makefile.
Finally, run regression test: Finally, run regression test:
abc>>> so regtest.script abc>>> so regtest.script
The following comment was added by Krish Sundaresan:
"I found that the code does compile correctly on Solaris
if gcc is used (instead of g++ that I was using for some reason).
Also readline which is not available by default on most
Sol10 systems, needs to be installed. I downloaded the
readline-5.2 package from sunfreeware.com and installed it
locally. Also modified CFLAGS to add the local include files
for readline and LIBS to add the local libreadline.a. Perhaps
you can add these steps in the readme to help folks compiling
this on Solaris."
Archiving the binary: tar czf archive.tar.gz directory

6
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To compile as C code: make sure CC=gcc, and, optionally, that ABC_NAMESPACE is not defined.
To compile as C++ code without namespaces: make sure CC=g++, and that ABC_NAMESPACE is not defined.
To compile as C++ code with namespaces: make sure CC=g++, and that ABC_NAMESPACE is defined to name of the requested namespace. For example, add to OPTFLAGS -DABC_NAMESPACE=xxx

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python new_abc_commands.py
python reachx_cmd.py
#python C:\Research\ABC\AIG\Python\reachx_cmd.py
# global parameters
set check # checks intermediate networks
#set checkfio # prints warnings when fanins/fanouts are duplicated
set checkread # checks new networks after reading from file
set backup # saves backup networks retrived by "undo" and "recall"
set savesteps 1 # sets the maximum number of backup networks to save
set progressbar # display the progress bar
# program names for internal calls
set dotwin dot.exe
set dotunix dot
set gsviewwin gsview32.exe
set gsviewunix gv
set siswin sis.exe
set sisunix sis
set mvsiswin mvsis.exe
set mvsisunix mvsis
set capowin MetaPl-Capo10.1-Win32.exe
set capounix MetaPl-Capo10.1
set gnuplotwin wgnuplot.exe
set gnuplotunix gnuplot
# standard aliases
alias b balance
alias cl cleanup
alias clp collapse
alias esd ext_seq_dcs
alias f fraig
alias fs fraig_sweep
alias fsto fraig_store
alias fres fraig_restore
alias ft fraig_trust
alias lp lutpack
alias pd print_dsd
alias pex print_exdc -d
alias pf print_factor
alias pfan print_fanio
alias pl print_level
alias pio print_io
alias pk print_kmap
alias ps print_stats
alias psu print_supp
alias psy print_symm
alias pun print_unate
alias q quit
alias r read
alias ra read_aiger
alias r3 retime -M 3
alias r1 dretime
alias r2 retime -M 2
alias r4 retime -M 4
alias r5 retime -M 5
alias r6 retime -M 6
alias ren renode
alias rh read_hie
alias rl read_blif
alias rb read_bench
alias ret retime
alias rp read_pla
alias rt read_truth
alias rv read_verilog
alias rvl read_verlib
alias rsup read_super mcnc5_old.super
alias rlib read_library
alias rlibc read_library cadence.genlib
alias rw rewrite
alias rwz rewrite -z
alias rf refactor
alias rfz refactor -z
alias re restructure
alias rez restructure -z
alias rs resub
alias rsz resub -z
alias sa set autoexec ps
alias ua set autoexec
alias scl scleanup
alias sif if -s
alias so source -x
alias st strash
alias sw sweep
alias ssw ssweep
alias tr0 trace_start
alias tr1 trace_check
alias trt "r c.blif; st; tr0; b; tr1"
alias u undo
alias w write
alias wa write_aiger
alias wb write_bench
alias wc write_cnf
alias wh write_hie
alias wl write_blif
alias wp write_pla
alias wv write_verilog
# standard scripts
alias share "b; multi; fx; b"
alias resyn "b; rw; rwz; b; rwz; b"
alias resyn2 "b; rw; rf; b; rw; rwz; b; rfz; rwz; b"
alias resyn2a "b; rw; b; rw; rwz; b; rwz; b"
alias resyn3 "b; rs; rs -K 6; b; rsz; rsz -K 6; b; rsz -K 5; b"
alias compress "b -l; rw -l; rwz -l; b -l; rwz -l; b -l"
alias compress2 "b -l; rw -l; rf -l; b -l; rw -l; rwz -l; b -l; rfz -l; rwz -l; b -l"
alias choice "fraig_store; resyn; fraig_store; resyn2; fraig_store; fraig_restore"
alias choice2 "fraig_store; balance; fraig_store; resyn; fraig_store; resyn2; fraig_store; resyn2; fraig_store; fraig_restore"
alias rwsat "st; rw -l; b -l; rw -l; rf -l"
alias rwsat2 "st; rw -l; b -l; rw -l; rf -l; fraig; rw -l; b -l; rw -l; rf -l"
alias shake "st; ps; sat -C 5000; rw -l; ps; sat -C 5000; b -l; rf -l; ps; sat -C 5000; rfz -l; ps; sat -C 5000; rwz -l; ps; sat -C 5000; rfz -l; ps; sat -C 5000"
alias snap fraig_store
alias unsnap fraig_restore
alias sv "wl temp"
alias usv "rl temp"
alias pli print_latch
alias cy "cycle -F 1"
alias im imfs
alias fx1 "fx -N 1"
alias el4 "eliminate -N 4"
alias if6 "if -K 6"
alias fr fretime -g
alias icb "ic -M 2 -B 10 -s"
alias cs "care_set "
# resubstitution scripts for the IWLS paper
alias src_rw "st; rw -l; rwz -l; rwz -l"
alias src_rs "st; rs -K 6 -N 2 -l; rs -K 9 -N 2 -l; rs -K 12 -N 2 -l"
alias src_rws "st; rw -l; rs -K 6 -N 2 -l; rwz -l; rs -K 9 -N 2 -l; rwz -l; rs -K 12 -N 2 -l"
alias resyn2rs "b; rs -K 6; rw; rs -K 6 -N 2; rf; rs -K 8; b; rs -K 8 -N 2; rw; rs -K 10; rwz; rs -K 10 -N 2; b; rs -K 12; rfz; rs -K 12 -N 2; rwz; b"
alias compress2rs "b -l; rs -K 6 -l; rw -l; rs -K 6 -N 2 -l; rf -l; rs -K 8 -l; b -l; rs -K 8 -N 2 -l; rw -l; rs -K 10 -l; rwz -l; rs -K 10 -N 2 -l; b -l; rs -K 12 -l; rfz -l; rs -K 12 -N 2 -l; rwz -l; b -l"
alias c2 "ua; compress2rs; sa"
alias ic "indcut -v"
alias lp "lutpack"
alias c "ua; compress; sa"
alias c1 "ua; compress;b -l; rs -K 6 -l; rw -l; rs -K 6 -N 2 -l; rf -l; rs -K 8 -l; b -l; sa"
alias dr dretime
alias ds dsec -v
alias dp dprove -v
# experimental implementation of don't-cares
alias resyn2rsdc "b; rs -K 6 -F 2; rw; rs -K 6 -N 2 -F 2; rf; rs -K 8 -F 2; b; rs -K 8 -N 2 -F 2; rw; rs -K 10 -F 2; rwz; rs -K 10 -N 2 -F 2; b; rs -K 12 -F 2; rfz; rs -K 12 -N 2 -F 2; rwz; b"
alias compress2rsdc "b -l; rs -K 6 -F 2 -l; rw -l; rs -K 6 -N 2 -F 2 -l; rf -l; rs -K 8 -F 2 -l; b -l; rs -K 8 -N 2 -F 2 -l; rw -l; rs -K 10 -F 2 -l; rwz -l; rs -K 10 -N 2 -F 2 -l; b -l; rs -K 12 -F 2 -l; rfz -l; rs -K 12 -N 2 -F 2 -l; rwz -l; b -l"
# minimizing for FF literals
alias fflitmin "compress2rs; ren; sop; ps -f"
# temporaries
#alias t "rvl th/lib.v; rvv th/t2.v"
#alias t "so c/pure_sat/test.c"
#alias t "r c/14/csat_998.bench; st; ps"
#alias t0 "r res.blif; aig; mfs"
#alias t "r res2.blif; aig; mfs"
#alias tt "r a/quip_opt/nut_001_opt.blif"
#alias ttb "wh a/quip_opt/nut_001_opt.blif 1.blif"
#alias ttv "wh a/quip_opt/nut_001_opt.blif 1.v"
#alias reach "st; ps; compress2; ps; qrel; ps; compress2; ps; qreach -v; ps"
alias qs1 "qvar -I 96 -u; ps; qbf -P 96"
alias qs2 "qvar -I 96 -u; qvar -I 97 -u; ps; qbf -P 96"
alias qs3 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; ps; qbf -P 96"
alias qs4 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; ps; qbf -P 96"
alias qs5 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; ps; qbf -P 96"
alias qs6 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; ps; qbf -P 96"
alias qs7 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; ps; qbf -P 96"
alias qs8 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; ps; qbf -P 96"
alias qs9 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; qvar -I 104 -u; ps; qbf -P 96"
alias qsA "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; qvar -I 104 -u; qvar -I 105 -u; ps; qbf -P 96"
alias chnew "st; haig_start; resyn2; haig_use"
alias chnewrs "st; haig_start; resyn2rs; haig_use"
alias stdsd "r test/6in.blif; st; ps; u; bdd; dsd -g; st; ps"
alias trec "rec_start; r c.blif; st; rec_add; rec_use"
alias trec4 "rec_start -K 4; r i10.blif; st; rec_add; rec_use"
alias trec5 "rec_start -K 5; r i10.blif; st; rec_add; rec_use"
alias trec6 "rec_start -K 6; r i10.blif; st; rec_add; rec_use"
alias trec7 "rec_start -K 7; r i10.blif; st; rec_add; rec_use"
alias trec8 "rec_start -K 8; r i10.blif; st; rec_add; rec_use"
alias trec10 "rec_start -K 10; r i10.blif; st; rec_add; rec_use"
alias trec12 "rec_start -K 12; r i10.blif; st; rec_add; rec_use"
#alias tsh "r i10_if.blif; st; ps; u; sw; st; ps; cec"
alias tst4 "r i10_if4.blif; st; ps; r x/rec4_.blif; st; rec_start; r i10_if4.blif; st -r; ps; cec"
alias tst4n "r i10_if4.blif; st; ps; r 5npn/all_functions.aig; st; rec_start; r i10_if4.blif; st -r; ps; cec"
alias tst6 "r i10_if6.blif; st; ps; r x/rec6_16_.blif; st; rec_start; r i10_if6.blif; st -r; ps; cec"
alias sn short_names
alias inth "int -rv -C 25000 -N 10000"
alias inthh "int -rv -C 75000 -N 100"
alias a "alias "
alias indh "ind -v -F 50 -C 10000"
alias indhu "ind -vu -F 25 -C 10000"
#alias reachx "reach -v -B 2000000 -F 20000"
alias dc2rs "ua; compress2rs; ps"
alias ffx "ps;orpos;qua_ffix"
alias bfx "ps;orpos;qua_bfix"
alias era "&get;&era -mv;&put"
#simulations
alias simh "sim -m -F 500 -W 15"
alias simhh "sim -m -F 2500 -W 3"
alias simdeep "sim -m -F 50000 -W 1"
alias simwide "sim -m -F 500 -W 255"
#BMC's:
alias bmc2h "bmc2 -v -C 25000 -G 250000 -F 100"
alias bmc2hh "bmc2 -v -C 75000 -G 750000 -F 100"
#SIMPLIFICATIONS
alias scr "&get; &scorr; &put"
alias lcr "&get; &lcorr; &put"
alias trm "logic;trim;st;ps"
alias smp "ua;ps;scl;ps;rw;dr;lcorr;rw;dr;ps;scorr;ps;fraig;ps;dc2;dr;scorr -F 2;ps;dc2rs;w temp.aig"
alias smp1 "ua;ps;scl;ps;rw;dr;lcorr;rw;dr;ps;scorr;ps;fraig;ps;dc2;dr;ps;dc2rs;w temp.aig"
alias smpf "ua;ps;scl;lcr;ps;rw;dr;ps;scr;ps;dc2;&get;&scorr -F 2;&put;dr;ps;dc2;ps;w temp.aig"
alias &smp "ua;&get;&ps;&scl;&ps;&dc2;&put;dr;&get;&lcorr;&dc2;&put;dr;&get;&ps;&scorr;&ps;&fraig;&ps;&dc2;&put;dr;&get;&scorr -F 2;&ps;&dc2;&put;w temp.aig"
alias smplite '&get;&scl;&dc2;&put;dr;&get;&lcorr;&dc2;&put;dr;&get;&scorr;&dc2;&put;dr;&get;&dc2;&put;ps;w temp.aig'
alias &smp1 "ua;&get;&ps;&scl;&ps;&dc2;&put;dr;&get;&lcorr;&dc2;&put;dr;&get;&ps;&scorr;&ps;&fraig;&ps;&dc2;&put;dr;&get;&ps;&dc2;&put;w temp.aig"
alias &smpf "ua;ps;rw;&get;&ps;&scl;&ps;&put;dr;&get;&ps;&lcorr;&ps;&dc2;&ps;&scorr;&ps;&put;rw;ps;w temp.aig"
#for each output separately
alias simpk "dprove -vrcbkmiu -B 10 -D 1000"
alias simpkh "simpk -D 5000"
alias simpkf "simpk -D 10"
#ABSTRACTIONS
#reparameterization
alias rpm "ps;&get;&reparam;&put;ps"
#register abstraction
alias absh "abs -se -D 200000 -R 2; short_names"
alias abshx "abs -se -D 1000000; short_names"
alias absr "abs -ser -G 2000; short_names"
alias absp "abs -sep -G 2000; short_names"
alias absh1 "abs -se -D 200000 -R 1; short_names"
#ABSTRACTION allowing continuation of register abstraction
alias absgo "&get; &abs_start -C 10000 -R 2; &ps; &w 1.aig; &abs_derive;&put; w gabs.aig"
alias absgof "&get; &abs_start -C 1000 -R 2; &ps; &w 1.aig; &abs_derive;&put; w gabs.aig"
alias absgoh "&get; &abs_start -C 200000 -R 2; &ps; &w 1.aig; &abs_derive;&put;w gabs.aig"
#continuation after a cex is found
alias absc "&r 1.aig; &ps; &abs_refine; &w 1.aig; &ps; &abs_derive; &ps;&put; w gabs.aig"
#PBA - proof based abstraction. continuation with cex is done with absc.
alias pbago "&get; &pba_start -vd -C 25000 -F 10; &ps; &w 1.aig; &abs_derive; &put; w gabs.aig"
#SPECULATION
#initial speculation where equivalences are gathered.
alias spechisysf "ua; &get; &equiv -s -W 512 -F 2000; &semi -v -F 50; &ps; &speci -F 1000 -C 25000; &srm -s; r gsrm.aig; &ps; &w gore.aig"
alias spechisysfx "ua; &get; &equiv -s -W 512 -F 2000; &semi -v -F 50; &ps; &speci -F 10000 -C 200000; &srm -s; r gsrm.aig; &ps; &w gore.aig"
alias spechisysff "ua; &get; &equiv -s -W 512 -F 2000; &semi -v -F 50; &ps; &speci -F 10000 -C 5000; &srm -s; r gsrm.aig; &ps; &w gore.aig"
alias spechisysfq "ua; &get; &equiv -s -W 512 -F 2000; &semi -v -F 50; &ps; &speci -F 10000 -C 10; &srm -s; r gsrm.aig; &ps; &w gore.aig"
# CONTINUATION OF SPECULATION
#BMC based:
alias spec "&r gore.aig;&srm -s;r gsrm.aig; bmc2 -v -F 100 -C 10000 -G 100000; &resim -m; &w gore.aig; &ps "
alias spech "&r gore.aig;&srm -s;r gsrm.aig;smp;ps; bmc2 -v -F 100 -C 25000 -G 250000; &resim -m; &w gore.aig; &ps "
alias spechh "&r gore.aig;&srm ;r gsrm.aig;smp;simpkf;smp;bmc2 -v -F 100 -C 200000; &resim -m; &w gore.aig; &ps "
alias specheavy "&r gore.aig;&srm -s;r gsrm.aig; smp;simpk;smp;bmc2 -v -F 5000 -C 200000 -F 100; &resim -m; &w gore.aig; &ps"
#BDD based:
alias specb "&r gore.aig;&srm ;r gsrm.aig;smp;ps; reach -ov -B 1000000 -F 200000; &resim -m; &w gore.aig; &ps "
alias specbb "&r gore.aig;&srm ;r gsrm.aig;smp;simpk -D 100;smp;ps; reach -ov -B 1000000 -F 200000; &resim -m; &w gore.aig; &ps "
#Interpolation based:
alias specint "&r gore.aig;&srm ;r gsrm.aig;inth;&resim -m; &w gore.aig; &ps"
alias speck "&r gore.aig;&srm ;r gsrm.aig;simpk;&resim -m; &w gore.aig; &ps "
alias speckf "&r gore.aig;&srm ;r gsrm.aig;simpk -D 100;&resim -m; &w gore.aig; &ps "
alias specpk "&r gore.aig;&srm ;r gsrm.aig;simpkf;smp;ps; simpk ; &resim -m; &w gore.aig; &ps "
alias specpkh "&r gore.aig;&srm ;r gsrm.aig;simpkf;smp;ps; simpkh ; &resim -m; &w gore.aig; &ps "
alias specp "&r gore.aig;&srm ;r gsrm.aig;ps; dprove -rmficbu -B 10 -D 10; &resim -m; &w gore.aig; &ps "
alias spece "&r gore.aig; &srm ;r gsrm.aig; smp; ps; &w gore.aig; &get; &era -m; &r gore.aig; &resim -m; &w gore.aig; &ps"
#simulation based:
alias specs "&r gore.aig; &srm ; r gsrm.aig; sim -m -F 500 -W 15; &resim -m; &w gore.aig; &ps "
alias specsh "&r gore.aig; &srm ; r gsrm.aig; sim -m -F 3500 -W 3; &resim -m; &w gore.aig;&ps "
alias speci "&r gore.aig;&srm ;r gsrm.aig;int -tk -C 2000;&resim -m; &w gore.aig; &ps"
alias %sa "set autoexec %ps"
alias %scr "%get;%st;%scorr;%put;st"
alias sc "fold;w tempc.aig;unfold -s"
alias uc "r tempc.aig;unfold -s"
alias smpc "scl;rw;ps;scorr -c;ps;fraig;ps;compress2rs;ps"

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#!/bin/sh
abc_root()
{
cwd="$(pwd)"
cd $(dirname "$1")
echo $(dirname "$(pwd)")
cd "${cwd}"
}
abc_dir=$(abc_root "$0")
bin_dir="${abc_dir}"/bin
aig_file="$1"
exec ${bin_dir}/abc -c "/rf ${aig_file} ; /pushredirect ; /pushdtemp ; bmc2 ; /popdtemp ; /popredirect ; /print_aiger_result"

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#!/bin/sh
abc_root()
{
cwd="$(pwd)"
cd $(dirname "$1")
echo $(dirname "$(pwd)")
cd "${cwd}"
}
abc_dir=$(abc_root "$0")
bin_dir="${abc_dir}"/bin
aig_file="$1"
exec "${bin_dir}"/abc -c "/rf ${aig_file} ; /pushredirect ; /pushdtemp ; bmc3 ; /popdtemp ; /popredirect ; /print_aiger_result"

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#!/bin/sh
abc_root()
{
cwd="$(pwd)"
cd $(dirname "$1")
echo $(dirname "$(pwd)")
cd "${cwd}"
}
abc_dir=$(abc_root "$0")
bin_dir="${abc_dir}"/bin
aig_file="$1"
exec ${bin_dir}/abc -c "/rf ${aig_file} ; /pushredirect ; /pushdtemp ; dprove ; /popdtemp ; /popredirect ; /print_aiger_result"

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class _Getch:
"""Gets a single character from standard input. Does not echo to the screen."""
def __init__(self):
try:
self.impl = _GetchWindows()
except ImportError:
self.impl = _GetchUnix()
def __call__(self): return self.impl()
class _GetchUnix:
def __init__(self):
import tty, sys
def __call__(self):
import sys, tty, termios
fd = sys.stdin.fileno()
old_settings = termios.tcgetattr(fd)
try:
tty.setraw(sys.stdin.fileno())
ch = sys.stdin.read(1)
finally:
termios.tcsetattr(fd, termios.TCSADRAIN, old_settings)
return ch
class _GetchWindows:
def __init__(self):
import msvcrt
def __call__(self):
import msvcrt
return msvcrt.getch()
getch = _Getch()

183
scripts/new_abc_commands.py Normal file
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@ -0,0 +1,183 @@
# You can use 'from pyabc import *' and then not need the pyabc. prefix everywhere
import os
import pyabc
import abc_common
import tempfile
import shutil
import redirect
# A new command is just a function that accepts a list of string arguments
# The first argument is always the name of the command
# It MUST return an integer. -1: user quits, -2: error. Return 0 for success.
# a command that calls prove(1) and returns success
def prove_cmd(args):
result = abc_common.prove(1)
print result
return 0
# registers the command:
# The first argument is the function
# The second argument is the category (mainly for the ABC help command)
# The third argument is the new command name
# Keep the fourth argument 0, or consult with Alan
pyabc.add_abc_command(prove_cmd, "ZPython", "/prove", 0)
def read_cmd(args):
if len(args)==2:
abc_common.read_file_quiet(args[1])
else:
abc_common.read_file()
return 0
pyabc.add_abc_command(read_cmd, "ZPython", "/rf", 0)
def chdir_cmd(args):
os.chdir( args[1] )
return 0
pyabc.add_abc_command(chdir_cmd, "ZPython", "/cd", 0)
def pwd_cmd(args):
print os.getcwd()
return 0
pyabc.add_abc_command(pwd_cmd, "ZPython", "/pwd", 0)
def ls_cmd(args):
os.system("ls " + " ".join(args[1:]))
return 0
pyabc.add_abc_command(ls_cmd, "ZPython", "/ls", 0)
pushd_temp_stack = []
def pushdtemp_cmd(args):
tmpdir = tempfile.mkdtemp()
pushd_temp_stack.append( (os.getcwd(), tmpdir) )
os.chdir(tmpdir)
return 0
pyabc.add_abc_command(pushdtemp_cmd, "ZPython", "/pushdtemp", 0)
def popdtemp_cmd(args):
prev, temp = pushd_temp_stack.pop()
os.chdir(prev)
shutil.rmtree(temp, ignore_errors=True)
return 0
pyabc.add_abc_command(popdtemp_cmd, "ZPython", "/popdtemp", 0)
pushredirect_stack = []
def push_redirect_cmd(args):
fdout = redirect.start_redirect( redirect.null_file, sys.stdout)
pushredirect_stack.append( (sys.stdout, fdout) )
fderr = redirect.start_redirect( redirect.null_file, sys.stderr)
pushredirect_stack.append( (sys.stderr, fderr) )
return 0
pyabc.add_abc_command(push_redirect_cmd, "ZPython", "/pushredirect", 0)
def pop_redirect_cmd(args):
err, fderr = pushredirect_stack.pop()
redirect.end_redirect(err, fderr)
out, fdout = pushredirect_stack.pop()
redirect.end_redirect(out, fdout)
return 0
pyabc.add_abc_command(pop_redirect_cmd, "ZPython", "/popredirect", 0)
def print_aiger_result(args):
status = pyabc.prob_status()
if status==1:
print 0
elif status==0:
print 1
else:
print 2
return 0
pyabc.add_abc_command(print_aiger_result, "ZPython", "/print_aiger_result", 0)
def super_prove_aiger_cmd(args):
noisy = len(args)==2 and args[1]=='-n'
if not noisy:
pyabc.run_command('/pushredirect')
pyabc.run_command('/pushdtemp')
try:
result = abc_common.super_prove()
except:
result = None
if not noisy:
pyabc.run_command('/popdtemp')
pyabc.run_command('/popredirect')
if result=="SAT":
print 1
elif result=="UNSAT":
print 0
else:
print 2
return 0
pyabc.add_abc_command(super_prove_aiger_cmd, "ZPython", "/super_prove_aiger", 0)
def prove_one_by_one_cmd(args):
noisy = len(args)==2 and args[1]=='-n'
# switch to a temporary directory
pyabc.run_command('/pushdtemp')
# write a copy of the original file in the temporary directory
pyabc.run_command('w original_aig_file.aig')
# iterate through the ouptus
for po in range(0, pyabc.n_pos()):
if not noisy:
pyabc.run_command('/pushredirect')
# replace the nework with the cone of the current PO
pyabc.run_command( 'cone -O %d -s'%po )
# run super_prove
try:
result = abc_common.super_prove()
except:
result = 'UNKNOWN'
if not noisy:
pyabc.run_command('/popredirect')
print 'PO %d is %s'%(po, result)
# stop if the result is not UNSAT
if result != "UNSAT":
break
# read the original file for the next iteration
pyabc.run_command('r original_aig_file.aig')
# go back to the original directory
pyabc.run_command('/popdtemp')
return 0
pyabc.add_abc_command(prove_one_by_one_cmd, "ZPython", "/prove_one_by_one", 0)

111
scripts/reachx_cmd.py Normal file
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@ -0,0 +1,111 @@
# You can use 'from pyabc import *' and then not need the pyabc. prefix everywhere
import sys
import optparse
import subprocess
import tempfile
import threading
import os
import os.path
from contextlib import contextmanager, nested
import pyabc
def wait_with_timeout(p, timeout):
""" Wait for a subprocess.Popen object to terminate, or until timeout (in seconds) expires. """
if timeout <= 0:
timeout = None
t = threading.Thread(target=lambda: p.wait())
t.start()
t.join(timeout)
if t.is_alive():
p.kill()
t.join()
return p.returncode
@contextmanager
def replace_sys_argv(argv):
if 'argv' in sys.__dict__:
old_argv = sys.argv
sys.argv = argv
yield
sys.argv = old_argv
else:
sys.argv = argv
yield
del sys.argv
@contextmanager
def temp_file_name(suffix=""):
file = tempfile.NamedTemporaryFile(delete=False, suffix=suffix)
name = file.name
file.close()
try:
yield name
finally:
os.unlink(name)
def cygpath(path):
if sys.platform == "win32":
if os.path.isabs(path):
drive, tail = os.path.splitdrive(path)
drive = drive.lower()
tail = tail.split(os.path.sep)
return '/cygdrive/%s'%drive[0] + '/'.join(tail)
else:
path = path.split(os.path.sep)
return "/".join(path)
return path
def run_reachx_cmd(effort, timeout):
with nested(temp_file_name(suffix=".aig"), temp_file_name()) as (tmpaig_name, tmplog_name):
pyabc.run_command("write %s"%tmpaig_name)
cmdline = [
'read %s'%cygpath(tmpaig_name),
'qua_ffix -effort %d -L %s'%(effort, cygpath(tmplog_name)),
'quit'
]
cmd = ["jabc", "-c", " ; ".join(cmdline)]
p = subprocess.Popen(cmd, shell=False, stdout=sys.stdout, stderr=sys.stderr)
rc = wait_with_timeout(p,timeout)
if rc != 0:
# jabc failed or stopped. Write a status file to update the status to unknown
with open(tmplog_name, "w") as f:
f.write('snl_UNK -1 unknown\n')
f.write('NULL\n')
f.write('NULL\n')
pyabc.run_command("read_status %s"%tmplog_name)
return rc
def reachx_cmd(argv):
usage = "usage: %prog [options]"
parser = optparse.OptionParser(usage)
parser.add_option("-e", "--effort", dest="effort", type=int, default=0, help="effort level. [default=0, means unlimited]")
parser.add_option("-t", "--timeout", dest="timeout", type=int, default=0, help="timeout in seconds [default=0, unlimited]")
with replace_sys_argv(argv):
options, args = parser.parse_args()
rc = run_reachx_cmd(options.effort, options.timeout)
print "%s command: jabc returned: %d"%(argv[0], rc)
return 0
pyabc.add_abc_command(reachx_cmd, "Verification", "reachx", 0)

94
scripts/redirect.py Normal file
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@ -0,0 +1,94 @@
"""
A simple context manager for redirecting streams in Python.
The streams are redirected at the the C runtime level so that the output of C extensions
that use stdio will also be redirected.
null_file : a stream representing the null device (e.g. /dev/null on Unix)
redirect: a context manager for redirecting streams
Author: Baruch Sterin (sterin@berkeley.edu)
"""
import os
import sys
from contextlib import contextmanager
null_file = open( os.devnull, "w" )
@contextmanager
def _dup( f ):
fd = os.dup( f.fileno() )
yield fd
os.close(fd)
@contextmanager
def redirect(dst = null_file, src = sys.stdout):
"""
Redirect the src stream into dst.
Example:
with redirect( open("somefile.txt", sys.stdout ) ):
do some stuff ...
"""
if src.fileno() == dst.fileno():
yield
return
with _dup( src ) as fd_dup_src:
dst.flush()
src.flush()
os.close( src.fileno() )
os.dup2( dst.fileno(), src.fileno() )
yield
src.flush()
os.close( src.fileno() )
os.dup2( fd_dup_src, src.fileno() )
def start_redirect(dst = null_file, src = sys.stdout):
"""
Start redirection of src stream into dst. Return the duplicated file handle of the source.
Example:
fd = start_redirect( open("somefile.txt"), sys.stdout )
... do some stuff ...
end_redirect(sys.stdout, fd)
"""
if src.fileno() == dst.fileno():
return None
fd_dup_src = os.dup( src.fileno() )
dst.flush()
src.flush()
os.close( src.fileno() )
os.dup2( dst.fileno(), src.fileno() )
return fd_dup_src
def end_redirect(src, fd_dup_src):
"""
End redirection of stream src.Redirect the src stream into dst. src is the source stream and fd_dup_src is the value returned by
start_redirect()
"""
if fd_dup_src is None:
return
src.flush()
os.close( src.fileno() )
os.dup2( fd_dup_src, src.fileno() )
os.close(fd_dup_src)

15
scripts/super_prove.sh Normal file
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@ -0,0 +1,15 @@
#!/bin/sh
abc_root()
{
cwd="$(pwd)"
cd $(dirname "$1")
echo $(dirname "$(pwd)")
cd "${cwd}"
}
abc_dir=$(abc_root "$0")
bin_dir="${abc_dir}"/bin
aig_file="$1"
exec ${bin_dir}/abc -c "/rf ${aig_file} ; /super_prove_aiger"

67
src/aig/aig/aig.h
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@ -21,6 +21,7 @@
#ifndef __AIG_H__ #ifndef __AIG_H__
#define __AIG_H__ #define __AIG_H__
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// INCLUDES /// /// INCLUDES ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -37,9 +38,10 @@
/// PARAMETERS /// /// PARAMETERS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
extern "C" {
#endif ABC_NAMESPACE_HEADER_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// BASIC TYPES /// /// BASIC TYPES ///
@ -105,6 +107,7 @@ struct Aig_Man_t_
int nTruePis; // the number of true primary inputs int nTruePis; // the number of true primary inputs
int nTruePos; // the number of true primary outputs int nTruePos; // the number of true primary outputs
int nAsserts; // the number of asserts among POs (asserts are first POs) int nAsserts; // the number of asserts among POs (asserts are first POs)
int nConstrs; // the number of constraints (model checking only)
// AIG node counters // AIG node counters
int nObjs[AIG_OBJ_VOID];// the number of objects by type int nObjs[AIG_OBJ_VOID];// the number of objects by type
int nCreated; // the number of created objects int nCreated; // the number of created objects
@ -148,7 +151,8 @@ struct Aig_Man_t_
Vec_Ptr_t * vMapped; Vec_Ptr_t * vMapped;
Vec_Int_t * vFlopNums; Vec_Int_t * vFlopNums;
Vec_Int_t * vFlopReprs; Vec_Int_t * vFlopReprs;
void * pSeqModel; Abc_Cex_t * pSeqModel;
Vec_Ptr_t * pSeqModelVec; // vector of counter-examples (for sequential miters)
Aig_Man_t * pManExdc; Aig_Man_t * pManExdc;
Vec_Ptr_t * vOnehots; Vec_Ptr_t * vOnehots;
Aig_Man_t * pManHaig; Aig_Man_t * pManHaig;
@ -217,10 +221,12 @@ static inline Aig_Cut_t * Aig_CutNext( Aig_Cut_t * pCut ) { return
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
static inline int Aig_IntAbs( int n ) { return (n < 0)? -n : n; } static inline int Aig_IntAbs( int n ) { return (n < 0)? -n : n; }
static inline int Aig_Float2Int( float Val ) { return *((int *)&Val); } //static inline int Aig_Float2Int( float Val ) { return *((int *)&Val); }
static inline float Aig_Int2Float( int Num ) { return *((float *)&Num); } //static inline float Aig_Int2Float( int Num ) { return *((float *)&Num); }
static inline int Aig_Base2Log( unsigned n ) { int r; assert( n >= 0 ); if ( n < 2 ) return n; for ( r = 0, n--; n; n >>= 1, r++ ); return r; } static inline int Aig_Float2Int( float Val ) { union { int x; float y; } v; v.y = Val; return v.x; }
static inline int Aig_Base10Log( unsigned n ) { int r; assert( n >= 0 ); if ( n < 2 ) return n; for ( r = 0, n--; n; n /= 10, r++ ); return r; } static inline float Aig_Int2Float( int Num ) { union { int x; float y; } v; v.x = Num; return v.y; }
static inline int Aig_Base2Log( unsigned n ) { int r; if ( n < 2 ) return n; for ( r = 0, n--; n; n >>= 1, r++ ); return r; }
static inline int Aig_Base10Log( unsigned n ) { int r; if ( n < 2 ) return n; for ( r = 0, n--; n; n /= 10, r++ ); return r; }
static inline char * Aig_UtilStrsav( char * s ) { return s ? strcpy(ABC_ALLOC(char, strlen(s)+1), s) : NULL; } static inline char * Aig_UtilStrsav( char * s ) { return s ? strcpy(ABC_ALLOC(char, strlen(s)+1), s) : NULL; }
static inline int Aig_BitWordNum( int nBits ) { return (nBits>>5) + ((nBits&31) > 0); } static inline int Aig_BitWordNum( int nBits ) { return (nBits>>5) + ((nBits&31) > 0); }
static inline int Aig_TruthWordNum( int nVars ) { return nVars <= 5 ? 1 : (1 << (nVars - 5)); } static inline int Aig_TruthWordNum( int nVars ) { return nVars <= 5 ? 1 : (1 << (nVars - 5)); }
@ -261,6 +267,7 @@ static inline int Aig_ManGetCost( Aig_Man_t * p ) { return p->nO
static inline int Aig_ManObjNum( Aig_Man_t * p ) { return p->nCreated - p->nDeleted; } static inline int Aig_ManObjNum( Aig_Man_t * p ) { return p->nCreated - p->nDeleted; }
static inline int Aig_ManObjNumMax( Aig_Man_t * p ) { return Vec_PtrSize(p->vObjs); } static inline int Aig_ManObjNumMax( Aig_Man_t * p ) { return Vec_PtrSize(p->vObjs); }
static inline int Aig_ManRegNum( Aig_Man_t * p ) { return p->nRegs; } static inline int Aig_ManRegNum( Aig_Man_t * p ) { return p->nRegs; }
static inline int Aig_ManConstrNum( Aig_Man_t * p ) { return p->nConstrs; }
static inline Aig_Obj_t * Aig_ManConst0( Aig_Man_t * p ) { return Aig_Not(p->pConst1); } static inline Aig_Obj_t * Aig_ManConst0( Aig_Man_t * p ) { return Aig_Not(p->pConst1); }
static inline Aig_Obj_t * Aig_ManConst1( Aig_Man_t * p ) { return p->pConst1; } static inline Aig_Obj_t * Aig_ManConst1( Aig_Man_t * p ) { return p->pConst1; }
@ -284,6 +291,7 @@ static inline int Aig_ObjIsNode( Aig_Obj_t * pObj ) { return pObj-
static inline int Aig_ObjIsTerm( Aig_Obj_t * pObj ) { return pObj->Type == AIG_OBJ_PI || pObj->Type == AIG_OBJ_PO || pObj->Type == AIG_OBJ_CONST1; } static inline int Aig_ObjIsTerm( Aig_Obj_t * pObj ) { return pObj->Type == AIG_OBJ_PI || pObj->Type == AIG_OBJ_PO || pObj->Type == AIG_OBJ_CONST1; }
static inline int Aig_ObjIsHash( Aig_Obj_t * pObj ) { return pObj->Type == AIG_OBJ_AND || pObj->Type == AIG_OBJ_EXOR; } static inline int Aig_ObjIsHash( Aig_Obj_t * pObj ) { return pObj->Type == AIG_OBJ_AND || pObj->Type == AIG_OBJ_EXOR; }
static inline int Aig_ObjIsChoice( Aig_Man_t * p, Aig_Obj_t * pObj ) { return p->pEquivs && p->pEquivs[pObj->Id] && pObj->nRefs > 0; } static inline int Aig_ObjIsChoice( Aig_Man_t * p, Aig_Obj_t * pObj ) { return p->pEquivs && p->pEquivs[pObj->Id] && pObj->nRefs > 0; }
static inline int Aig_ObjIsCand( Aig_Obj_t * pObj ) { return pObj->Type == AIG_OBJ_PI || pObj->Type == AIG_OBJ_AND || pObj->Type == AIG_OBJ_EXOR; }
static inline int Aig_ObjIsMarkA( Aig_Obj_t * pObj ) { return pObj->fMarkA; } static inline int Aig_ObjIsMarkA( Aig_Obj_t * pObj ) { return pObj->fMarkA; }
static inline void Aig_ObjSetMarkA( Aig_Obj_t * pObj ) { pObj->fMarkA = 1; } static inline void Aig_ObjSetMarkA( Aig_Obj_t * pObj ) { pObj->fMarkA = 1; }
@ -315,6 +323,9 @@ static inline Aig_Obj_t * Aig_ObjChild0Next( Aig_Obj_t * pObj ) { assert( !Aig
static inline Aig_Obj_t * Aig_ObjChild1Next( Aig_Obj_t * pObj ) { assert( !Aig_IsComplement(pObj) ); return Aig_ObjFanin1(pObj)? Aig_NotCond((Aig_Obj_t *)Aig_ObjFanin1(pObj)->pNext, Aig_ObjFaninC1(pObj)) : NULL; } static inline Aig_Obj_t * Aig_ObjChild1Next( Aig_Obj_t * pObj ) { assert( !Aig_IsComplement(pObj) ); return Aig_ObjFanin1(pObj)? Aig_NotCond((Aig_Obj_t *)Aig_ObjFanin1(pObj)->pNext, Aig_ObjFaninC1(pObj)) : NULL; }
static inline void Aig_ObjChild0Flip( Aig_Obj_t * pObj ) { assert( !Aig_IsComplement(pObj) ); pObj->pFanin0 = Aig_Not(pObj->pFanin0); } static inline void Aig_ObjChild0Flip( Aig_Obj_t * pObj ) { assert( !Aig_IsComplement(pObj) ); pObj->pFanin0 = Aig_Not(pObj->pFanin0); }
static inline void Aig_ObjChild1Flip( Aig_Obj_t * pObj ) { assert( !Aig_IsComplement(pObj) ); pObj->pFanin1 = Aig_Not(pObj->pFanin1); } static inline void Aig_ObjChild1Flip( Aig_Obj_t * pObj ) { assert( !Aig_IsComplement(pObj) ); pObj->pFanin1 = Aig_Not(pObj->pFanin1); }
static inline Aig_Obj_t * Aig_ObjCopy( Aig_Obj_t * pObj ) { assert( !Aig_IsComplement(pObj) ); return (Aig_Obj_t *)pObj->pData; }
static inline void Aig_ObjSetCopy( Aig_Obj_t * pObj, Aig_Obj_t * pCopy ) { assert( !Aig_IsComplement(pObj) ); pObj->pData = pCopy; }
static inline Aig_Obj_t * Aig_ObjRealCopy( Aig_Obj_t * pObj ) { return Aig_NotCond((Aig_Obj_t *)Aig_Regular(pObj)->pData, Aig_IsComplement(pObj));}
static inline int Aig_ObjLevel( Aig_Obj_t * pObj ) { assert( !Aig_IsComplement(pObj) ); return pObj->Level; } static inline int Aig_ObjLevel( Aig_Obj_t * pObj ) { assert( !Aig_IsComplement(pObj) ); return pObj->Level; }
static inline int Aig_ObjLevelNew( Aig_Obj_t * pObj ) { assert( !Aig_IsComplement(pObj) ); return Aig_ObjFanin1(pObj)? 1 + Aig_ObjIsExor(pObj) + ABC_MAX(Aig_ObjFanin0(pObj)->Level, Aig_ObjFanin1(pObj)->Level) : Aig_ObjFanin0(pObj)->Level; } static inline int Aig_ObjLevelNew( Aig_Obj_t * pObj ) { assert( !Aig_IsComplement(pObj) ); return Aig_ObjFanin1(pObj)? 1 + Aig_ObjIsExor(pObj) + ABC_MAX(Aig_ObjFanin0(pObj)->Level, Aig_ObjFanin1(pObj)->Level) : Aig_ObjFanin0(pObj)->Level; }
static inline int Aig_ObjSetLevel( Aig_Obj_t * pObj, int i ) { assert( !Aig_IsComplement(pObj) ); return pObj->Level = i; } static inline int Aig_ObjSetLevel( Aig_Obj_t * pObj, int i ) { assert( !Aig_IsComplement(pObj) ); return pObj->Level = i; }
@ -388,22 +399,22 @@ static inline void Aig_ManRecycleMemory( Aig_Man_t * p, Aig_Obj_t * pEntry )
// iterator over the primary inputs // iterator over the primary inputs
#define Aig_ManForEachPi( p, pObj, i ) \ #define Aig_ManForEachPi( p, pObj, i ) \
Vec_PtrForEachEntry( p->vPis, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, p->vPis, pObj, i )
// iterator over the primary outputs // iterator over the primary outputs
#define Aig_ManForEachPo( p, pObj, i ) \ #define Aig_ManForEachPo( p, pObj, i ) \
Vec_PtrForEachEntry( p->vPos, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, p->vPos, pObj, i )
// iterator over the assertions // iterator over the assertions
#define Aig_ManForEachAssert( p, pObj, i ) \ #define Aig_ManForEachAssert( p, pObj, i ) \
Vec_PtrForEachEntryStart( p->vPos, pObj, i, Aig_ManPoNum(p)-p->nAsserts ) Vec_PtrForEachEntryStart( Aig_Obj_t *, p->vPos, pObj, i, Aig_ManPoNum(p)-p->nAsserts )
// iterator over all objects, including those currently not used // iterator over all objects, including those currently not used
#define Aig_ManForEachObj( p, pObj, i ) \ #define Aig_ManForEachObj( p, pObj, i ) \
Vec_PtrForEachEntry( p->vObjs, pObj, i ) if ( (pObj) == NULL ) {} else Vec_PtrForEachEntry( Aig_Obj_t *, p->vObjs, pObj, i ) if ( (pObj) == NULL ) {} else
// iterator over all nodes // iterator over all nodes
#define Aig_ManForEachNode( p, pObj, i ) \ #define Aig_ManForEachNode( p, pObj, i ) \
Vec_PtrForEachEntry( p->vObjs, pObj, i ) if ( (pObj) == NULL || !Aig_ObjIsNode(pObj) ) {} else Vec_PtrForEachEntry( Aig_Obj_t *, p->vObjs, pObj, i ) if ( (pObj) == NULL || !Aig_ObjIsNode(pObj) ) {} else
// iterator over all nodes // iterator over all nodes
#define Aig_ManForEachExor( p, pObj, i ) \ #define Aig_ManForEachExor( p, pObj, i ) \
Vec_PtrForEachEntry( p->vObjs, pObj, i ) if ( (pObj) == NULL || !Aig_ObjIsExor(pObj) ) {} else Vec_PtrForEachEntry( Aig_Obj_t *, p->vObjs, pObj, i ) if ( (pObj) == NULL || !Aig_ObjIsExor(pObj) ) {} else
// iterator over the nodes whose IDs are stored in the array // iterator over the nodes whose IDs are stored in the array
#define Aig_ManForEachNodeVec( p, vIds, pObj, i ) \ #define Aig_ManForEachNodeVec( p, vIds, pObj, i ) \
for ( i = 0; i < Vec_IntSize(vIds) && ((pObj) = Aig_ManObj(p, Vec_IntEntry(vIds,i))); i++ ) for ( i = 0; i < Vec_IntSize(vIds) && ((pObj) = Aig_ManObj(p, Vec_IntEntry(vIds,i))); i++ )
@ -429,16 +440,16 @@ static inline int Aig_ObjFanoutNext( Aig_Man_t * p, int iFan ) { assert(iF
// iterator over the primary inputs // iterator over the primary inputs
#define Aig_ManForEachPiSeq( p, pObj, i ) \ #define Aig_ManForEachPiSeq( p, pObj, i ) \
Vec_PtrForEachEntryStop( p->vPis, pObj, i, Aig_ManPiNum(p)-Aig_ManRegNum(p) ) Vec_PtrForEachEntryStop( Aig_Obj_t *, p->vPis, pObj, i, Aig_ManPiNum(p)-Aig_ManRegNum(p) )
// iterator over the latch outputs // iterator over the latch outputs
#define Aig_ManForEachLoSeq( p, pObj, i ) \ #define Aig_ManForEachLoSeq( p, pObj, i ) \
Vec_PtrForEachEntryStart( p->vPis, pObj, i, Aig_ManPiNum(p)-Aig_ManRegNum(p) ) Vec_PtrForEachEntryStart( Aig_Obj_t *, p->vPis, pObj, i, Aig_ManPiNum(p)-Aig_ManRegNum(p) )
// iterator over the primary outputs // iterator over the primary outputs
#define Aig_ManForEachPoSeq( p, pObj, i ) \ #define Aig_ManForEachPoSeq( p, pObj, i ) \
Vec_PtrForEachEntryStop( p->vPos, pObj, i, Aig_ManPoNum(p)-Aig_ManRegNum(p) ) Vec_PtrForEachEntryStop( Aig_Obj_t *, p->vPos, pObj, i, Aig_ManPoNum(p)-Aig_ManRegNum(p) )
// iterator over the latch inputs // iterator over the latch inputs
#define Aig_ManForEachLiSeq( p, pObj, i ) \ #define Aig_ManForEachLiSeq( p, pObj, i ) \
Vec_PtrForEachEntryStart( p->vPos, pObj, i, Aig_ManPoNum(p)-Aig_ManRegNum(p) ) Vec_PtrForEachEntryStart( Aig_Obj_t *, p->vPos, pObj, i, Aig_ManPoNum(p)-Aig_ManRegNum(p) )
// iterator over the latch input and outputs // iterator over the latch input and outputs
#define Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, k ) \ #define Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, k ) \
for ( k = 0; (k < Aig_ManRegNum(p)) && (((pObjLi) = Aig_ManLi(p, k)), 1) \ for ( k = 0; (k < Aig_ManRegNum(p)) && (((pObjLi) = Aig_ManLi(p, k)), 1) \
@ -475,10 +486,13 @@ extern Aig_Obj_t * Aig_Compose( Aig_Man_t * p, Aig_Obj_t * pRoot, Aig_Obj_t
extern void Aig_ObjCollectCut( Aig_Obj_t * pRoot, Vec_Ptr_t * vLeaves, Vec_Ptr_t * vNodes ); extern void Aig_ObjCollectCut( Aig_Obj_t * pRoot, Vec_Ptr_t * vLeaves, Vec_Ptr_t * vNodes );
extern int Aig_ObjCollectSuper( Aig_Obj_t * pObj, Vec_Ptr_t * vSuper ); extern int Aig_ObjCollectSuper( Aig_Obj_t * pObj, Vec_Ptr_t * vSuper );
/*=== aigDup.c ==========================================================*/ /*=== aigDup.c ==========================================================*/
extern Aig_Obj_t * Aig_ManDupSimpleDfs_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t * pObj );
extern Aig_Man_t * Aig_ManDupSimple( Aig_Man_t * p ); extern Aig_Man_t * Aig_ManDupSimple( Aig_Man_t * p );
extern Aig_Man_t * Aig_ManDupSimpleWithHints( Aig_Man_t * p, Vec_Int_t * vHints );
extern Aig_Man_t * Aig_ManDupSimpleDfs( Aig_Man_t * p ); extern Aig_Man_t * Aig_ManDupSimpleDfs( Aig_Man_t * p );
extern Aig_Man_t * Aig_ManDupSimpleDfsPart( Aig_Man_t * p, Vec_Ptr_t * vPis, Vec_Ptr_t * vPos ); extern Aig_Man_t * Aig_ManDupSimpleDfsPart( Aig_Man_t * p, Vec_Ptr_t * vPis, Vec_Ptr_t * vPos );
extern Aig_Man_t * Aig_ManDupOrdered( Aig_Man_t * p ); extern Aig_Man_t * Aig_ManDupOrdered( Aig_Man_t * p );
extern Aig_Man_t * Aig_ManDupCof( Aig_Man_t * p, int iInput, int Value );
extern Aig_Man_t * Aig_ManDupTrim( Aig_Man_t * p ); extern Aig_Man_t * Aig_ManDupTrim( Aig_Man_t * p );
extern Aig_Man_t * Aig_ManDupExor( Aig_Man_t * p ); extern Aig_Man_t * Aig_ManDupExor( Aig_Man_t * p );
extern Aig_Man_t * Aig_ManDupDfs( Aig_Man_t * p ); extern Aig_Man_t * Aig_ManDupDfs( Aig_Man_t * p );
@ -503,7 +517,8 @@ extern Aig_Man_t * Aig_ManFrames( Aig_Man_t * pAig, int nFs, int fInit, int
extern Aig_Man_t * Aig_ManStart( int nNodesMax ); extern Aig_Man_t * Aig_ManStart( int nNodesMax );
extern Aig_Man_t * Aig_ManStartFrom( Aig_Man_t * p ); extern Aig_Man_t * Aig_ManStartFrom( Aig_Man_t * p );
extern Aig_Man_t * Aig_ManExtractMiter( Aig_Man_t * p, Aig_Obj_t * pNode1, Aig_Obj_t * pNode2 ); extern Aig_Man_t * Aig_ManExtractMiter( Aig_Man_t * p, Aig_Obj_t * pNode1, Aig_Obj_t * pNode2 );
extern ABC_DLL void Aig_ManStop( Aig_Man_t * p ); extern void Aig_ManStop( Aig_Man_t * p );
extern void Aig_ManStopP( Aig_Man_t ** p );
extern int Aig_ManCleanup( Aig_Man_t * p ); extern int Aig_ManCleanup( Aig_Man_t * p );
extern int Aig_ManAntiCleanup( Aig_Man_t * p ); extern int Aig_ManAntiCleanup( Aig_Man_t * p );
extern int Aig_ManPiCleanup( Aig_Man_t * p ); extern int Aig_ManPiCleanup( Aig_Man_t * p );
@ -512,6 +527,7 @@ extern void Aig_ManPrintStats( Aig_Man_t * p );
extern void Aig_ManReportImprovement( Aig_Man_t * p, Aig_Man_t * pNew ); extern void Aig_ManReportImprovement( Aig_Man_t * p, Aig_Man_t * pNew );
extern void Aig_ManSetRegNum( Aig_Man_t * p, int nRegs ); extern void Aig_ManSetRegNum( Aig_Man_t * p, int nRegs );
extern void Aig_ManFlipFirstPo( Aig_Man_t * p ); extern void Aig_ManFlipFirstPo( Aig_Man_t * p );
extern void * Aig_ManReleaseData( Aig_Man_t * p );
/*=== aigMem.c ==========================================================*/ /*=== aigMem.c ==========================================================*/
extern void Aig_ManStartMemory( Aig_Man_t * p ); extern void Aig_ManStartMemory( Aig_Man_t * p );
extern void Aig_ManStopMemory( Aig_Man_t * p ); extern void Aig_ManStopMemory( Aig_Man_t * p );
@ -620,6 +636,7 @@ extern Aig_Man_t * Aig_ManConstReduce( Aig_Man_t * p, int fVerbose );
/*=== aigUtil.c =========================================================*/ /*=== aigUtil.c =========================================================*/
extern unsigned Aig_PrimeCudd( unsigned p ); extern unsigned Aig_PrimeCudd( unsigned p );
extern void Aig_ManIncrementTravId( Aig_Man_t * p ); extern void Aig_ManIncrementTravId( Aig_Man_t * p );
extern char * Aig_TimeStamp();
extern int Aig_ManHasNoGaps( Aig_Man_t * p ); extern int Aig_ManHasNoGaps( Aig_Man_t * p );
extern int Aig_ManLevels( Aig_Man_t * p ); extern int Aig_ManLevels( Aig_Man_t * p );
extern void Aig_ManResetRefs( Aig_Man_t * p ); extern void Aig_ManResetRefs( Aig_Man_t * p );
@ -650,6 +667,10 @@ extern unsigned Aig_ManRandom( int fReset );
extern void Aig_ManRandomInfo( Vec_Ptr_t * vInfo, int iInputStart, int iWordStart, int iWordStop ); extern void Aig_ManRandomInfo( Vec_Ptr_t * vInfo, int iInputStart, int iWordStart, int iWordStop );
extern void Aig_NodeUnionLists( Vec_Ptr_t * vArr1, Vec_Ptr_t * vArr2, Vec_Ptr_t * vArr ); extern void Aig_NodeUnionLists( Vec_Ptr_t * vArr1, Vec_Ptr_t * vArr2, Vec_Ptr_t * vArr );
extern void Aig_NodeIntersectLists( Vec_Ptr_t * vArr1, Vec_Ptr_t * vArr2, Vec_Ptr_t * vArr ); extern void Aig_NodeIntersectLists( Vec_Ptr_t * vArr1, Vec_Ptr_t * vArr2, Vec_Ptr_t * vArr );
extern void Aig_ManSetPhase( Aig_Man_t * pAig );
extern Vec_Ptr_t * Aig_ManMuxesCollect( Aig_Man_t * pAig );
extern void Aig_ManMuxesDeref( Aig_Man_t * pAig, Vec_Ptr_t * vMuxes );
extern void Aig_ManMuxesRef( Aig_Man_t * pAig, Vec_Ptr_t * vMuxes );
/*=== aigWin.c =========================================================*/ /*=== aigWin.c =========================================================*/
extern void Aig_ManFindCut( Aig_Obj_t * pRoot, Vec_Ptr_t * vFront, Vec_Ptr_t * vVisited, int nSizeLimit, int nFanoutLimit ); extern void Aig_ManFindCut( Aig_Obj_t * pRoot, Vec_Ptr_t * vFront, Vec_Ptr_t * vVisited, int nSizeLimit, int nFanoutLimit );
@ -676,9 +697,11 @@ extern char * Aig_MmStepEntryFetch( Aig_MmStep_t * p, int nBytes );
extern void Aig_MmStepEntryRecycle( Aig_MmStep_t * p, char * pEntry, int nBytes ); extern void Aig_MmStepEntryRecycle( Aig_MmStep_t * p, char * pEntry, int nBytes );
extern int Aig_MmStepReadMemUsage( Aig_MmStep_t * p ); extern int Aig_MmStepReadMemUsage( Aig_MmStep_t * p );
#ifdef __cplusplus
}
#endif ABC_NAMESPACE_HEADER_END
#endif #endif

10
src/aig/aig/aigCanon.c
View File

@ -21,6 +21,10 @@
#include "aig.h" #include "aig.h"
#include "kit.h" #include "kit.h"
#include "bdc.h" #include "bdc.h"
#include "ioa.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
@ -277,7 +281,7 @@ void Aig_RManStop( Aig_RMan_t * p )
***********************************************************************/ ***********************************************************************/
void Aig_RManQuit() void Aig_RManQuit()
{ {
extern void Ioa_WriteAiger( Aig_Man_t * pMan, char * pFileName, int fWriteSymbols, int fCompact ); // extern void Ioa_WriteAiger( Aig_Man_t * pMan, char * pFileName, int fWriteSymbols, int fCompact );
char Buffer[20]; char Buffer[20];
if ( s_pRMan == NULL ) if ( s_pRMan == NULL )
return; return;
@ -537,7 +541,7 @@ unsigned Aig_RManSemiCanonicize( unsigned * pOut, unsigned * pIn, int nVars, cha
***********************************************************************/ ***********************************************************************/
static inline Aig_Obj_t * Bdc_FunCopyHop( Bdc_Fun_t * pObj ) static inline Aig_Obj_t * Bdc_FunCopyHop( Bdc_Fun_t * pObj )
{ return Aig_NotCond( Bdc_FuncCopy(Bdc_Regular(pObj)), Bdc_IsComplement(pObj) ); } { return Aig_NotCond( (Aig_Obj_t *)Bdc_FuncCopy(Bdc_Regular(pObj)), Bdc_IsComplement(pObj) ); }
/**Function************************************************************* /**Function*************************************************************
@ -692,3 +696,5 @@ Extra_PrintBinary( stdout, s_pRMan->pTruth, 1<<nVars ); printf( "\n\n" );
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

5
src/aig/aig/aigCheck.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -161,3 +164,5 @@ void Aig_ManCheckPhase( Aig_Man_t * p )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

7
src/aig/aig/aigCuts.c
View File

@ -21,6 +21,9 @@
#include "aig.h" #include "aig.h"
#include "kit.h" #include "kit.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -207,7 +210,7 @@ static inline float Aig_CutFindCost2( Aig_ManCut_t * p, Aig_Cut_t * pCut )
/**Function************************************************************* /**Function*************************************************************
Synopsis [Returns the next ABC_FREE cut to use.] Synopsis [Returns the next free cut to use.]
Description [] Description []
@ -667,3 +670,5 @@ Aig_ManCut_t * Aig_ComputeCuts( Aig_Man_t * pAig, int nCutsMax, int nLeafMax, in
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

34
src/aig/aig/aigDfs.c
View File

@ -21,6 +21,9 @@
#include "aig.h" #include "aig.h"
#include "tim.h" #include "tim.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -76,15 +79,15 @@ int Aig_ManVerifyTopoOrder( Aig_Man_t * p )
{ {
if ( p->pManTime ) if ( p->pManTime )
{ {
iBox = Tim_ManBoxForCi( p->pManTime, Aig_ObjPioNum(pObj) ); iBox = Tim_ManBoxForCi( (Tim_Man_t *)p->pManTime, Aig_ObjPioNum(pObj) );
if ( iBox >= 0 ) // this is not a true PI if ( iBox >= 0 ) // this is not a true PI
{ {
iTerm1 = Tim_ManBoxInputFirst( p->pManTime, iBox ); iTerm1 = Tim_ManBoxInputFirst( (Tim_Man_t *)p->pManTime, iBox );
nTerms = Tim_ManBoxInputNum( p->pManTime, iBox ); nTerms = Tim_ManBoxInputNum( (Tim_Man_t *)p->pManTime, iBox );
for ( k = 0; k < nTerms; k++ ) for ( k = 0; k < nTerms; k++ )
{ {
pNext = Aig_ManPo( p, iTerm1 + k ); pNext = Aig_ManPo( p, iTerm1 + k );
assert( Tim_ManBoxForCo( p->pManTime, Aig_ObjPioNum(pNext) ) == iBox ); assert( Tim_ManBoxForCo( (Tim_Man_t *)p->pManTime, Aig_ObjPioNum(pNext) ) == iBox );
if ( !Aig_ObjIsTravIdCurrent(p,pNext) ) if ( !Aig_ObjIsTravIdCurrent(p,pNext) )
{ {
printf( "Box %d has input %d that is not in a topological order.\n", iBox, pNext->Id ); printf( "Box %d has input %d that is not in a topological order.\n", iBox, pNext->Id );
@ -276,6 +279,9 @@ Vec_Ptr_t * Aig_ManDfsNodes( Aig_Man_t * p, Aig_Obj_t ** ppNodes, int nNodes )
// go through the nodes // go through the nodes
vNodes = Vec_PtrAlloc( Aig_ManNodeNum(p) ); vNodes = Vec_PtrAlloc( Aig_ManNodeNum(p) );
for ( i = 0; i < nNodes; i++ ) for ( i = 0; i < nNodes; i++ )
if ( Aig_ObjIsPo(ppNodes[i]) )
Aig_ManDfs_rec( p, Aig_ObjFanin0(ppNodes[i]), vNodes );
else
Aig_ManDfs_rec( p, ppNodes[i], vNodes ); Aig_ManDfs_rec( p, ppNodes[i], vNodes );
return vNodes; return vNodes;
} }
@ -435,11 +441,11 @@ void Aig_ManChoiceLevel_rec( Aig_Man_t * p, Aig_Obj_t * pObj )
{ {
if ( p->pManTime ) if ( p->pManTime )
{ {
iBox = Tim_ManBoxForCi( p->pManTime, Aig_ObjPioNum(pObj) ); iBox = Tim_ManBoxForCi( (Tim_Man_t *)p->pManTime, Aig_ObjPioNum(pObj) );
if ( iBox >= 0 ) // this is not a true PI if ( iBox >= 0 ) // this is not a true PI
{ {
iTerm1 = Tim_ManBoxInputFirst( p->pManTime, iBox ); iTerm1 = Tim_ManBoxInputFirst( (Tim_Man_t *)p->pManTime, iBox );
nTerms = Tim_ManBoxInputNum( p->pManTime, iBox ); nTerms = Tim_ManBoxInputNum( (Tim_Man_t *)p->pManTime, iBox );
for ( i = 0; i < nTerms; i++ ) for ( i = 0; i < nTerms; i++ )
{ {
pNext = Aig_ManPo(p, iTerm1 + i); pNext = Aig_ManPo(p, iTerm1 + i);
@ -815,7 +821,7 @@ Aig_Obj_t * Aig_Transfer( Aig_Man_t * pSour, Aig_Man_t * pDest, Aig_Obj_t * pRoo
Aig_Transfer_rec( pDest, Aig_Regular(pRoot) ); Aig_Transfer_rec( pDest, Aig_Regular(pRoot) );
// clear the markings // clear the markings
Aig_ConeUnmark_rec( Aig_Regular(pRoot) ); Aig_ConeUnmark_rec( Aig_Regular(pRoot) );
return Aig_NotCond( Aig_Regular(pRoot)->pData, Aig_IsComplement(pRoot) ); return Aig_NotCond( (Aig_Obj_t *)Aig_Regular(pRoot)->pData, Aig_IsComplement(pRoot) );
} }
/**Function************************************************************* /**Function*************************************************************
@ -869,7 +875,7 @@ Aig_Obj_t * Aig_Compose( Aig_Man_t * p, Aig_Obj_t * pRoot, Aig_Obj_t * pFunc, in
Aig_Compose_rec( p, Aig_Regular(pRoot), pFunc, Aig_ManPi(p, iVar) ); Aig_Compose_rec( p, Aig_Regular(pRoot), pFunc, Aig_ManPi(p, iVar) );
// clear the markings // clear the markings
Aig_ConeUnmark_rec( Aig_Regular(pRoot) ); Aig_ConeUnmark_rec( Aig_Regular(pRoot) );
return Aig_NotCond( Aig_Regular(pRoot)->pData, Aig_IsComplement(pRoot) ); return Aig_NotCond( (Aig_Obj_t *)Aig_Regular(pRoot)->pData, Aig_IsComplement(pRoot) );
} }
/**Function************************************************************* /**Function*************************************************************
@ -914,7 +920,7 @@ void Aig_ObjCollectCut( Aig_Obj_t * pRoot, Vec_Ptr_t * vLeaves, Vec_Ptr_t * vNod
int i; int i;
// collect and mark the leaves // collect and mark the leaves
Vec_PtrClear( vNodes ); Vec_PtrClear( vNodes );
Vec_PtrForEachEntry( vLeaves, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vLeaves, pObj, i )
{ {
assert( pObj->fMarkA == 0 ); assert( pObj->fMarkA == 0 );
pObj->fMarkA = 1; pObj->fMarkA = 1;
@ -924,9 +930,9 @@ void Aig_ObjCollectCut( Aig_Obj_t * pRoot, Vec_Ptr_t * vLeaves, Vec_Ptr_t * vNod
// collect and mark the nodes // collect and mark the nodes
Aig_ObjCollectCut_rec( pRoot, vNodes ); Aig_ObjCollectCut_rec( pRoot, vNodes );
// clean the nodes // clean the nodes
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
pObj->fMarkA = 0; pObj->fMarkA = 0;
Vec_PtrForEachEntry( vLeaves, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vLeaves, pObj, i )
pObj->fMarkA = 0; pObj->fMarkA = 0;
} }
@ -998,7 +1004,7 @@ int Aig_ObjCollectSuper( Aig_Obj_t * pObj, Vec_Ptr_t * vSuper )
RetValue = Aig_ObjCollectSuper_rec( pObj, pObj, vSuper ); RetValue = Aig_ObjCollectSuper_rec( pObj, pObj, vSuper );
assert( Vec_PtrSize(vSuper) > 1 ); assert( Vec_PtrSize(vSuper) > 1 );
// unmark the visited nodes // unmark the visited nodes
Vec_PtrForEachEntry( vSuper, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vSuper, pObj, i )
Aig_Regular(pObj)->fMarkA = 0; Aig_Regular(pObj)->fMarkA = 0;
// if we found the node and its complement in the same implication supergate, // if we found the node and its complement in the same implication supergate,
// return empty set of nodes (meaning that we should use constant-0 node) // return empty set of nodes (meaning that we should use constant-0 node)
@ -1012,3 +1018,5 @@ int Aig_ObjCollectSuper( Aig_Obj_t * pObj, Vec_Ptr_t * vSuper )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

204
src/aig/aig/aigDup.c
View File

@ -21,6 +21,9 @@
#include "saig.h" #include "saig.h"
#include "tim.h" #include "tim.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -52,6 +55,7 @@ Aig_Man_t * Aig_ManDupSimple( Aig_Man_t * p )
pNew->pName = Aig_UtilStrsav( p->pName ); pNew->pName = Aig_UtilStrsav( p->pName );
pNew->pSpec = Aig_UtilStrsav( p->pSpec ); pNew->pSpec = Aig_UtilStrsav( p->pSpec );
pNew->nAsserts = p->nAsserts; pNew->nAsserts = p->nAsserts;
pNew->nConstrs = p->nConstrs;
if ( p->vFlopNums ) if ( p->vFlopNums )
pNew->vFlopNums = Vec_IntDup( p->vFlopNums ); pNew->vFlopNums = Vec_IntDup( p->vFlopNums );
// create the PIs // create the PIs
@ -100,6 +104,57 @@ Aig_Man_t * Aig_ManDupSimple( Aig_Man_t * p )
return pNew; return pNew;
} }
/**Function*************************************************************
Synopsis [Derives AIG with hints.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Aig_ManDupSimpleWithHints( Aig_Man_t * p, Vec_Int_t * vHints )
{
Aig_Man_t * pNew;
Aig_Obj_t * pObj;
int i, Entry;
assert( p->pManHaig == NULL || Aig_ManBufNum(p) == 0 );
assert( p->nAsserts == 0 || p->nConstrs == 0 );
// create the new manager
pNew = Aig_ManStart( Aig_ManObjNumMax(p) );
pNew->pName = Aig_UtilStrsav( p->pName );
// create the PIs
Aig_ManCleanData( p );
Aig_ManConst1(p)->pData = Aig_ManConst1(pNew);
Aig_ManForEachPi( p, pObj, i )
{
pObj->pData = Aig_ObjCreatePi( pNew );
Entry = Vec_IntEntry( vHints, Aig_ObjId(pObj) );
if ( Entry == 0 || Entry == 1 )
pObj->pData = Aig_NotCond( Aig_ManConst1(pNew), Entry ); // restrict to the complement of constraint!!!
}
// duplicate internal nodes
Aig_ManForEachNode( p, pObj, i )
{
pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
Entry = Vec_IntEntry( vHints, Aig_ObjId(pObj) );
if ( Entry == 0 || Entry == 1 )
pObj->pData = Aig_NotCond( Aig_ManConst1(pNew), Entry ); // restrict to the complement of constraint!!!
}
// add the POs
Aig_ManForEachPo( p, pObj, i )
pObj->pData = Aig_ObjCreatePo( pNew, Aig_ObjChild0Copy(pObj) );
Aig_ManCleanup( pNew );
Aig_ManSetRegNum( pNew, Aig_ManRegNum(p) );
// check the resulting network
if ( !Aig_ManCheck(pNew) )
printf( "Llb_ManDeriveAigWithHints(): The check has failed.\n" );
return pNew;
}
/**Function************************************************************* /**Function*************************************************************
Synopsis [Duplicates the AIG manager recursively.] Synopsis [Duplicates the AIG manager recursively.]
@ -114,14 +169,14 @@ Aig_Man_t * Aig_ManDupSimple( Aig_Man_t * p )
Aig_Obj_t * Aig_ManDupSimpleDfs_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t * pObj ) Aig_Obj_t * Aig_ManDupSimpleDfs_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t * pObj )
{ {
if ( pObj->pData ) if ( pObj->pData )
return pObj->pData; return (Aig_Obj_t *)pObj->pData;
Aig_ManDupSimpleDfs_rec( pNew, p, Aig_ObjFanin0(pObj) ); Aig_ManDupSimpleDfs_rec( pNew, p, Aig_ObjFanin0(pObj) );
if ( Aig_ObjIsBuf(pObj) ) if ( Aig_ObjIsBuf(pObj) )
return pObj->pData = Aig_ObjChild0Copy(pObj); return (Aig_Obj_t *)(pObj->pData = Aig_ObjChild0Copy(pObj));
Aig_ManDupSimpleDfs_rec( pNew, p, Aig_ObjFanin1(pObj) ); Aig_ManDupSimpleDfs_rec( pNew, p, Aig_ObjFanin1(pObj) );
pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) ); pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
Aig_Regular(pObj->pData)->pHaig = pObj->pHaig; Aig_Regular((Aig_Obj_t *)pObj->pData)->pHaig = pObj->pHaig;
return pObj->pData; return (Aig_Obj_t *)pObj->pData;
} }
/**Function************************************************************* /**Function*************************************************************
@ -151,6 +206,7 @@ Aig_Man_t * Aig_ManDupSimpleDfs( Aig_Man_t * p )
pNew->pName = Aig_UtilStrsav( p->pName ); pNew->pName = Aig_UtilStrsav( p->pName );
pNew->pSpec = Aig_UtilStrsav( p->pSpec ); pNew->pSpec = Aig_UtilStrsav( p->pSpec );
pNew->nAsserts = p->nAsserts; pNew->nAsserts = p->nAsserts;
pNew->nConstrs = p->nConstrs;
if ( p->vFlopNums ) if ( p->vFlopNums )
pNew->vFlopNums = Vec_IntDup( p->vFlopNums ); pNew->vFlopNums = Vec_IntDup( p->vFlopNums );
// create the PIs // create the PIs
@ -213,10 +269,10 @@ Aig_Man_t * Aig_ManDupSimpleDfsPart( Aig_Man_t * p, Vec_Ptr_t * vPis, Vec_Ptr_t
// create the PIs // create the PIs
Aig_ManCleanData( p ); Aig_ManCleanData( p );
Aig_ManConst1(p)->pData = Aig_ManConst1( pNew ); Aig_ManConst1(p)->pData = Aig_ManConst1( pNew );
Vec_PtrForEachEntry( vPis, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vPis, pObj, i )
pObj->pData = Aig_ObjCreatePi( pNew ); pObj->pData = Aig_ObjCreatePi( pNew );
// duplicate internal nodes // duplicate internal nodes
Vec_PtrForEachEntry( vPos, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vPos, pObj, i )
{ {
pObjNew = Aig_ManDupSimpleDfs_rec( pNew, p, Aig_ObjFanin0(pObj) ); pObjNew = Aig_ManDupSimpleDfs_rec( pNew, p, Aig_ObjFanin0(pObj) );
pObjNew = Aig_NotCond( pObjNew, Aig_ObjFaninC0(pObj) ); pObjNew = Aig_NotCond( pObjNew, Aig_ObjFaninC0(pObj) );
@ -250,6 +306,7 @@ Aig_Man_t * Aig_ManDupOrdered( Aig_Man_t * p )
pNew->pName = Aig_UtilStrsav( p->pName ); pNew->pName = Aig_UtilStrsav( p->pName );
pNew->pSpec = Aig_UtilStrsav( p->pSpec ); pNew->pSpec = Aig_UtilStrsav( p->pSpec );
pNew->nAsserts = p->nAsserts; pNew->nAsserts = p->nAsserts;
pNew->nConstrs = p->nConstrs;
if ( p->vFlopNums ) if ( p->vFlopNums )
pNew->vFlopNums = Vec_IntDup( p->vFlopNums ); pNew->vFlopNums = Vec_IntDup( p->vFlopNums );
// create the PIs // create the PIs
@ -289,7 +346,7 @@ Aig_Man_t * Aig_ManDupOrdered( Aig_Man_t * p )
Aig_ManSetRegNum( pNew, Aig_ManRegNum(p) ); Aig_ManSetRegNum( pNew, Aig_ManRegNum(p) );
// duplicate the timing manager // duplicate the timing manager
if ( p->pManTime ) if ( p->pManTime )
pNew->pManTime = Tim_ManDup( p->pManTime, 0 ); pNew->pManTime = Tim_ManDup( (Tim_Man_t *)p->pManTime, 0 );
// pass the HAIG manager // pass the HAIG manager
if ( p->pManHaig != NULL ) if ( p->pManHaig != NULL )
{ {
@ -301,6 +358,86 @@ Aig_Man_t * Aig_ManDupOrdered( Aig_Man_t * p )
printf( "Aig_ManDupOrdered(): The check has failed.\n" ); printf( "Aig_ManDupOrdered(): The check has failed.\n" );
return pNew; return pNew;
} }
/**Function*************************************************************
Synopsis [Duplicates the AIG manager.]
Description [Orders nodes as follows: PIs, ANDs, POs.]
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Aig_ManDupCof( Aig_Man_t * p, int iInput, int Value )
{
Aig_Man_t * pNew;
Aig_Obj_t * pObj, * pObjNew;
int i;
assert( p->pManTime == NULL );
assert( p->pManHaig == NULL || Aig_ManBufNum(p) == 0 );
// create the new manager
pNew = Aig_ManStart( Aig_ManObjNumMax(p) );
pNew->pName = Aig_UtilStrsav( p->pName );
pNew->pSpec = Aig_UtilStrsav( p->pSpec );
pNew->nAsserts = p->nAsserts;
pNew->nConstrs = p->nConstrs;
if ( p->vFlopNums )
pNew->vFlopNums = Vec_IntDup( p->vFlopNums );
// create the PIs
Aig_ManCleanData( p );
Aig_ManConst1(p)->pData = Aig_ManConst1(pNew);
Aig_ManConst1(pNew)->pHaig = Aig_ManConst1(p)->pHaig;
Aig_ManForEachPi( p, pObj, i )
{
if ( i == iInput )
pObjNew = Value ? Aig_ManConst1(pNew) : Aig_ManConst0(pNew);
else
{
pObjNew = Aig_ObjCreatePi( pNew );
pObjNew->pHaig = pObj->pHaig;
pObjNew->Level = pObj->Level;
}
pObj->pData = pObjNew;
}
// duplicate internal nodes
Aig_ManForEachObj( p, pObj, i )
if ( Aig_ObjIsBuf(pObj) )
{
pObjNew = Aig_ObjChild0Copy(pObj);
Aig_Regular(pObjNew)->pHaig = pObj->pHaig;
pObj->pData = pObjNew;
}
else if ( Aig_ObjIsNode(pObj) )
{
pObjNew = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
Aig_Regular(pObjNew)->pHaig = pObj->pHaig;
pObj->pData = pObjNew;
}
// add the POs
Aig_ManForEachPo( p, pObj, i )
{
pObjNew = Aig_ObjCreatePo( pNew, Aig_ObjChild0Copy(pObj) );
pObjNew->pHaig = pObj->pHaig;
pObj->pData = pObjNew;
}
// assert( Aig_ManBufNum(p) != 0 || Aig_ManNodeNum(p) == Aig_ManNodeNum(pNew) );
Aig_ManCleanup( pNew );
Aig_ManSetRegNum( pNew, Aig_ManRegNum(p) );
// pass the HAIG manager
if ( p->pManHaig != NULL )
{
pNew->pManHaig = p->pManHaig;
p->pManHaig = NULL;
}
// check the resulting network
if ( !Aig_ManCheck(pNew) )
printf( "Aig_ManDupSimple(): The check has failed.\n" );
return pNew;
}
/**Function************************************************************* /**Function*************************************************************
Synopsis [Duplicates the AIG manager.] Synopsis [Duplicates the AIG manager.]
@ -321,6 +458,7 @@ Aig_Man_t * Aig_ManDupTrim( Aig_Man_t * p )
pNew = Aig_ManStart( Aig_ManObjNumMax(p) ); pNew = Aig_ManStart( Aig_ManObjNumMax(p) );
pNew->pName = Aig_UtilStrsav( p->pName ); pNew->pName = Aig_UtilStrsav( p->pName );
pNew->pSpec = Aig_UtilStrsav( p->pSpec ); pNew->pSpec = Aig_UtilStrsav( p->pSpec );
pNew->nConstrs = p->nConstrs;
// create the PIs // create the PIs
Aig_ManCleanData( p ); Aig_ManCleanData( p );
// duplicate internal nodes // duplicate internal nodes
@ -370,6 +508,7 @@ Aig_Man_t * Aig_ManDupExor( Aig_Man_t * p )
pNew->pName = Aig_UtilStrsav( p->pName ); pNew->pName = Aig_UtilStrsav( p->pName );
pNew->pSpec = Aig_UtilStrsav( p->pSpec ); pNew->pSpec = Aig_UtilStrsav( p->pSpec );
pNew->nAsserts = p->nAsserts; pNew->nAsserts = p->nAsserts;
pNew->nConstrs = p->nConstrs;
if ( p->vFlopNums ) if ( p->vFlopNums )
pNew->vFlopNums = Vec_IntDup( p->vFlopNums ); pNew->vFlopNums = Vec_IntDup( p->vFlopNums );
// create the PIs // create the PIs
@ -407,7 +546,7 @@ Aig_Man_t * Aig_ManDupExor( Aig_Man_t * p )
Aig_ManSetRegNum( pNew, Aig_ManRegNum(p) ); Aig_ManSetRegNum( pNew, Aig_ManRegNum(p) );
// duplicate the timing manager // duplicate the timing manager
if ( p->pManTime ) if ( p->pManTime )
pNew->pManTime = Tim_ManDup( p->pManTime, 0 ); pNew->pManTime = Tim_ManDup( (Tim_Man_t *)p->pManTime, 0 );
// check the resulting network // check the resulting network
if ( !Aig_ManCheck(pNew) ) if ( !Aig_ManCheck(pNew) )
printf( "Aig_ManDupExor(): The check has failed.\n" ); printf( "Aig_ManDupExor(): The check has failed.\n" );
@ -429,12 +568,12 @@ Aig_Obj_t * Aig_ManDupDfs_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t * pObj
{ {
Aig_Obj_t * pObjNew, * pEquivNew = NULL; Aig_Obj_t * pObjNew, * pEquivNew = NULL;
if ( pObj->pData ) if ( pObj->pData )
return pObj->pData; return (Aig_Obj_t *)pObj->pData;
if ( p->pEquivs && Aig_ObjEquiv(p, pObj) ) if ( p->pEquivs && Aig_ObjEquiv(p, pObj) )
pEquivNew = Aig_ManDupDfs_rec( pNew, p, Aig_ObjEquiv(p, pObj) ); pEquivNew = Aig_ManDupDfs_rec( pNew, p, Aig_ObjEquiv(p, pObj) );
Aig_ManDupDfs_rec( pNew, p, Aig_ObjFanin0(pObj) ); Aig_ManDupDfs_rec( pNew, p, Aig_ObjFanin0(pObj) );
if ( Aig_ObjIsBuf(pObj) ) if ( Aig_ObjIsBuf(pObj) )
return pObj->pData = Aig_ObjChild0Copy(pObj); return (Aig_Obj_t *)(pObj->pData = Aig_ObjChild0Copy(pObj));
Aig_ManDupDfs_rec( pNew, p, Aig_ObjFanin1(pObj) ); Aig_ManDupDfs_rec( pNew, p, Aig_ObjFanin1(pObj) );
pObjNew = Aig_Oper( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj), Aig_ObjType(pObj) ); pObjNew = Aig_Oper( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj), Aig_ObjType(pObj) );
if ( p->pManHaig != NULL ) if ( p->pManHaig != NULL )
@ -448,7 +587,7 @@ Aig_Obj_t * Aig_ManDupDfs_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t * pObj
if ( pNew->pReprs ) if ( pNew->pReprs )
pNew->pReprs[Aig_Regular(pEquivNew)->Id] = Aig_Regular(pObjNew); pNew->pReprs[Aig_Regular(pEquivNew)->Id] = Aig_Regular(pObjNew);
} }
return pObj->pData = pObjNew; return (Aig_Obj_t *)(pObj->pData = pObjNew);
} }
/**Function************************************************************* /**Function*************************************************************
@ -472,6 +611,7 @@ Aig_Man_t * Aig_ManDupDfs( Aig_Man_t * p )
pNew->pName = Aig_UtilStrsav( p->pName ); pNew->pName = Aig_UtilStrsav( p->pName );
pNew->pSpec = Aig_UtilStrsav( p->pSpec ); pNew->pSpec = Aig_UtilStrsav( p->pSpec );
pNew->nAsserts = p->nAsserts; pNew->nAsserts = p->nAsserts;
pNew->nConstrs = p->nConstrs;
if ( p->vFlopNums ) if ( p->vFlopNums )
pNew->vFlopNums = Vec_IntDup( p->vFlopNums ); pNew->vFlopNums = Vec_IntDup( p->vFlopNums );
// duplicate representation of choice nodes // duplicate representation of choice nodes
@ -508,7 +648,7 @@ Aig_Man_t * Aig_ManDupDfs( Aig_Man_t * p )
Aig_ManSetRegNum( pNew, Aig_ManRegNum(p) ); Aig_ManSetRegNum( pNew, Aig_ManRegNum(p) );
// duplicate the timing manager // duplicate the timing manager
if ( p->pManTime ) if ( p->pManTime )
pNew->pManTime = Tim_ManDup( p->pManTime, 0 ); pNew->pManTime = Tim_ManDup( (Tim_Man_t *)p->pManTime, 0 );
// pass the HAIG manager // pass the HAIG manager
if ( p->pManHaig != NULL ) if ( p->pManHaig != NULL )
{ {
@ -567,7 +707,7 @@ Aig_Obj_t * Aig_ManDupDfsGuided_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t
{ {
Aig_Obj_t * pObjNew, * pEquivNew = NULL; Aig_Obj_t * pObjNew, * pEquivNew = NULL;
if ( pObj->pData ) if ( pObj->pData )
return pObj->pData; return (Aig_Obj_t *)pObj->pData;
if ( Aig_ObjIsPi(pObj) ) if ( Aig_ObjIsPi(pObj) )
return NULL; return NULL;
if ( p->pEquivs && Aig_ObjEquiv(p, pObj) ) if ( p->pEquivs && Aig_ObjEquiv(p, pObj) )
@ -575,7 +715,7 @@ Aig_Obj_t * Aig_ManDupDfsGuided_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t
if ( !Aig_ManDupDfsGuided_rec( pNew, p, Aig_ObjFanin0(pObj) ) ) if ( !Aig_ManDupDfsGuided_rec( pNew, p, Aig_ObjFanin0(pObj) ) )
return NULL; return NULL;
if ( Aig_ObjIsBuf(pObj) ) if ( Aig_ObjIsBuf(pObj) )
return pObj->pData = Aig_ObjChild0Copy(pObj); return (Aig_Obj_t *)(pObj->pData = Aig_ObjChild0Copy(pObj));
if ( !Aig_ManDupDfsGuided_rec( pNew, p, Aig_ObjFanin1(pObj) ) ) if ( !Aig_ManDupDfsGuided_rec( pNew, p, Aig_ObjFanin1(pObj) ) )
return NULL; return NULL;
pObjNew = Aig_Oper( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj), Aig_ObjType(pObj) ); pObjNew = Aig_Oper( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj), Aig_ObjType(pObj) );
@ -588,7 +728,7 @@ Aig_Obj_t * Aig_ManDupDfsGuided_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t
if ( pNew->pReprs ) if ( pNew->pReprs )
pNew->pReprs[Aig_Regular(pEquivNew)->Id] = Aig_Regular(pObjNew); pNew->pReprs[Aig_Regular(pEquivNew)->Id] = Aig_Regular(pObjNew);
} }
return pObj->pData = pObjNew; return (Aig_Obj_t *)(pObj->pData = pObjNew);
} }
/**Function************************************************************* /**Function*************************************************************
@ -612,6 +752,7 @@ Aig_Man_t * Aig_ManDupDfsGuided( Aig_Man_t * p, Vec_Ptr_t * vPios )
pNew->pName = Aig_UtilStrsav( p->pName ); pNew->pName = Aig_UtilStrsav( p->pName );
pNew->pSpec = Aig_UtilStrsav( p->pSpec ); pNew->pSpec = Aig_UtilStrsav( p->pSpec );
pNew->nAsserts = p->nAsserts; pNew->nAsserts = p->nAsserts;
pNew->nConstrs = p->nConstrs;
if ( p->vFlopNums ) if ( p->vFlopNums )
pNew->vFlopNums = Vec_IntDup( p->vFlopNums ); pNew->vFlopNums = Vec_IntDup( p->vFlopNums );
// duplicate representation of choice nodes // duplicate representation of choice nodes
@ -630,7 +771,7 @@ Aig_Man_t * Aig_ManDupDfsGuided( Aig_Man_t * p, Vec_Ptr_t * vPios )
// duplicate internal nodes // duplicate internal nodes
Aig_ManConst1(p)->pData = Aig_ManConst1(pNew); Aig_ManConst1(p)->pData = Aig_ManConst1(pNew);
Aig_ManConst1(pNew)->pHaig = Aig_ManConst1(p)->pHaig; Aig_ManConst1(pNew)->pHaig = Aig_ManConst1(p)->pHaig;
Vec_PtrForEachEntry( vPios, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vPios, pObj, i )
{ {
if ( Aig_ObjIsPi(pObj) ) if ( Aig_ObjIsPi(pObj) )
{ {
@ -654,7 +795,7 @@ Aig_Man_t * Aig_ManDupDfsGuided( Aig_Man_t * p, Vec_Ptr_t * vPios )
Aig_ManSetRegNum( pNew, Aig_ManRegNum(p) ); Aig_ManSetRegNum( pNew, Aig_ManRegNum(p) );
// duplicate the timing manager // duplicate the timing manager
if ( p->pManTime ) if ( p->pManTime )
pNew->pManTime = Tim_ManDup( p->pManTime, 0 ); pNew->pManTime = Tim_ManDup( (Tim_Man_t *)p->pManTime, 0 );
// check the resulting network // check the resulting network
if ( !Aig_ManCheck(pNew) ) if ( !Aig_ManCheck(pNew) )
printf( "Aig_ManDupDfs(): The check has failed.\n" ); printf( "Aig_ManDupDfs(): The check has failed.\n" );
@ -683,6 +824,7 @@ Aig_Man_t * Aig_ManDupLevelized( Aig_Man_t * p )
pNew->pName = Aig_UtilStrsav( p->pName ); pNew->pName = Aig_UtilStrsav( p->pName );
pNew->pSpec = Aig_UtilStrsav( p->pSpec ); pNew->pSpec = Aig_UtilStrsav( p->pSpec );
pNew->nAsserts = p->nAsserts; pNew->nAsserts = p->nAsserts;
pNew->nConstrs = p->nConstrs;
if ( p->vFlopNums ) if ( p->vFlopNums )
pNew->vFlopNums = Vec_IntDup( p->vFlopNums ); pNew->vFlopNums = Vec_IntDup( p->vFlopNums );
// duplicate representation of choice nodes // duplicate representation of choice nodes
@ -708,7 +850,7 @@ Aig_Man_t * Aig_ManDupLevelized( Aig_Man_t * p )
} }
// duplicate internal nodes // duplicate internal nodes
vLevels = Aig_ManLevelize( p ); vLevels = Aig_ManLevelize( p );
Vec_VecForEachEntry( vLevels, pObj, i, k ) Vec_VecForEachEntry( Aig_Obj_t *, vLevels, pObj, i, k )
{ {
pObjNew = Aig_Oper( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj), Aig_ObjType(pObj) ); pObjNew = Aig_Oper( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj), Aig_ObjType(pObj) );
Aig_Regular(pObjNew)->pHaig = pObj->pHaig; Aig_Regular(pObjNew)->pHaig = pObj->pHaig;
@ -728,7 +870,7 @@ Aig_Man_t * Aig_ManDupLevelized( Aig_Man_t * p )
Aig_ManSetRegNum( pNew, Aig_ManRegNum(p) ); Aig_ManSetRegNum( pNew, Aig_ManRegNum(p) );
// duplicate the timing manager // duplicate the timing manager
if ( p->pManTime ) if ( p->pManTime )
pNew->pManTime = Tim_ManDup( p->pManTime, 0 ); pNew->pManTime = Tim_ManDup( (Tim_Man_t *)p->pManTime, 0 );
// check the resulting network // check the resulting network
if ( !Aig_ManCheck(pNew) ) if ( !Aig_ManCheck(pNew) )
printf( "Aig_ManDupLevelized(): The check has failed.\n" ); printf( "Aig_ManDupLevelized(): The check has failed.\n" );
@ -787,8 +929,8 @@ static inline Aig_Obj_t * Aig_ObjGetRepres( Aig_Man_t * p, Aig_Obj_t * pObj )
{ {
Aig_Obj_t * pRepr; Aig_Obj_t * pRepr;
if ( (pRepr = Aig_ObjRepr(p, pObj)) ) if ( (pRepr = Aig_ObjRepr(p, pObj)) )
return Aig_NotCond( pRepr->pData, pObj->fPhase ^ pRepr->fPhase ); return Aig_NotCond( (Aig_Obj_t *)pRepr->pData, pObj->fPhase ^ pRepr->fPhase );
return pObj->pData; return (Aig_Obj_t *)pObj->pData;
} }
static inline Aig_Obj_t * Aig_ObjChild0Repres( Aig_Man_t * p, Aig_Obj_t * pObj ) { return Aig_NotCond( Aig_ObjGetRepres(p, Aig_ObjFanin0(pObj)), Aig_ObjFaninC0(pObj) ); } static inline Aig_Obj_t * Aig_ObjChild0Repres( Aig_Man_t * p, Aig_Obj_t * pObj ) { return Aig_NotCond( Aig_ObjGetRepres(p, Aig_ObjFanin0(pObj)), Aig_ObjFaninC0(pObj) ); }
static inline Aig_Obj_t * Aig_ObjChild1Repres( Aig_Man_t * p, Aig_Obj_t * pObj ) { return Aig_NotCond( Aig_ObjGetRepres(p, Aig_ObjFanin1(pObj)), Aig_ObjFaninC1(pObj) ); } static inline Aig_Obj_t * Aig_ObjChild1Repres( Aig_Man_t * p, Aig_Obj_t * pObj ) { return Aig_NotCond( Aig_ObjGetRepres(p, Aig_ObjFanin1(pObj)), Aig_ObjFaninC1(pObj) ); }
@ -813,6 +955,7 @@ Aig_Man_t * Aig_ManDupRepres( Aig_Man_t * p )
pNew = Aig_ManStart( Aig_ManObjNumMax(p) ); pNew = Aig_ManStart( Aig_ManObjNumMax(p) );
pNew->pName = Aig_UtilStrsav( p->pName ); pNew->pName = Aig_UtilStrsav( p->pName );
pNew->pSpec = Aig_UtilStrsav( p->pSpec ); pNew->pSpec = Aig_UtilStrsav( p->pSpec );
pNew->nConstrs = p->nConstrs;
if ( p->vFlopNums ) if ( p->vFlopNums )
pNew->vFlopNums = Vec_IntDup( p->vFlopNums ); pNew->vFlopNums = Vec_IntDup( p->vFlopNums );
// map the const and primary inputs // map the const and primary inputs
@ -855,15 +998,15 @@ Aig_Obj_t * Aig_ManDupRepres_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t * p
{ {
Aig_Obj_t * pRepr; Aig_Obj_t * pRepr;
if ( pObj->pData ) if ( pObj->pData )
return pObj->pData; return (Aig_Obj_t *)pObj->pData;
if ( (pRepr = Aig_ObjRepr(p, pObj)) ) if ( (pRepr = Aig_ObjRepr(p, pObj)) )
{ {
Aig_ManDupRepres_rec( pNew, p, pRepr ); Aig_ManDupRepres_rec( pNew, p, pRepr );
return pObj->pData = Aig_NotCond( pRepr->pData, pRepr->fPhase ^ pObj->fPhase ); return (Aig_Obj_t *)(pObj->pData = Aig_NotCond( (Aig_Obj_t *)pRepr->pData, pRepr->fPhase ^ pObj->fPhase ));
} }
Aig_ManDupRepres_rec( pNew, p, Aig_ObjFanin0(pObj) ); Aig_ManDupRepres_rec( pNew, p, Aig_ObjFanin0(pObj) );
Aig_ManDupRepres_rec( pNew, p, Aig_ObjFanin1(pObj) ); Aig_ManDupRepres_rec( pNew, p, Aig_ObjFanin1(pObj) );
return pObj->pData = Aig_And( pNew, Aig_ObjChild0Repres(p, pObj), Aig_ObjChild1Repres(p, pObj) ); return (Aig_Obj_t *)(pObj->pData = Aig_And( pNew, Aig_ObjChild0Repres(p, pObj), Aig_ObjChild1Repres(p, pObj) ));
} }
/**Function************************************************************* /**Function*************************************************************
@ -886,6 +1029,7 @@ Aig_Man_t * Aig_ManDupRepresDfs( Aig_Man_t * p )
pNew = Aig_ManStart( Aig_ManObjNumMax(p) ); pNew = Aig_ManStart( Aig_ManObjNumMax(p) );
pNew->pName = Aig_UtilStrsav( p->pName ); pNew->pName = Aig_UtilStrsav( p->pName );
pNew->pSpec = Aig_UtilStrsav( p->pSpec ); pNew->pSpec = Aig_UtilStrsav( p->pSpec );
pNew->nConstrs = p->nConstrs;
if ( p->vFlopNums ) if ( p->vFlopNums )
pNew->vFlopNums = Vec_IntDup( p->vFlopNums ); pNew->vFlopNums = Vec_IntDup( p->vFlopNums );
// map the const and primary inputs // map the const and primary inputs
@ -985,6 +1129,11 @@ Aig_Man_t * Aig_ManDupOrpos( Aig_Man_t * p, int fAddRegs )
Aig_Obj_t * pObj, * pMiter; Aig_Obj_t * pObj, * pMiter;
int i; int i;
assert( Aig_ManRegNum(p) > 0 ); assert( Aig_ManRegNum(p) > 0 );
if ( p->nConstrs > 0 )
{
printf( "The AIG manager should have no constraints.\n" );
return NULL;
}
// create the new manager // create the new manager
pNew = Aig_ManStart( Aig_ManObjNumMax(p) ); pNew = Aig_ManStart( Aig_ManObjNumMax(p) );
pNew->pName = Aig_UtilStrsav( p->pName ); pNew->pName = Aig_UtilStrsav( p->pName );
@ -1080,6 +1229,11 @@ Aig_Man_t * Aig_ManDupUnsolvedOutputs( Aig_Man_t * p, int fAddRegs )
Aig_Obj_t * pObj; Aig_Obj_t * pObj;
int i, nOuts = 0; int i, nOuts = 0;
assert( Aig_ManRegNum(p) > 0 ); assert( Aig_ManRegNum(p) > 0 );
if ( p->nConstrs > 0 )
{
printf( "The AIG manager should have no constraints.\n" );
return NULL;
}
// create the new manager // create the new manager
pNew = Aig_ManStart( Aig_ManObjNumMax(p) ); pNew = Aig_ManStart( Aig_ManObjNumMax(p) );
pNew->pName = Aig_UtilStrsav( p->pName ); pNew->pName = Aig_UtilStrsav( p->pName );
@ -1120,3 +1274,5 @@ Aig_Man_t * Aig_ManDupUnsolvedOutputs( Aig_Man_t * p, int fAddRegs )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

454
src/aig/aig/aigFact.c
View File

@ -19,6 +19,10 @@
***********************************************************************/ ***********************************************************************/
#include "aig.h" #include "aig.h"
#include "kit.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
@ -116,7 +120,7 @@ int Aig_ManFindConeOverlap( Aig_Man_t * p, Vec_Ptr_t * vImplics, Aig_Obj_t * pNo
assert( !Aig_IsComplement(pNode) ); assert( !Aig_IsComplement(pNode) );
assert( !Aig_ObjIsConst1(pNode) ); assert( !Aig_ObjIsConst1(pNode) );
Aig_ManIncrementTravId( p ); Aig_ManIncrementTravId( p );
Vec_PtrForEachEntry( vImplics, pTemp, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vImplics, pTemp, i )
Aig_ObjSetTravIdCurrent( p, Aig_Regular(pTemp) ); Aig_ObjSetTravIdCurrent( p, Aig_Regular(pTemp) );
Aig_ManIncrementTravId( p ); Aig_ManIncrementTravId( p );
return Aig_ManFindConeOverlap_rec( p, pNode ); return Aig_ManFindConeOverlap_rec( p, pNode );
@ -136,13 +140,13 @@ int Aig_ManFindConeOverlap( Aig_Man_t * p, Vec_Ptr_t * vImplics, Aig_Obj_t * pNo
Aig_Obj_t * Aig_ManDeriveNewCone_rec( Aig_Man_t * p, Aig_Obj_t * pNode ) Aig_Obj_t * Aig_ManDeriveNewCone_rec( Aig_Man_t * p, Aig_Obj_t * pNode )
{ {
if ( Aig_ObjIsTravIdCurrent( p, pNode ) ) if ( Aig_ObjIsTravIdCurrent( p, pNode ) )
return pNode->pData; return (Aig_Obj_t *)pNode->pData;
Aig_ObjSetTravIdCurrent( p, pNode ); Aig_ObjSetTravIdCurrent( p, pNode );
if ( Aig_ObjIsPi(pNode) ) if ( Aig_ObjIsPi(pNode) )
return pNode->pData = pNode; return (Aig_Obj_t *)(pNode->pData = pNode);
Aig_ManDeriveNewCone_rec( p, Aig_ObjFanin0(pNode) ); Aig_ManDeriveNewCone_rec( p, Aig_ObjFanin0(pNode) );
Aig_ManDeriveNewCone_rec( p, Aig_ObjFanin1(pNode) ); Aig_ManDeriveNewCone_rec( p, Aig_ObjFanin1(pNode) );
return pNode->pData = Aig_And( p, Aig_ObjChild0Copy(pNode), Aig_ObjChild1Copy(pNode) ); return (Aig_Obj_t *)(pNode->pData = Aig_And( p, Aig_ObjChild0Copy(pNode), Aig_ObjChild1Copy(pNode) ));
} }
/**Function************************************************************* /**Function*************************************************************
@ -163,7 +167,7 @@ Aig_Obj_t * Aig_ManDeriveNewCone( Aig_Man_t * p, Vec_Ptr_t * vImplics, Aig_Obj_t
assert( !Aig_IsComplement(pNode) ); assert( !Aig_IsComplement(pNode) );
assert( !Aig_ObjIsConst1(pNode) ); assert( !Aig_ObjIsConst1(pNode) );
Aig_ManIncrementTravId( p ); Aig_ManIncrementTravId( p );
Vec_PtrForEachEntry( vImplics, pTemp, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vImplics, pTemp, i )
{ {
Aig_ObjSetTravIdCurrent( p, Aig_Regular(pTemp) ); Aig_ObjSetTravIdCurrent( p, Aig_Regular(pTemp) );
Aig_Regular(pTemp)->pData = Aig_NotCond( Aig_ManConst1(p), Aig_IsComplement(pTemp) ); Aig_Regular(pTemp)->pData = Aig_NotCond( Aig_ManConst1(p), Aig_IsComplement(pTemp) );
@ -267,6 +271,446 @@ void Aig_ManFactorAlgebraicTest( Aig_Man_t * p )
*/ */
} }
/**Function*************************************************************
Synopsis [Determines what support variables can be cofactored.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Aig_SuppMinPerform( Aig_Man_t * p, Vec_Ptr_t * vOrGate, Vec_Ptr_t * vNodes, Vec_Ptr_t * vSupp )
{
Aig_Obj_t * pObj;
Vec_Ptr_t * vTrSupp, * vTrNode, * vCofs;
unsigned * uFunc, * uCare, * uFunc0, * uFunc1, * uCof;
int i, nWords = Aig_TruthWordNum( Vec_PtrSize(vSupp) );
// assign support nodes
vTrSupp = Vec_PtrAllocTruthTables( Vec_PtrSize(vSupp) );
Vec_PtrForEachEntry( Aig_Obj_t *, vSupp, pObj, i )
{
printf( "%d %d\n", Aig_ObjId(pObj), i );
pObj->pData = Vec_PtrEntry( vTrSupp, i );
}
// compute internal nodes
vTrNode = Vec_PtrAllocSimInfo( Vec_PtrSize(vNodes) + 5, nWords );
Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
{
pObj->pData = uFunc = (unsigned *)Vec_PtrEntry( vTrNode, i );
uFunc0 = (unsigned *)Aig_ObjFanin0(pObj)->pData;
uFunc1 = (unsigned *)Aig_ObjFanin1(pObj)->pData;
Kit_TruthAndPhase( uFunc, uFunc0, uFunc1, Vec_PtrSize(vSupp), Aig_ObjFaninC0(pObj), Aig_ObjFaninC1(pObj) );
}
// uFunc contains the result of computation
// compute care set
uCare = (unsigned *)Vec_PtrEntry( vTrNode, Vec_PtrSize(vNodes) );
Kit_TruthClear( uCare, Vec_PtrSize(vSupp) );
Vec_PtrForEachEntry( Aig_Obj_t *, vOrGate, pObj, i )
{
printf( "%d %d %d - or gate\n", Aig_ObjId(Aig_Regular(pObj)), Aig_IsComplement(pObj), i );
Kit_TruthOrPhase( uCare, uCare, (unsigned *)Aig_Regular(pObj)->pData, Vec_PtrSize(vSupp), 0, Aig_IsComplement(pObj) );
}
// try cofactoring each variable in both polarities
vCofs = Vec_PtrAlloc( 10 );
uCof = (unsigned *)Vec_PtrEntry( vTrNode, Vec_PtrSize(vNodes)+1 );
Vec_PtrForEachEntry( Aig_Obj_t *, vSupp, pObj, i )
{
// consider negative cofactor
Kit_TruthCofactor0New( uCof, uFunc, Vec_PtrSize(vSupp), i );
if ( Kit_TruthIsEqualWithCare( uFunc, uCof, uCare, Vec_PtrSize(vSupp) ) )
{
Vec_PtrPush( vCofs, Aig_Not(pObj) );
Kit_TruthCopy( uFunc, uCof, Vec_PtrSize(vSupp) );
Kit_TruthCofactor0( uCare, Vec_PtrSize(vSupp), i );
continue;
}
// consider positive cofactor
Kit_TruthCofactor1New( uCof, uFunc, Vec_PtrSize(vSupp), i );
if ( Kit_TruthIsEqualWithCare( uFunc, uCof, uCare, Vec_PtrSize(vSupp) ) )
{
Vec_PtrPush( vCofs, pObj );
Kit_TruthCopy( uFunc, uCof, Vec_PtrSize(vSupp) );
Kit_TruthCofactor1( uCare, Vec_PtrSize(vSupp), i );
}
}
Vec_PtrFree( vTrNode );
Vec_PtrFree( vTrSupp );
return vCofs;
}
/**Function*************************************************************
Synopsis [Returns the new node after cofactoring.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_SuppMinReconstruct( Aig_Man_t * p, Vec_Ptr_t * vCofs, Vec_Ptr_t * vNodes, Vec_Ptr_t * vSupp )
{
Aig_Obj_t * pObj;
int i;
// set the value of the support variables
Vec_PtrForEachEntry( Aig_Obj_t *, vSupp, pObj, i )
assert( !Aig_IsComplement(pObj) );
Vec_PtrForEachEntry( Aig_Obj_t *, vSupp, pObj, i )
pObj->pData = pObj;
// set the value of the cofactoring variables
Vec_PtrForEachEntry( Aig_Obj_t *, vCofs, pObj, i )
Aig_Regular(pObj)->pData = Aig_NotCond( Aig_ManConst1(p), Aig_IsComplement(pObj) );
// reconstruct the node
Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
pObj->pData = Aig_And( p, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
return (Aig_Obj_t *)pObj->pData;
}
/**Function*************************************************************
Synopsis [Returns 1 if all nodes of vOrGate are in vSupp.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Aig_SuppMinGateIsInSupport( Aig_Man_t * p, Vec_Ptr_t * vOrGate, Vec_Ptr_t * vSupp )
{
Aig_Obj_t * pObj;
int i;
Aig_ManIncrementTravId( p );
Vec_PtrForEachEntry( Aig_Obj_t *, vSupp, pObj, i )
Aig_ObjSetTravIdCurrent( p, pObj );
Vec_PtrForEachEntry( Aig_Obj_t *, vOrGate, pObj, i )
if ( !Aig_ObjIsTravIdCurrent( p, Aig_Regular(pObj) ) )
return 0;
return 1;
}
/**Function*************************************************************
Synopsis [Collects fanins of the marked nodes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Aig_SuppMinCollectSupport( Aig_Man_t * p, Vec_Ptr_t * vNodes )
{
Vec_Ptr_t * vSupp;
Aig_Obj_t * pObj, * pFanin;
int i;
vSupp = Vec_PtrAlloc( 4 );
Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
{
assert( Aig_ObjIsTravIdCurrent(p, pObj) );
assert( Aig_ObjIsNode(pObj) );
pFanin = Aig_ObjFanin0( pObj );
if ( !Aig_ObjIsTravIdCurrent(p, pFanin) )
{
Aig_ObjSetTravIdCurrent( p, pFanin );
Vec_PtrPush( vSupp, pFanin );
}
pFanin = Aig_ObjFanin1( pObj );
if ( !Aig_ObjIsTravIdCurrent(p, pFanin) )
{
Aig_ObjSetTravIdCurrent( p, pFanin );
Vec_PtrPush( vSupp, pFanin );
}
}
return vSupp;
}
/**Function*************************************************************
Synopsis [Marks the nodes in the cone with current trav ID.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_SuppMinCollectCone_rec( Aig_Man_t * p, Aig_Obj_t * pObj, Vec_Ptr_t * vNodes )
{
if ( Aig_ObjIsTravIdCurrent( p, pObj ) ) // visited
return;
if ( !Aig_ObjIsTravIdPrevious( p, pObj ) ) // not visited, but outside
return;
assert( Aig_ObjIsTravIdPrevious(p, pObj) ); // not visited, inside
assert( Aig_ObjIsNode(pObj) );
Aig_ObjSetTravIdCurrent( p, pObj );
Aig_SuppMinCollectCone_rec( p, Aig_ObjFanin0(pObj), vNodes );
Aig_SuppMinCollectCone_rec( p, Aig_ObjFanin1(pObj), vNodes );
Vec_PtrPush( vNodes, pObj );
}
/**Function*************************************************************
Synopsis [Collects nodes with the current trav ID rooted in the node.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Aig_SuppMinCollectCone( Aig_Man_t * p, Aig_Obj_t * pRoot )
{
Vec_Ptr_t * vNodes;
assert( !Aig_IsComplement(pRoot) );
// assert( Aig_ObjIsTravIdCurrent( p, pRoot ) );
vNodes = Vec_PtrAlloc( 4 );
Aig_ManIncrementTravId( p );
Aig_SuppMinCollectCone_rec( p, Aig_Regular(pRoot), vNodes );
return vNodes;
}
/**Function*************************************************************
Synopsis [Marks the nodes in the cone with current trav ID.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Aig_SuppMinHighlightCone_rec( Aig_Man_t * p, Aig_Obj_t * pObj )
{
int RetValue;
if ( Aig_ObjIsTravIdCurrent( p, pObj ) ) // visited, marks there
return 1;
if ( Aig_ObjIsTravIdPrevious( p, pObj ) ) // visited, no marks there
return 0;
Aig_ObjSetTravIdPrevious( p, pObj );
if ( Aig_ObjIsPi(pObj) )
return 0;
RetValue = Aig_SuppMinHighlightCone_rec( p, Aig_ObjFanin0(pObj) ) |
Aig_SuppMinHighlightCone_rec( p, Aig_ObjFanin1(pObj) );
// printf( "%d %d\n", Aig_ObjId(pObj), RetValue );
if ( RetValue )
Aig_ObjSetTravIdCurrent( p, pObj );
return RetValue;
}
/**Function*************************************************************
Synopsis [Marks the nodes in the cone with current trav ID.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Aig_SuppMinHighlightCone( Aig_Man_t * p, Aig_Obj_t * pRoot, Vec_Ptr_t * vOrGate )
{
Aig_Obj_t * pLeaf;
int i, RetValue;
assert( !Aig_IsComplement(pRoot) );
Aig_ManIncrementTravId( p );
Aig_ManIncrementTravId( p );
Vec_PtrForEachEntry( Aig_Obj_t *, vOrGate, pLeaf, i )
Aig_ObjSetTravIdCurrent( p, Aig_Regular(pLeaf) );
RetValue = Aig_SuppMinHighlightCone_rec( p, pRoot );
Vec_PtrForEachEntry( Aig_Obj_t *, vOrGate, pLeaf, i )
Aig_ObjSetTravIdPrevious( p, Aig_Regular(pLeaf) );
return RetValue;
}
/**Function*************************************************************
Synopsis [Collects the supergate.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_SuppMinCollectSuper_rec( Aig_Obj_t * pObj, Vec_Ptr_t * vSuper )
{
// if the new node is complemented or a PI, another gate begins
if ( Aig_IsComplement(pObj) || Aig_ObjIsPi(pObj) ) // || (Aig_ObjRefs(pObj) > 1) )
{
Vec_PtrPushUnique( vSuper, Aig_Not(pObj) );
return;
}
// go through the branches
Aig_SuppMinCollectSuper_rec( Aig_ObjChild0(pObj), vSuper );
Aig_SuppMinCollectSuper_rec( Aig_ObjChild1(pObj), vSuper );
}
/**Function*************************************************************
Synopsis [Collects the supergate.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Aig_SuppMinCollectSuper( Aig_Obj_t * pObj )
{
Vec_Ptr_t * vSuper;
assert( !Aig_IsComplement(pObj) );
assert( !Aig_ObjIsPi(pObj) );
vSuper = Vec_PtrAlloc( 4 );
Aig_SuppMinCollectSuper_rec( Aig_ObjChild0(pObj), vSuper );
Aig_SuppMinCollectSuper_rec( Aig_ObjChild1(pObj), vSuper );
return vSuper;
}
/**Function*************************************************************
Synopsis [Returns the result of support minimization.]
Description [Returns internal AIG node that is equal to pFunc under
assignment pCond == 1, or NULL if there is no such node. status is
-1 if condition is not OR;
-2 if cone is too large or no cone;
-3 if no support reduction is possible.]
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_ManSupportMinimization( Aig_Man_t * p, Aig_Obj_t * pCond, Aig_Obj_t * pFunc, int * pStatus )
{
int nSuppMax = 16;
Vec_Ptr_t * vOrGate, * vNodes, * vSupp, * vCofs;
Aig_Obj_t * pResult;
int RetValue;
*pStatus = 0;
// if pCond is not OR
if ( !Aig_IsComplement(pCond) || Aig_ObjIsPi(Aig_Regular(pCond)) || Aig_ObjIsConst1(Aig_Regular(pCond)) )
{
*pStatus = -1;
return NULL;
}
// if pFunc is not a node
if ( !Aig_ObjIsNode(Aig_Regular(pFunc)) )
{
*pStatus = -2;
return NULL;
}
// collect the multi-input OR gate rooted in the condition
vOrGate = Aig_SuppMinCollectSuper( Aig_Regular(pCond) );
if ( Vec_PtrSize(vOrGate) > nSuppMax )
{
Vec_PtrFree( vOrGate );
*pStatus = -2;
return NULL;
}
// highlight the cone limited by these gates
RetValue = Aig_SuppMinHighlightCone( p, Aig_Regular(pFunc), vOrGate );
if ( RetValue == 0 ) // no overlap
{
Vec_PtrFree( vOrGate );
*pStatus = -2;
return NULL;
}
// collect the cone rooted in pFunc limited by vOrGate
vNodes = Aig_SuppMinCollectCone( p, Aig_Regular(pFunc) );
// collect the support nodes reachable from the cone
vSupp = Aig_SuppMinCollectSupport( p, vNodes );
if ( Vec_PtrSize(vSupp) > nSuppMax )
{
Vec_PtrFree( vOrGate );
Vec_PtrFree( vNodes );
Vec_PtrFree( vSupp );
*pStatus = -2;
return NULL;
}
// check if all nodes belonging to OR gate are included in the support
// (if this is not the case, don't-care minimization is not possible)
if ( !Aig_SuppMinGateIsInSupport( p, vOrGate, vSupp ) )
{
Vec_PtrFree( vOrGate );
Vec_PtrFree( vNodes );
Vec_PtrFree( vSupp );
*pStatus = -3;
return NULL;
}
// create truth tables of all nodes and find the maximal number
// of support varialbles that can be replaced by constants
vCofs = Aig_SuppMinPerform( p, vOrGate, vNodes, vSupp );
if ( Vec_PtrSize(vCofs) == 0 )
{
Vec_PtrFree( vCofs );
Vec_PtrFree( vOrGate );
Vec_PtrFree( vNodes );
Vec_PtrFree( vSupp );
*pStatus = -3;
return NULL;
}
// reconstruct the cone
pResult = Aig_SuppMinReconstruct( p, vCofs, vNodes, vSupp );
pResult = Aig_NotCond( pResult, Aig_IsComplement(pFunc) );
Vec_PtrFree( vCofs );
Vec_PtrFree( vOrGate );
Vec_PtrFree( vNodes );
Vec_PtrFree( vSupp );
return pResult;
}
/**Function*************************************************************
Synopsis [Testing procedure.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_ManSupportMinimizationTest()
{
Aig_Man_t * p;
Aig_Obj_t * pFunc, * pCond, * pRes;
int i, Status;
p = Aig_ManStart( 100 );
for ( i = 0; i < 5; i++ )
Aig_IthVar(p,i);
pFunc = Aig_Mux( p, Aig_IthVar(p,3), Aig_IthVar(p,1), Aig_IthVar(p,0) );
pFunc = Aig_Mux( p, Aig_IthVar(p,4), Aig_IthVar(p,2), pFunc );
pCond = Aig_Or( p, Aig_IthVar(p,3), Aig_IthVar(p,4) );
pRes = Aig_ManSupportMinimization( p, pCond, pFunc, &Status );
assert( Status == 0 );
Aig_ObjPrint( p, Aig_Regular(pRes) ); printf( "\n" );
Aig_ObjPrint( p, Aig_ObjFanin0(Aig_Regular(pRes)) ); printf( "\n" );
Aig_ObjPrint( p, Aig_ObjFanin1(Aig_Regular(pRes)) ); printf( "\n" );
Aig_ManStop( p );
}
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// END OF FILE /// /// END OF FILE ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

5
src/aig/aig/aigFanout.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
// 0: first iFan // 0: first iFan
// 1: prev iFan0 // 1: prev iFan0
// 2: prev iFan1 // 2: prev iFan1
@ -187,3 +190,5 @@ void Aig_ObjRemoveFanout( Aig_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pFanout )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

5
src/aig/aig/aigFrames.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -133,3 +136,5 @@ Aig_Man_t * Aig_ManFrames( Aig_Man_t * pAig, int nFs, int fInit, int fOuts, int
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

9
src/aig/aig/aigInter.c
View File

@ -22,6 +22,9 @@
#include "cnf.h" #include "cnf.h"
#include "satStore.h" #include "satStore.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -268,7 +271,7 @@ timeSat += clock() - clk;
// create the resulting manager // create the resulting manager
clk = clock(); clk = clock();
pManInter = Inta_ManAlloc(); pManInter = Inta_ManAlloc();
pRes = Inta_ManInterpolate( pManInter, pSatCnf, vVarsAB, fVerbose ); pRes = (Aig_Man_t *)Inta_ManInterpolate( pManInter, (Sto_Man_t *)pSatCnf, vVarsAB, fVerbose );
Inta_ManFree( pManInter ); Inta_ManFree( pManInter );
timeInt += clock() - clk; timeInt += clock() - clk;
/* /*
@ -283,7 +286,7 @@ timeInt += clock() - clk;
} }
*/ */
Vec_IntFree( vVarsAB ); Vec_IntFree( vVarsAB );
Sto_ManFree( pSatCnf ); Sto_ManFree( (Sto_Man_t *)pSatCnf );
// Ioa_WriteAiger( pRes, "inter2.aig", 0, 0 ); // Ioa_WriteAiger( pRes, "inter2.aig", 0, 0 );
return pRes; return pRes;
@ -294,3 +297,5 @@ timeInt += clock() - clk;
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

97
src/aig/aig/aigMan.c
View File

@ -21,6 +21,9 @@
#include "aig.h" #include "aig.h"
#include "tim.h" #include "tim.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -118,14 +121,14 @@ Aig_Obj_t * Aig_ManDup_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t * pObj )
{ {
Aig_Obj_t * pObjNew; Aig_Obj_t * pObjNew;
if ( pObj->pData ) if ( pObj->pData )
return pObj->pData; return (Aig_Obj_t *)pObj->pData;
Aig_ManDup_rec( pNew, p, Aig_ObjFanin0(pObj) ); Aig_ManDup_rec( pNew, p, Aig_ObjFanin0(pObj) );
if ( Aig_ObjIsBuf(pObj) ) if ( Aig_ObjIsBuf(pObj) )
return pObj->pData = Aig_ObjChild0Copy(pObj); return (Aig_Obj_t *)(pObj->pData = Aig_ObjChild0Copy(pObj));
Aig_ManDup_rec( pNew, p, Aig_ObjFanin1(pObj) ); Aig_ManDup_rec( pNew, p, Aig_ObjFanin1(pObj) );
pObjNew = Aig_Oper( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj), Aig_ObjType(pObj) ); pObjNew = Aig_Oper( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj), Aig_ObjType(pObj) );
Aig_Regular(pObjNew)->pHaig = pObj->pHaig; Aig_Regular(pObjNew)->pHaig = pObj->pHaig;
return pObj->pData = pObjNew; return (Aig_Obj_t *)(pObj->pData = pObjNew);
} }
/**Function************************************************************* /**Function*************************************************************
@ -157,7 +160,7 @@ Aig_Man_t * Aig_ManExtractMiter( Aig_Man_t * p, Aig_Obj_t * pNode1, Aig_Obj_t *
Aig_ManDup_rec( pNew, p, pNode1 ); Aig_ManDup_rec( pNew, p, pNode1 );
Aig_ManDup_rec( pNew, p, pNode2 ); Aig_ManDup_rec( pNew, p, pNode2 );
// construct the EXOR // construct the EXOR
pObj = Aig_Exor( pNew, pNode1->pData, pNode2->pData ); pObj = Aig_Exor( pNew, (Aig_Obj_t *)pNode1->pData, (Aig_Obj_t *)pNode2->pData );
pObj = Aig_NotCond( pObj, Aig_Regular(pObj)->fPhase ^ Aig_IsComplement(pObj) ); pObj = Aig_NotCond( pObj, Aig_Regular(pObj)->fPhase ^ Aig_IsComplement(pObj) );
// add the PO // add the PO
Aig_ObjCreatePo( pNew, pObj ); Aig_ObjCreatePo( pNew, pObj );
@ -183,35 +186,33 @@ void Aig_ManStop( Aig_Man_t * p )
{ {
Aig_Obj_t * pObj; Aig_Obj_t * pObj;
int i; int i;
if ( p->vMapped )
Vec_PtrFree( p->vMapped );
// print time
if ( p->time1 ) { ABC_PRT( "time1", p->time1 ); } if ( p->time1 ) { ABC_PRT( "time1", p->time1 ); }
if ( p->time2 ) { ABC_PRT( "time2", p->time2 ); } if ( p->time2 ) { ABC_PRT( "time2", p->time2 ); }
// delete timing
if ( p->pManTime )
Tim_ManStop( p->pManTime );
// delete fanout
if ( p->pFanData )
Aig_ManFanoutStop( p );
// make sure the nodes have clean marks // make sure the nodes have clean marks
Aig_ManForEachObj( p, pObj, i ) Aig_ManForEachObj( p, pObj, i )
assert( !pObj->fMarkA && !pObj->fMarkB ); assert( !pObj->fMarkA && !pObj->fMarkB );
Tim_ManStopP( (Tim_Man_t **)&p->pManTime );
if ( p->pFanData )
Aig_ManFanoutStop( p );
if ( p->pManExdc )
Aig_ManStop( p->pManExdc );
// Aig_TableProfile( p ); // Aig_TableProfile( p );
Aig_MmFixedStop( p->pMemObjs, 0 ); Aig_MmFixedStop( p->pMemObjs, 0 );
if ( p->vPis ) Vec_PtrFree( p->vPis ); Vec_PtrFreeP( &p->vPis );
if ( p->vPos ) Vec_PtrFree( p->vPos ); Vec_PtrFreeP( &p->vPos );
if ( p->vObjs ) Vec_PtrFree( p->vObjs ); Vec_PtrFreeP( &p->vObjs );
if ( p->vBufs ) Vec_PtrFree( p->vBufs ); Vec_PtrFreeP( &p->vBufs );
if ( p->vLevelR ) Vec_IntFree( p->vLevelR ); Vec_IntFreeP( &p->vLevelR );
if ( p->vLevels ) Vec_VecFree( p->vLevels ); Vec_VecFreeP( &p->vLevels );
if ( p->vFlopNums) Vec_IntFree( p->vFlopNums ); Vec_IntFreeP( &p->vFlopNums );
if ( p->vFlopReprs) Vec_IntFree( p->vFlopReprs ); Vec_IntFreeP( &p->vFlopReprs );
if ( p->pManExdc ) Aig_ManStop( p->pManExdc ); Vec_VecFreeP( (Vec_Vec_t **)&p->vOnehots );
if ( p->vOnehots ) Vec_VecFree( (Vec_Vec_t *)p->vOnehots ); Vec_VecFreeP( &p->vClockDoms );
if ( p->vClockDoms) Vec_VecFree( p->vClockDoms ); Vec_IntFreeP( &p->vProbs );
if ( p->vProbs ) Vec_IntFree( p->vProbs ); Vec_IntFreeP( &p->vCiNumsOrig );
if ( p->vCiNumsOrig)Vec_IntFree( p->vCiNumsOrig ); Vec_PtrFreeP( &p->vMapped );
if ( p->pSeqModelVec )
Vec_PtrFreeFree( p->pSeqModelVec );
ABC_FREE( p->pFastSim ); ABC_FREE( p->pFastSim );
ABC_FREE( p->pData ); ABC_FREE( p->pData );
ABC_FREE( p->pSeqModel ); ABC_FREE( p->pSeqModel );
@ -224,6 +225,25 @@ void Aig_ManStop( Aig_Man_t * p )
ABC_FREE( p ); ABC_FREE( p );
} }
/**Function*************************************************************
Synopsis [Stops the AIG manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_ManStopP( Aig_Man_t ** p )
{
if ( *p == NULL )
return;
Aig_ManStop( *p );
*p = NULL;
}
/**Function************************************************************* /**Function*************************************************************
Synopsis [Removes combinational logic that does not feed into POs.] Synopsis [Removes combinational logic that does not feed into POs.]
@ -246,7 +266,7 @@ int Aig_ManCleanup( Aig_Man_t * p )
if ( Aig_ObjIsNode(pNode) && Aig_ObjRefs(pNode) == 0 ) if ( Aig_ObjIsNode(pNode) && Aig_ObjRefs(pNode) == 0 )
Vec_PtrPush( vObjs, pNode ); Vec_PtrPush( vObjs, pNode );
// recursively remove dangling nodes // recursively remove dangling nodes
Vec_PtrForEachEntry( vObjs, pNode, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vObjs, pNode, i )
Aig_ObjDelete_rec( p, pNode, 1 ); Aig_ObjDelete_rec( p, pNode, 1 );
Vec_PtrFree( vObjs ); Vec_PtrFree( vObjs );
return nNodesOld - Aig_ManNodeNum(p); return nNodesOld - Aig_ManNodeNum(p);
@ -288,7 +308,7 @@ int Aig_ManPiCleanup( Aig_Man_t * p )
{ {
Aig_Obj_t * pObj; Aig_Obj_t * pObj;
int i, k = 0, nPisOld = Aig_ManPiNum(p); int i, k = 0, nPisOld = Aig_ManPiNum(p);
Vec_PtrForEachEntry( p->vPis, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, p->vPis, pObj, i )
{ {
if ( i >= Aig_ManPiNum(p) - Aig_ManRegNum(p) ) if ( i >= Aig_ManPiNum(p) - Aig_ManRegNum(p) )
Vec_PtrWriteEntry( p->vPis, k++, pObj ); Vec_PtrWriteEntry( p->vPis, k++, pObj );
@ -319,7 +339,7 @@ int Aig_ManPoCleanup( Aig_Man_t * p )
{ {
Aig_Obj_t * pObj; Aig_Obj_t * pObj;
int i, k = 0, nPosOld = Aig_ManPoNum(p); int i, k = 0, nPosOld = Aig_ManPoNum(p);
Vec_PtrForEachEntry( p->vPos, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, p->vPos, pObj, i )
{ {
if ( i >= Aig_ManPoNum(p) - Aig_ManRegNum(p) ) if ( i >= Aig_ManPoNum(p) - Aig_ManRegNum(p) )
Vec_PtrWriteEntry( p->vPos, k++, pObj ); Vec_PtrWriteEntry( p->vPos, k++, pObj );
@ -453,9 +473,28 @@ void Aig_ManFlipFirstPo( Aig_Man_t * p )
Aig_ObjChild0Flip( Aig_ManPo(p, 0) ); Aig_ObjChild0Flip( Aig_ManPo(p, 0) );
} }
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void * Aig_ManReleaseData( Aig_Man_t * p )
{
void * pD = p->pData;
p->pData = NULL;
return pD;
}
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// END OF FILE /// /// END OF FILE ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

21
src/aig/aig/aigMem.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -31,7 +34,7 @@ struct Aig_MmFixed_t_
int nEntriesAlloc; // the total number of entries allocated int nEntriesAlloc; // the total number of entries allocated
int nEntriesUsed; // the number of entries in use int nEntriesUsed; // the number of entries in use
int nEntriesMax; // the max number of entries in use int nEntriesMax; // the max number of entries in use
char * pEntriesFree; // the linked list of ABC_FREE entries char * pEntriesFree; // the linked list of free entries
// this is where the memory is stored // this is where the memory is stored
int nChunkSize; // the size of one chunk int nChunkSize; // the size of one chunk
@ -48,8 +51,8 @@ struct Aig_MmFlex_t_
{ {
// information about individual entries // information about individual entries
int nEntriesUsed; // the number of entries allocated int nEntriesUsed; // the number of entries allocated
char * pCurrent; // the current pointer to ABC_FREE memory char * pCurrent; // the current pointer to free memory
char * pEnd; // the first entry outside the ABC_FREE memory char * pEnd; // the first entry outside the free memory
// this is where the memory is stored // this is where the memory is stored
int nChunkSize; // the size of one chunk int nChunkSize; // the size of one chunk
@ -160,7 +163,7 @@ char * Aig_MmFixedEntryFetch( Aig_MmFixed_t * p )
char * pTemp; char * pTemp;
int i; int i;
// check if there are still ABC_FREE entries // check if there are still free entries
if ( p->nEntriesUsed == p->nEntriesAlloc ) if ( p->nEntriesUsed == p->nEntriesAlloc )
{ // need to allocate more entries { // need to allocate more entries
assert( p->pEntriesFree == NULL ); assert( p->pEntriesFree == NULL );
@ -189,7 +192,7 @@ char * Aig_MmFixedEntryFetch( Aig_MmFixed_t * p )
p->nEntriesUsed++; p->nEntriesUsed++;
if ( p->nEntriesMax < p->nEntriesUsed ) if ( p->nEntriesMax < p->nEntriesUsed )
p->nEntriesMax = p->nEntriesUsed; p->nEntriesMax = p->nEntriesUsed;
// return the first entry in the ABC_FREE entry list // return the first entry in the free entry list
pTemp = p->pEntriesFree; pTemp = p->pEntriesFree;
p->pEntriesFree = *((char **)pTemp); p->pEntriesFree = *((char **)pTemp);
return pTemp; return pTemp;
@ -210,7 +213,7 @@ void Aig_MmFixedEntryRecycle( Aig_MmFixed_t * p, char * pEntry )
{ {
// decrement the counter of used entries // decrement the counter of used entries
p->nEntriesUsed--; p->nEntriesUsed--;
// add the entry to the linked list of ABC_FREE entries // add the entry to the linked list of free entries
*((char **)pEntry) = p->pEntriesFree; *((char **)pEntry) = p->pEntriesFree;
p->pEntriesFree = pEntry; p->pEntriesFree = pEntry;
} }
@ -245,7 +248,7 @@ void Aig_MmFixedRestart( Aig_MmFixed_t * p )
} }
// set the last link // set the last link
*((char **)pTemp) = NULL; *((char **)pTemp) = NULL;
// set the ABC_FREE entry list // set the free entry list
p->pEntriesFree = p->pChunks[0]; p->pEntriesFree = p->pChunks[0];
// set the correct statistics // set the correct statistics
p->nMemoryAlloc = p->nEntrySize * p->nChunkSize; p->nMemoryAlloc = p->nEntrySize * p->nChunkSize;
@ -363,7 +366,7 @@ void Aig_MmFlexStop( Aig_MmFlex_t * p, int fVerbose )
char * Aig_MmFlexEntryFetch( Aig_MmFlex_t * p, int nBytes ) char * Aig_MmFlexEntryFetch( Aig_MmFlex_t * p, int nBytes )
{ {
char * pTemp; char * pTemp;
// check if there are still ABC_FREE entries // check if there are still free entries
if ( p->pCurrent == NULL || p->pCurrent + nBytes > p->pEnd ) if ( p->pCurrent == NULL || p->pCurrent + nBytes > p->pEnd )
{ // need to allocate more entries { // need to allocate more entries
if ( p->nChunks == p->nChunksAlloc ) if ( p->nChunks == p->nChunksAlloc )
@ -591,3 +594,5 @@ int Aig_MmStepReadMemUsage( Aig_MmStep_t * p )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// END OF FILE /// /// END OF FILE ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

13
src/aig/aig/aigMffc.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -237,11 +240,11 @@ int Aig_NodeMffcLabelCut( Aig_Man_t * p, Aig_Obj_t * pNode, Vec_Ptr_t * vLeaves
assert( !Aig_IsComplement(pNode) ); assert( !Aig_IsComplement(pNode) );
assert( Aig_ObjIsNode(pNode) ); assert( Aig_ObjIsNode(pNode) );
Aig_ManIncrementTravId( p ); Aig_ManIncrementTravId( p );
Vec_PtrForEachEntry( vLeaves, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vLeaves, pObj, i )
pObj->nRefs++; pObj->nRefs++;
ConeSize1 = Aig_NodeDeref_rec( pNode, 0, NULL, NULL ); ConeSize1 = Aig_NodeDeref_rec( pNode, 0, NULL, NULL );
ConeSize2 = Aig_NodeRefLabel_rec( p, pNode, 0 ); ConeSize2 = Aig_NodeRefLabel_rec( p, pNode, 0 );
Vec_PtrForEachEntry( vLeaves, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vLeaves, pObj, i )
pObj->nRefs--; pObj->nRefs--;
assert( ConeSize1 == ConeSize2 ); assert( ConeSize1 == ConeSize2 );
assert( ConeSize1 > 0 ); assert( ConeSize1 > 0 );
@ -265,7 +268,7 @@ int Aig_NodeMffcExtendCut( Aig_Man_t * p, Aig_Obj_t * pNode, Vec_Ptr_t * vLeaves
int i, LevelMax, ConeSize1, ConeSize2, ConeCur1, ConeCur2, ConeBest; int i, LevelMax, ConeSize1, ConeSize2, ConeCur1, ConeCur2, ConeBest;
// dereference the current cut // dereference the current cut
LevelMax = 0; LevelMax = 0;
Vec_PtrForEachEntry( vLeaves, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vLeaves, pObj, i )
LevelMax = ABC_MAX( LevelMax, (int)pObj->Level ); LevelMax = ABC_MAX( LevelMax, (int)pObj->Level );
if ( LevelMax == 0 ) if ( LevelMax == 0 )
return 0; return 0;
@ -274,7 +277,7 @@ int Aig_NodeMffcExtendCut( Aig_Man_t * p, Aig_Obj_t * pNode, Vec_Ptr_t * vLeaves
// try expanding each node in the boundary // try expanding each node in the boundary
ConeBest = ABC_INFINITY; ConeBest = ABC_INFINITY;
pLeafBest = NULL; pLeafBest = NULL;
Vec_PtrForEachEntry( vLeaves, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vLeaves, pObj, i )
{ {
if ( (int)pObj->Level != LevelMax ) if ( (int)pObj->Level != LevelMax )
continue; continue;
@ -309,3 +312,5 @@ int Aig_NodeMffcExtendCut( Aig_Man_t * p, Aig_Obj_t * pNode, Vec_Ptr_t * vLeaves
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

7
src/aig/aig/aigObj.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -441,7 +444,7 @@ int Aig_ManPropagateBuffers( Aig_Man_t * p, int fUpdateLevel )
for ( nSteps = 0; Vec_PtrSize(p->vBufs) > 0; nSteps++ ) for ( nSteps = 0; Vec_PtrSize(p->vBufs) > 0; nSteps++ )
{ {
// get the node with a buffer fanin // get the node with a buffer fanin
for ( pObj = Vec_PtrEntryLast(p->vBufs); Aig_ObjIsBuf(pObj); pObj = Aig_ObjFanout0(p, pObj) ); for ( pObj = (Aig_Obj_t *)Vec_PtrEntryLast(p->vBufs); Aig_ObjIsBuf(pObj); pObj = Aig_ObjFanout0(p, pObj) );
// replace this node by a node without buffer // replace this node by a node without buffer
Aig_NodeFixBufferFanins( p, pObj, fUpdateLevel ); Aig_NodeFixBufferFanins( p, pObj, fUpdateLevel );
// stop if a cycle occured // stop if a cycle occured
@ -549,3 +552,5 @@ void Aig_ObjReplace( Aig_Man_t * p, Aig_Obj_t * pObjOld, Aig_Obj_t * pObjNew, in
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

173
src/aig/aig/aigOper.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -258,6 +261,48 @@ Aig_Obj_t * Aig_Or( Aig_Man_t * p, Aig_Obj_t * p0, Aig_Obj_t * p1 )
return Aig_Not( Aig_And( p, Aig_Not(p0), Aig_Not(p1) ) ); return Aig_Not( Aig_And( p, Aig_Not(p0), Aig_Not(p1) ) );
} }
/**Function*************************************************************
Synopsis [Implements ITE operation.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_TableLookupInt( Aig_Man_t * p, Aig_Obj_t * p0, Aig_Obj_t * p1 )
{
if ( p0 == p1 )
return p0;
if ( p0 == Aig_ManConst0(p) || p1 == Aig_ManConst0(p) || p0 == Aig_Not(p1) )
return Aig_ManConst0(p);
if ( p0 == Aig_ManConst1(p) )
return p1;
if ( p1 == Aig_ManConst1(p) )
return p0;
if ( Aig_Regular(p0)->Id < Aig_Regular(p1)->Id )
return Aig_TableLookup( p, Aig_ObjCreateGhost(p, p0, p1, AIG_OBJ_AND) );
return Aig_TableLookup( p, Aig_ObjCreateGhost(p, p1, p0, AIG_OBJ_AND) );
}
/**Function*************************************************************
Synopsis [Implements ITE operation.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_Mux2( Aig_Man_t * p, Aig_Obj_t * pC, Aig_Obj_t * p1, Aig_Obj_t * p0 )
{
return Aig_Or( p, Aig_And(p, pC, p1), Aig_And(p, Aig_Not(pC), p0) );
}
/**Function************************************************************* /**Function*************************************************************
Synopsis [Implements ITE operation.] Synopsis [Implements ITE operation.]
@ -271,46 +316,50 @@ Aig_Obj_t * Aig_Or( Aig_Man_t * p, Aig_Obj_t * p0, Aig_Obj_t * p1 )
***********************************************************************/ ***********************************************************************/
Aig_Obj_t * Aig_Mux( Aig_Man_t * p, Aig_Obj_t * pC, Aig_Obj_t * p1, Aig_Obj_t * p0 ) Aig_Obj_t * Aig_Mux( Aig_Man_t * p, Aig_Obj_t * pC, Aig_Obj_t * p1, Aig_Obj_t * p0 )
{ {
/* int fUseMuxCanon = 0;
Aig_Obj_t * pTempA1, * pTempA2, * pTempB1, * pTempB2, * pTemp; Aig_Obj_t * pTempA1, * pTempA2, * pTempB1, * pTempB2, * pTemp;
int Count0, Count1; int Count0, Count1;
// consider trivial cases if ( !fUseMuxCanon )
if ( p0 == Aig_Not(p1) ) return Aig_Mux2( p, pC, p1, p0 );
if ( p0 == p1 )
return p0;
if ( p1 == Aig_Not(p0) )
return Aig_Exor( p, pC, p0 ); return Aig_Exor( p, pC, p0 );
// other cases can be added if ( pC == Aig_ManConst0(p) )
return p0;
if ( pC == Aig_ManConst1(p) )
return p1;
if ( p0 == Aig_ManConst0(p) )
return Aig_And( p, pC, p1 );
if ( p0 == Aig_ManConst1(p) )
return Aig_Or( p, Aig_Not(pC), p1 );
if ( p1 == Aig_ManConst0(p) )
return Aig_And( p, Aig_Not(pC), p0 );
if ( p1 == Aig_ManConst1(p) )
return Aig_Or( p, pC, p0 );
// implement the first MUX (F = C * x1 + C' * x0) // implement the first MUX (F = C * x1 + C' * x0)
pTempA1 = Aig_TableLookupInt( p, pC, p1 );
// check for constants here!!! pTempA2 = Aig_TableLookupInt( p, Aig_Not(pC), p0 );
pTempA1 = Aig_TableLookup( p, Aig_ObjCreateGhost(p, pC, p1, AIG_OBJ_AND) );
pTempA2 = Aig_TableLookup( p, Aig_ObjCreateGhost(p, Aig_Not(pC), p0, AIG_OBJ_AND) );
if ( pTempA1 && pTempA2 ) if ( pTempA1 && pTempA2 )
{ {
pTemp = Aig_TableLookup( p, Aig_ObjCreateGhost(p, Aig_Not(pTempA1), Aig_Not(pTempA2), AIG_OBJ_AND) ); pTemp = Aig_TableLookupInt( p, Aig_Not(pTempA1), Aig_Not(pTempA2) );
if ( pTemp ) return Aig_Not(pTemp); if ( pTemp ) return Aig_Not(pTemp);
} }
Count0 = (pTempA1 != NULL) + (pTempA2 != NULL); Count0 = (pTempA1 != NULL) + (pTempA2 != NULL);
// implement the second MUX (F' = C * x1' + C' * x0') // implement the second MUX (F' = C * x1' + C' * x0')
pTempB1 = Aig_TableLookup( p, Aig_ObjCreateGhost(p, pC, Aig_Not(p1), AIG_OBJ_AND) ); pTempB1 = Aig_TableLookupInt( p, pC, Aig_Not(p1) );
pTempB2 = Aig_TableLookup( p, Aig_ObjCreateGhost(p, Aig_Not(pC), Aig_Not(p0), AIG_OBJ_AND) ); pTempB2 = Aig_TableLookupInt( p, Aig_Not(pC), Aig_Not(p0) );
if ( pTempB1 && pTempB2 ) if ( pTempB1 && pTempB2 )
{ {
pTemp = Aig_TableLookup( p, Aig_ObjCreateGhost(p, Aig_Not(pTempB1), Aig_Not(pTempB2), AIG_OBJ_AND) ); pTemp = Aig_TableLookupInt( p, Aig_Not(pTempB1), Aig_Not(pTempB2) );
if ( pTemp ) return pTemp; if ( pTemp ) return pTemp;
} }
Count1 = (pTempB1 != NULL) + (pTempB2 != NULL); Count1 = (pTempB1 != NULL) + (pTempB2 != NULL);
// compare and decide which one to implement // compare and decide which one to implement
if ( Count0 >= Count1 ) if ( Count0 >= Count1 )
{
pTempA1 = pTempA1? pTempA1 : Aig_And(p, pC, p1);
pTempA2 = pTempA2? pTempA2 : Aig_And(p, Aig_Not(pC), p0);
return Aig_Or( p, pTempA1, pTempA2 );
}
pTempB1 = pTempB1? pTempB1 : Aig_And(p, pC, Aig_Not(p1));
pTempB2 = pTempB2? pTempB2 : Aig_And(p, Aig_Not(pC), Aig_Not(p0));
return Aig_Not( Aig_Or( p, pTempB1, pTempB2 ) );
*/
return Aig_Or( p, Aig_And(p, pC, p1), Aig_And(p, Aig_Not(pC), p0) ); return Aig_Or( p, Aig_And(p, pC, p1), Aig_And(p, Aig_Not(pC), p0) );
return Aig_Not( Aig_Or( p, Aig_And(p, pC, Aig_Not(p1)), Aig_And(p, Aig_Not(pC), Aig_Not(p0)) ) );
// return Aig_Or( p, Aig_And(p, pC, p1), Aig_And(p, Aig_Not(pC), p0) );
} }
/**Function************************************************************* /**Function*************************************************************
@ -385,7 +434,7 @@ Aig_Obj_t * Aig_Miter( Aig_Man_t * p, Vec_Ptr_t * vPairs )
assert( vPairs->nSize > 0 ); assert( vPairs->nSize > 0 );
assert( vPairs->nSize % 2 == 0 ); assert( vPairs->nSize % 2 == 0 );
for ( i = 0; i < vPairs->nSize; i += 2 ) for ( i = 0; i < vPairs->nSize; i += 2 )
vPairs->pArray[i/2] = Aig_Not( Aig_Exor( p, vPairs->pArray[i], vPairs->pArray[i+1] ) ); vPairs->pArray[i/2] = Aig_Not( Aig_Exor( p, (Aig_Obj_t *)vPairs->pArray[i], (Aig_Obj_t *)vPairs->pArray[i+1] ) );
vPairs->nSize = vPairs->nSize/2; vPairs->nSize = vPairs->nSize/2;
return Aig_Not( Aig_Multi_rec( p, (Aig_Obj_t **)vPairs->pArray, vPairs->nSize, AIG_OBJ_AND ) ); return Aig_Not( Aig_Multi_rec( p, (Aig_Obj_t **)vPairs->pArray, vPairs->nSize, AIG_OBJ_AND ) );
} }
@ -407,7 +456,7 @@ Aig_Obj_t * Aig_MiterTwo( Aig_Man_t * p, Vec_Ptr_t * vNodes1, Vec_Ptr_t * vNodes
assert( vNodes1->nSize > 0 && vNodes1->nSize > 0 ); assert( vNodes1->nSize > 0 && vNodes1->nSize > 0 );
assert( vNodes1->nSize == vNodes2->nSize ); assert( vNodes1->nSize == vNodes2->nSize );
for ( i = 0; i < vNodes1->nSize; i++ ) for ( i = 0; i < vNodes1->nSize; i++ )
vNodes1->pArray[i] = Aig_Not( Aig_Exor( p, vNodes1->pArray[i], vNodes2->pArray[i] ) ); vNodes1->pArray[i] = Aig_Not( Aig_Exor( p, (Aig_Obj_t *)vNodes1->pArray[i], (Aig_Obj_t *)vNodes2->pArray[i] ) );
return Aig_Not( Aig_Multi_rec( p, (Aig_Obj_t **)vNodes1->pArray, vNodes1->nSize, AIG_OBJ_AND ) ); return Aig_Not( Aig_Multi_rec( p, (Aig_Obj_t **)vNodes1->pArray, vNodes1->nSize, AIG_OBJ_AND ) );
} }
@ -474,8 +523,84 @@ Aig_Obj_t * Aig_CreateExor( Aig_Man_t * p, int nVars )
return pFunc; return pFunc;
} }
/**Function*************************************************************
Synopsis [Implements ITE operation.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_MuxTest()
{
Vec_Ptr_t * vNodes;
Aig_Man_t * p;
Aig_Obj_t * pObj, * pFanin0, * pFanin1, * pCtrl;
int nNodes = 2000;
int i,nPIs = 20;
// srand( time(NULL) );
srand( 321 );
vNodes = Vec_PtrAlloc( 100 );
// create a bunch of random MUXes
p = Aig_ManStart( 10000 );
for ( i = 0; i < nPIs; i++ )
Aig_IthVar(p,i);
for ( i = 0; i < nNodes; i++ )
{
if ( rand() % 10 == 0 )
pCtrl = Aig_ManConst0(p);
else if ( rand() % 10 == 0 )
pCtrl = Aig_ManConst1(p);
else if ( rand() % 3 == 0 || i < nPIs )
pCtrl = Aig_IthVar( p, rand() % nPIs );
else
pCtrl = (Aig_Obj_t *)Vec_PtrEntry(vNodes, rand() % i);
if ( rand() % 2 == 0 )
pCtrl = Aig_Not( pCtrl );
if ( rand() % 10 == 0 )
pFanin1 = Aig_ManConst0(p);
else if ( rand() % 10 == 0 )
pFanin1 = Aig_ManConst1(p);
else if ( rand() % 3 == 0 || i < nPIs )
pFanin1 = Aig_IthVar( p, rand() % nPIs );
else
pFanin1 = (Aig_Obj_t *)Vec_PtrEntry(vNodes, rand() % i);
if ( rand() % 2 == 0 )
pFanin1 = Aig_Not( pFanin1 );
if ( rand() % 10 == 0 )
pFanin0 = Aig_ManConst0(p);
else if ( rand() % 10 == 0 )
pFanin0 = Aig_ManConst1(p);
else if ( rand() % 3 == 0 || i < nPIs )
pFanin0 = Aig_IthVar( p, rand() % nPIs );
else
pFanin0 = (Aig_Obj_t *)Vec_PtrEntry(vNodes, rand() % i);
if ( rand() % 2 == 0 )
pFanin0 = Aig_Not( pFanin0 );
pObj = Aig_Mux( p, pCtrl, pFanin1, pFanin0 );
Vec_PtrPush( vNodes, pObj );
}
Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
Aig_ObjCreatePo( p, pObj );
Vec_PtrFree( vNodes );
printf( "Number of nodes = %6d.\n", Aig_ManObjNum(p) );
Aig_ManCleanup( p );
printf( "Number of nodes = %6d.\n", Aig_ManObjNum(p) );
Aig_ManDumpBlif( p, "test1.blif", NULL, NULL );
Aig_ManStop( p );
}
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// END OF FILE /// /// END OF FILE ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

5
src/aig/aig/aigOrder.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -169,3 +172,5 @@ void Aig_ObjOrderAdvance( Aig_Man_t * p )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

148
src/aig/aig/aigPart.c
View File

@ -20,6 +20,10 @@
#include "aig.h" #include "aig.h"
#include "tim.h" #include "tim.h"
#include "fra.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
@ -30,10 +34,10 @@ struct Part_Man_t_
{ {
int nChunkSize; // the size of one chunk of memory (~1 Mb) int nChunkSize; // the size of one chunk of memory (~1 Mb)
int nStepSize; // the step size in saving memory (~64 bytes) int nStepSize; // the step size in saving memory (~64 bytes)
char * pFreeBuf; // the pointer to ABC_FREE memory char * pFreeBuf; // the pointer to free memory
int nFreeSize; // the size of remaining ABC_FREE memory int nFreeSize; // the size of remaining free memory
Vec_Ptr_t * vMemory; // the memory allocated Vec_Ptr_t * vMemory; // the memory allocated
Vec_Ptr_t * vFree; // the vector of ABC_FREE pieces of memory Vec_Ptr_t * vFree; // the vector of free pieces of memory
}; };
typedef struct Part_One_t_ Part_One_t; typedef struct Part_One_t_ Part_One_t;
@ -91,7 +95,7 @@ void Part_ManStop( Part_Man_t * p )
{ {
void * pMemory; void * pMemory;
int i; int i;
Vec_PtrForEachEntry( p->vMemory, pMemory, i ) Vec_PtrForEachEntry( void *, p->vMemory, pMemory, i )
ABC_FREE( pMemory ); ABC_FREE( pMemory );
Vec_PtrFree( p->vMemory ); Vec_PtrFree( p->vMemory );
Vec_PtrFree( p->vFree ); Vec_PtrFree( p->vFree );
@ -116,7 +120,7 @@ char * Part_ManFetch( Part_Man_t * p, int nSize )
assert( nSize > 0 ); assert( nSize > 0 );
Type = Part_SizeType( nSize, p->nStepSize ); Type = Part_SizeType( nSize, p->nStepSize );
Vec_PtrFillExtra( p->vFree, Type + 1, NULL ); Vec_PtrFillExtra( p->vFree, Type + 1, NULL );
if ( (pMemory = Vec_PtrEntry( p->vFree, Type )) ) if ( (pMemory = (char *)Vec_PtrEntry( p->vFree, Type )) )
{ {
Vec_PtrWriteEntry( p->vFree, Type, Part_OneNext(pMemory) ); Vec_PtrWriteEntry( p->vFree, Type, Part_OneNext(pMemory) );
return pMemory; return pMemory;
@ -151,7 +155,7 @@ void Part_ManRecycle( Part_Man_t * p, char * pMemory, int nSize )
int Type; int Type;
Type = Part_SizeType( nSize, p->nStepSize ); Type = Part_SizeType( nSize, p->nStepSize );
Vec_PtrFillExtra( p->vFree, Type + 1, NULL ); Vec_PtrFillExtra( p->vFree, Type + 1, NULL );
Part_OneSetNext( pMemory, Vec_PtrEntry(p->vFree, Type) ); Part_OneSetNext( pMemory, (char *)Vec_PtrEntry(p->vFree, Type) );
Vec_PtrWriteEntry( p->vFree, Type, pMemory ); Vec_PtrWriteEntry( p->vFree, Type, pMemory );
} }
@ -288,8 +292,8 @@ Vec_Ptr_t * Aig_ManSupports( Aig_Man_t * pMan )
{ {
if ( Aig_ObjIsNode(pObj) ) if ( Aig_ObjIsNode(pObj) )
{ {
pPart0 = Aig_ObjFanin0(pObj)->pData; pPart0 = (Part_One_t *)Aig_ObjFanin0(pObj)->pData;
pPart1 = Aig_ObjFanin1(pObj)->pData; pPart1 = (Part_One_t *)Aig_ObjFanin1(pObj)->pData;
pObj->pData = Part_ManMergeEntry( p, pPart0, pPart1, pObj->nRefs ); pObj->pData = Part_ManMergeEntry( p, pPart0, pPart1, pObj->nRefs );
assert( pPart0->nRefs > 0 ); assert( pPart0->nRefs > 0 );
if ( --pPart0->nRefs == 0 ) if ( --pPart0->nRefs == 0 )
@ -301,7 +305,7 @@ Vec_Ptr_t * Aig_ManSupports( Aig_Man_t * pMan )
} }
if ( Aig_ObjIsPo(pObj) ) if ( Aig_ObjIsPo(pObj) )
{ {
pPart0 = Aig_ObjFanin0(pObj)->pData; pPart0 = (Part_One_t *)Aig_ObjFanin0(pObj)->pData;
vSupp = Part_ManTransferEntry(pPart0); vSupp = Part_ManTransferEntry(pPart0);
Vec_IntPush( vSupp, (int)(long)pObj->pNext ); Vec_IntPush( vSupp, (int)(long)pObj->pNext );
Vec_PtrPush( vSupports, vSupp ); Vec_PtrPush( vSupports, vSupp );
@ -369,11 +373,11 @@ Vec_Ptr_t * Aig_ManSupportsInverse( Aig_Man_t * p )
for ( i = 0; i < Aig_ManPiNum(p); i++ ) for ( i = 0; i < Aig_ManPiNum(p); i++ )
Vec_PtrPush( vSuppsInv, Vec_IntAlloc(8) ); Vec_PtrPush( vSuppsInv, Vec_IntAlloc(8) );
// transforms the supports into the inverse supports // transforms the supports into the inverse supports
Vec_PtrForEachEntry( vSupps, vSupp, i ) Vec_PtrForEachEntry( Vec_Int_t *, vSupps, vSupp, i )
{ {
iOut = Vec_IntPop( vSupp ); iOut = Vec_IntPop( vSupp );
Vec_IntForEachEntry( vSupp, iIn, k ) Vec_IntForEachEntry( vSupp, iIn, k )
Vec_IntPush( Vec_PtrEntry(vSuppsInv, iIn), iOut ); Vec_IntPush( (Vec_Int_t *)Vec_PtrEntry(vSuppsInv, iIn), iOut );
} }
Vec_VecFree( (Vec_Vec_t *)vSupps ); Vec_VecFree( (Vec_Vec_t *)vSupps );
return vSuppsInv; return vSuppsInv;
@ -399,7 +403,7 @@ Vec_Ptr_t * Aig_ManSupportsRegisters( Aig_Man_t * p )
vSupports = Aig_ManSupports( p ); vSupports = Aig_ManSupports( p );
// transforms the supports into the latch dependency matrix // transforms the supports into the latch dependency matrix
vMatrix = Vec_PtrStart( Aig_ManRegNum(p) ); vMatrix = Vec_PtrStart( Aig_ManRegNum(p) );
Vec_PtrForEachEntry( vSupports, vSupp, i ) Vec_PtrForEachEntry( Vec_Int_t *, vSupports, vSupp, i )
{ {
// skip true POs // skip true POs
iOut = Vec_IntPop( vSupp ); iOut = Vec_IntPop( vSupp );
@ -426,7 +430,7 @@ Vec_Ptr_t * Aig_ManSupportsRegisters( Aig_Man_t * p )
} }
Vec_PtrFree( vSupports ); Vec_PtrFree( vSupports );
// check that all supports are used // check that all supports are used
Vec_PtrForEachEntry( vMatrix, vSupp, i ) Vec_PtrForEachEntry( Vec_Int_t *, vMatrix, vSupp, i )
assert( vSupp != NULL ); assert( vSupp != NULL );
return vMatrix; return vMatrix;
} }
@ -515,13 +519,13 @@ int Aig_ManPartitionSmartFindPart( Vec_Ptr_t * vPartSuppsAll, Vec_Ptr_t * vParts
int i, nCommon, iBest; int i, nCommon, iBest;
iBest = -1; iBest = -1;
ValueBest = 0; ValueBest = 0;
Vec_PtrForEachEntry( vPartSuppsAll, vPartSupp, i ) Vec_PtrForEachEntry( Vec_Int_t *, vPartSuppsAll, vPartSupp, i )
{ {
// vPart = Vec_PtrEntry( vPartsAll, i ); // vPart = Vec_PtrEntry( vPartsAll, i );
// if ( nSuppSizeLimit > 0 && Vec_IntSize(vPart) >= nSuppSizeLimit ) // if ( nSuppSizeLimit > 0 && Vec_IntSize(vPart) >= nSuppSizeLimit )
// continue; // continue;
// nCommon = Vec_IntTwoCountCommon( vPartSupp, vOne ); // nCommon = Vec_IntTwoCountCommon( vPartSupp, vOne );
nCommon = Aig_ManSuppCharCommon( Vec_PtrEntry(vPartSuppsBit, i), vOne ); nCommon = Aig_ManSuppCharCommon( (unsigned *)Vec_PtrEntry(vPartSuppsBit, i), vOne );
if ( nCommon == 0 ) if ( nCommon == 0 )
continue; continue;
if ( nCommon == Vec_IntSize(vOne) ) if ( nCommon == Vec_IntSize(vOne) )
@ -563,9 +567,9 @@ void Aig_ManPartitionPrint( Aig_Man_t * p, Vec_Ptr_t * vPartsAll, Vec_Ptr_t * vP
int i, nOutputs, Counter; int i, nOutputs, Counter;
Counter = 0; Counter = 0;
Vec_PtrForEachEntry( vPartSuppsAll, vOne, i ) Vec_PtrForEachEntry( Vec_Int_t *, vPartSuppsAll, vOne, i )
{ {
nOutputs = Vec_IntSize(Vec_PtrEntry(vPartsAll, i)); nOutputs = Vec_IntSize((Vec_Int_t *)Vec_PtrEntry(vPartsAll, i));
printf( "%d=(%d,%d) ", i, Vec_IntSize(vOne), nOutputs ); printf( "%d=(%d,%d) ", i, Vec_IntSize(vOne), nOutputs );
Counter += nOutputs; Counter += nOutputs;
if ( i == Vec_PtrSize(vPartsAll) - 1 ) if ( i == Vec_PtrSize(vPartsAll) - 1 )
@ -597,7 +601,7 @@ void Aig_ManPartitionCompact( Vec_Ptr_t * vPartsAll, Vec_Ptr_t * vPartSuppsAll,
// pack smaller partitions into larger blocks // pack smaller partitions into larger blocks
iPart = 0; iPart = 0;
vPart = vPartSupp = NULL; vPart = vPartSupp = NULL;
Vec_PtrForEachEntry( vPartSuppsAll, vOne, i ) Vec_PtrForEachEntry( Vec_Int_t *, vPartSuppsAll, vOne, i )
{ {
if ( Vec_IntSize(vOne) < nSuppSizeLimit ) if ( Vec_IntSize(vOne) < nSuppSizeLimit )
{ {
@ -605,27 +609,27 @@ void Aig_ManPartitionCompact( Vec_Ptr_t * vPartsAll, Vec_Ptr_t * vPartSuppsAll,
{ {
assert( vPart == NULL ); assert( vPart == NULL );
vPartSupp = Vec_IntDup(vOne); vPartSupp = Vec_IntDup(vOne);
vPart = Vec_PtrEntry(vPartsAll, i); vPart = (Vec_Int_t *)Vec_PtrEntry(vPartsAll, i);
} }
else else
{ {
vPartSupp = Vec_IntTwoMerge( vTemp = vPartSupp, vOne ); vPartSupp = Vec_IntTwoMerge( vTemp = vPartSupp, vOne );
Vec_IntFree( vTemp ); Vec_IntFree( vTemp );
vPart = Vec_IntTwoMerge( vTemp = vPart, Vec_PtrEntry(vPartsAll, i) ); vPart = Vec_IntTwoMerge( vTemp = vPart, (Vec_Int_t *)Vec_PtrEntry(vPartsAll, i) );
Vec_IntFree( vTemp ); Vec_IntFree( vTemp );
Vec_IntFree( Vec_PtrEntry(vPartsAll, i) ); Vec_IntFree( (Vec_Int_t *)Vec_PtrEntry(vPartsAll, i) );
} }
if ( Vec_IntSize(vPartSupp) < nSuppSizeLimit ) if ( Vec_IntSize(vPartSupp) < nSuppSizeLimit )
continue; continue;
} }
else else
vPart = Vec_PtrEntry(vPartsAll, i); vPart = (Vec_Int_t *)Vec_PtrEntry(vPartsAll, i);
// add the partition // add the partition
Vec_PtrWriteEntry( vPartsAll, iPart, vPart ); Vec_PtrWriteEntry( vPartsAll, iPart, vPart );
vPart = NULL; vPart = NULL;
if ( vPartSupp ) if ( vPartSupp )
{ {
Vec_IntFree( Vec_PtrEntry(vPartSuppsAll, iPart) ); Vec_IntFree( (Vec_Int_t *)Vec_PtrEntry(vPartSuppsAll, iPart) );
Vec_PtrWriteEntry( vPartSuppsAll, iPart, vPartSupp ); Vec_PtrWriteEntry( vPartSuppsAll, iPart, vPartSupp );
vPartSupp = NULL; vPartSupp = NULL;
} }
@ -638,7 +642,7 @@ void Aig_ManPartitionCompact( Vec_Ptr_t * vPartsAll, Vec_Ptr_t * vPartSuppsAll,
vPart = NULL; vPart = NULL;
assert( vPartSupp != NULL ); assert( vPartSupp != NULL );
Vec_IntFree( Vec_PtrEntry(vPartSuppsAll, iPart) ); Vec_IntFree( (Vec_Int_t *)Vec_PtrEntry(vPartSuppsAll, iPart) );
Vec_PtrWriteEntry( vPartSuppsAll, iPart, vPartSupp ); Vec_PtrWriteEntry( vPartSuppsAll, iPart, vPartSupp );
vPartSupp = NULL; vPartSupp = NULL;
iPart++; iPart++;
@ -679,7 +683,7 @@ ABC_PRT( "Supps", clock() - clk );
clk = clock(); clk = clock();
vPartsAll = Vec_PtrAlloc( 256 ); vPartsAll = Vec_PtrAlloc( 256 );
vPartSuppsAll = Vec_PtrAlloc( 256 ); vPartSuppsAll = Vec_PtrAlloc( 256 );
Vec_PtrForEachEntry( vSupports, vOne, i ) Vec_PtrForEachEntry( Vec_Int_t *, vSupports, vOne, i )
{ {
// get the output number // get the output number
iOut = Vec_IntPop(vOne); iOut = Vec_IntPop(vOne);
@ -701,21 +705,21 @@ clk = clock();
else else
{ {
// add output to this partition // add output to this partition
vPart = Vec_PtrEntry( vPartsAll, iPart ); vPart = (Vec_Int_t *)Vec_PtrEntry( vPartsAll, iPart );
Vec_IntPush( vPart, iOut ); Vec_IntPush( vPart, iOut );
// merge supports // merge supports
vPartSupp = Vec_PtrEntry( vPartSuppsAll, iPart ); vPartSupp = (Vec_Int_t *)Vec_PtrEntry( vPartSuppsAll, iPart );
vPartSupp = Vec_IntTwoMerge( vTemp = vPartSupp, vOne ); vPartSupp = Vec_IntTwoMerge( vTemp = vPartSupp, vOne );
Vec_IntFree( vTemp ); Vec_IntFree( vTemp );
// reinsert new support // reinsert new support
Vec_PtrWriteEntry( vPartSuppsAll, iPart, vPartSupp ); Vec_PtrWriteEntry( vPartSuppsAll, iPart, vPartSupp );
Aig_ManSuppCharAdd( Vec_PtrEntry(vPartSuppsBit, iPart), vOne, Aig_ManPiNum(p) ); Aig_ManSuppCharAdd( (unsigned *)Vec_PtrEntry(vPartSuppsBit, iPart), vOne, Aig_ManPiNum(p) );
} }
} }
// stop char-based support representation // stop char-based support representation
Vec_PtrForEachEntry( vPartSuppsBit, vTemp, i ) Vec_PtrForEachEntry( Vec_Int_t *, vPartSuppsBit, vTemp, i )
ABC_FREE( vTemp ); ABC_FREE( vTemp );
Vec_PtrFree( vPartSuppsBit ); Vec_PtrFree( vPartSuppsBit );
@ -728,13 +732,13 @@ ABC_PRT( "Parts", clock() - clk );
clk = clock(); clk = clock();
// reorder partitions in the decreasing order of support sizes // reorder partitions in the decreasing order of support sizes
// remember partition number in each partition support // remember partition number in each partition support
Vec_PtrForEachEntry( vPartSuppsAll, vOne, i ) Vec_PtrForEachEntry( Vec_Int_t *, vPartSuppsAll, vOne, i )
Vec_IntPush( vOne, i ); Vec_IntPush( vOne, i );
// sort the supports in the decreasing order // sort the supports in the decreasing order
Vec_VecSort( (Vec_Vec_t *)vPartSuppsAll, 1 ); Vec_VecSort( (Vec_Vec_t *)vPartSuppsAll, 1 );
// reproduce partitions // reproduce partitions
vPartsAll2 = Vec_PtrAlloc( 256 ); vPartsAll2 = Vec_PtrAlloc( 256 );
Vec_PtrForEachEntry( vPartSuppsAll, vOne, i ) Vec_PtrForEachEntry( Vec_Int_t *, vPartSuppsAll, vOne, i )
Vec_PtrPush( vPartsAll2, Vec_PtrEntry(vPartsAll, Vec_IntPop(vOne)) ); Vec_PtrPush( vPartsAll2, Vec_PtrEntry(vPartsAll, Vec_IntPop(vOne)) );
Vec_PtrFree( vPartsAll ); Vec_PtrFree( vPartsAll );
vPartsAll = vPartsAll2; vPartsAll = vPartsAll2;
@ -759,7 +763,7 @@ if ( fVerbose )
*pvPartSupps = vPartSuppsAll; *pvPartSupps = vPartSuppsAll;
/* /*
// converts from intergers to nodes // converts from intergers to nodes
Vec_PtrForEachEntry( vPartsAll, vPart, iPart ) Vec_PtrForEachEntry( Vec_Int_t *, vPartsAll, vPart, iPart )
{ {
vPartPtr = Vec_PtrAlloc( Vec_IntSize(vPart) ); vPartPtr = Vec_PtrAlloc( Vec_IntSize(vPart) );
Vec_IntForEachEntry( vPart, iOut, i ) Vec_IntForEachEntry( vPart, iOut, i )
@ -793,7 +797,7 @@ Vec_Ptr_t * Aig_ManPartitionSmartRegisters( Aig_Man_t * pAig, int nSuppSizeLimit
clk = clock(); clk = clock();
vSupports = Aig_ManSupportsRegisters( pAig ); vSupports = Aig_ManSupportsRegisters( pAig );
assert( Vec_PtrSize(vSupports) == Aig_ManRegNum(pAig) ); assert( Vec_PtrSize(vSupports) == Aig_ManRegNum(pAig) );
Vec_PtrForEachEntry( vSupports, vOne, i ) Vec_PtrForEachEntry( Vec_Int_t *, vSupports, vOne, i )
Vec_IntPush( vOne, i ); Vec_IntPush( vOne, i );
if ( fVerbose ) if ( fVerbose )
{ {
@ -807,7 +811,7 @@ ABC_PRT( "Supps", clock() - clk );
clk = clock(); clk = clock();
vPartsAll = Vec_PtrAlloc( 256 ); vPartsAll = Vec_PtrAlloc( 256 );
vPartSuppsAll = Vec_PtrAlloc( 256 ); vPartSuppsAll = Vec_PtrAlloc( 256 );
Vec_PtrForEachEntry( vSupports, vOne, i ) Vec_PtrForEachEntry( Vec_Int_t *, vSupports, vOne, i )
{ {
// get the output number // get the output number
iOut = Vec_IntPop(vOne); iOut = Vec_IntPop(vOne);
@ -829,21 +833,21 @@ clk = clock();
else else
{ {
// add output to this partition // add output to this partition
vPart = Vec_PtrEntry( vPartsAll, iPart ); vPart = (Vec_Int_t *)Vec_PtrEntry( vPartsAll, iPart );
Vec_IntPush( vPart, iOut ); Vec_IntPush( vPart, iOut );
// merge supports // merge supports
vPartSupp = Vec_PtrEntry( vPartSuppsAll, iPart ); vPartSupp = (Vec_Int_t *)Vec_PtrEntry( vPartSuppsAll, iPart );
vPartSupp = Vec_IntTwoMerge( vTemp = vPartSupp, vOne ); vPartSupp = Vec_IntTwoMerge( vTemp = vPartSupp, vOne );
Vec_IntFree( vTemp ); Vec_IntFree( vTemp );
// reinsert new support // reinsert new support
Vec_PtrWriteEntry( vPartSuppsAll, iPart, vPartSupp ); Vec_PtrWriteEntry( vPartSuppsAll, iPart, vPartSupp );
Aig_ManSuppCharAdd( Vec_PtrEntry(vPartSuppsBit, iPart), vOne, Vec_PtrSize(vSupports) ); Aig_ManSuppCharAdd( (unsigned *)Vec_PtrEntry(vPartSuppsBit, iPart), vOne, Vec_PtrSize(vSupports) );
} }
} }
// stop char-based support representation // stop char-based support representation
Vec_PtrForEachEntry( vPartSuppsBit, vTemp, i ) Vec_PtrForEachEntry( Vec_Int_t *, vPartSuppsBit, vTemp, i )
ABC_FREE( vTemp ); ABC_FREE( vTemp );
Vec_PtrFree( vPartSuppsBit ); Vec_PtrFree( vPartSuppsBit );
@ -856,13 +860,13 @@ ABC_PRT( "Parts", clock() - clk );
clk = clock(); clk = clock();
// reorder partitions in the decreasing order of support sizes // reorder partitions in the decreasing order of support sizes
// remember partition number in each partition support // remember partition number in each partition support
Vec_PtrForEachEntry( vPartSuppsAll, vOne, i ) Vec_PtrForEachEntry( Vec_Int_t *, vPartSuppsAll, vOne, i )
Vec_IntPush( vOne, i ); Vec_IntPush( vOne, i );
// sort the supports in the decreasing order // sort the supports in the decreasing order
Vec_VecSort( (Vec_Vec_t *)vPartSuppsAll, 1 ); Vec_VecSort( (Vec_Vec_t *)vPartSuppsAll, 1 );
// reproduce partitions // reproduce partitions
vPartsAll2 = Vec_PtrAlloc( 256 ); vPartsAll2 = Vec_PtrAlloc( 256 );
Vec_PtrForEachEntry( vPartSuppsAll, vOne, i ) Vec_PtrForEachEntry( Vec_Int_t *, vPartSuppsAll, vOne, i )
Vec_PtrPush( vPartsAll2, Vec_PtrEntry(vPartsAll, Vec_IntPop(vOne)) ); Vec_PtrPush( vPartsAll2, Vec_PtrEntry(vPartsAll, Vec_IntPop(vOne)) );
Vec_PtrFree( vPartsAll ); Vec_PtrFree( vPartsAll );
vPartsAll = vPartsAll2; vPartsAll = vPartsAll2;
@ -888,7 +892,7 @@ if ( fVerbose )
/* /*
// converts from intergers to nodes // converts from intergers to nodes
Vec_PtrForEachEntry( vPartsAll, vPart, iPart ) Vec_PtrForEachEntry( Vec_Int_t *, vPartsAll, vPart, iPart )
{ {
vPartPtr = Vec_PtrAlloc( Vec_IntSize(vPart) ); vPartPtr = Vec_PtrAlloc( Vec_IntSize(vPart) );
Vec_IntForEachEntry( vPart, iOut, i ) Vec_IntForEachEntry( vPart, iOut, i )
@ -919,7 +923,7 @@ Vec_Ptr_t * Aig_ManPartitionNaive( Aig_Man_t * p, int nPartSize )
nParts = (Aig_ManPoNum(p) / nPartSize) + ((Aig_ManPoNum(p) % nPartSize) > 0); nParts = (Aig_ManPoNum(p) / nPartSize) + ((Aig_ManPoNum(p) % nPartSize) > 0);
vParts = (Vec_Ptr_t *)Vec_VecStart( nParts ); vParts = (Vec_Ptr_t *)Vec_VecStart( nParts );
Aig_ManForEachPo( p, pObj, i ) Aig_ManForEachPo( p, pObj, i )
Vec_IntPush( Vec_PtrEntry(vParts, i / nPartSize), i ); Vec_IntPush( (Vec_Int_t *)Vec_PtrEntry(vParts, i / nPartSize), i );
return vParts; return vParts;
} }
@ -940,18 +944,18 @@ Aig_Obj_t * Aig_ManDupPart_rec( Aig_Man_t * pNew, Aig_Man_t * pOld, Aig_Obj_t *
{ {
assert( !Aig_IsComplement(pObj) ); assert( !Aig_IsComplement(pObj) );
if ( Aig_ObjIsTravIdCurrent(pOld, pObj) ) if ( Aig_ObjIsTravIdCurrent(pOld, pObj) )
return pObj->pData; return (Aig_Obj_t *)pObj->pData;
Aig_ObjSetTravIdCurrent(pOld, pObj); Aig_ObjSetTravIdCurrent(pOld, pObj);
if ( Aig_ObjIsPi(pObj) ) if ( Aig_ObjIsPi(pObj) )
{ {
assert( Vec_IntSize(vSuppMap) == Aig_ManPiNum(pNew) ); assert( Vec_IntSize(vSuppMap) == Aig_ManPiNum(pNew) );
Vec_IntPush( vSuppMap, (int)(long)pObj->pNext ); Vec_IntPush( vSuppMap, (int)(long)pObj->pNext );
return pObj->pData = Aig_ObjCreatePi(pNew); return (Aig_Obj_t *)(pObj->pData = Aig_ObjCreatePi(pNew));
} }
assert( Aig_ObjIsNode(pObj) ); assert( Aig_ObjIsNode(pObj) );
Aig_ManDupPart_rec( pNew, pOld, Aig_ObjFanin0(pObj), vSuppMap ); Aig_ManDupPart_rec( pNew, pOld, Aig_ObjFanin0(pObj), vSuppMap );
Aig_ManDupPart_rec( pNew, pOld, Aig_ObjFanin1(pObj), vSuppMap ); Aig_ManDupPart_rec( pNew, pOld, Aig_ObjFanin1(pObj), vSuppMap );
return pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) ); return (Aig_Obj_t *)(pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) ));
} }
/**Function************************************************************* /**Function*************************************************************
@ -1133,7 +1137,7 @@ Vec_Ptr_t * Aig_ManSupportNodes( Aig_Man_t * p, Vec_Ptr_t * vParts )
int i, k, iOut; int i, k, iOut;
Aig_ManSetPioNumbers( p ); Aig_ManSetPioNumbers( p );
vPartSupps = Vec_PtrAlloc( Vec_PtrSize(vParts) ); vPartSupps = Vec_PtrAlloc( Vec_PtrSize(vParts) );
Vec_PtrForEachEntry( vParts, vPart, i ) Vec_PtrForEachEntry( Vec_Int_t *, vParts, vPart, i )
{ {
vSupport = Vec_IntAlloc( 100 ); vSupport = Vec_IntAlloc( 100 );
Aig_ManIncrementTravId( p ); Aig_ManIncrementTravId( p );
@ -1180,8 +1184,8 @@ Vec_Ptr_t * Aig_ManMiterPartitioned( Aig_Man_t * p1, Aig_Man_t * p2, int nPartSi
for ( i = 0; i < Vec_PtrSize(vParts); i++ ) for ( i = 0; i < Vec_PtrSize(vParts); i++ )
{ {
// get partition and its support // get partition and its support
vPart = Vec_PtrEntry( vParts, i ); vPart = (Vec_Int_t *)Vec_PtrEntry( vParts, i );
vPartSupp = Vec_PtrEntry( vPartSupps, i ); vPartSupp = (Vec_Int_t *)Vec_PtrEntry( vPartSupps, i );
// create the new miter // create the new miter
pNew = Aig_ManStart( 1000 ); pNew = Aig_ManStart( 1000 );
// create the PIs // create the PIs
@ -1221,7 +1225,7 @@ Aig_Man_t * Aig_ManChoicePartitioned( Vec_Ptr_t * vAigs, int nPartSize, int nCon
{ {
// extern int Cmd_CommandExecute( void * pAbc, char * sCommand ); // extern int Cmd_CommandExecute( void * pAbc, char * sCommand );
// extern void * Abc_FrameGetGlobalFrame(); // extern void * Abc_FrameGetGlobalFrame();
extern Aig_Man_t * Fra_FraigChoice( Aig_Man_t * pManAig, int nConfMax, int nLevelMax ); // extern Aig_Man_t * Fra_FraigChoice( Aig_Man_t * pManAig, int nConfMax, int nLevelMax );
Vec_Ptr_t * vPios; Vec_Ptr_t * vPios;
Vec_Ptr_t * vOutsTotal, * vOuts; Vec_Ptr_t * vOutsTotal, * vOuts;
@ -1235,11 +1239,11 @@ Aig_Man_t * Aig_ManChoicePartitioned( Vec_Ptr_t * vAigs, int nPartSize, int nCon
// compute the total number of IDs // compute the total number of IDs
nIdMax = 0; nIdMax = 0;
Vec_PtrForEachEntry( vAigs, pAig, i ) Vec_PtrForEachEntry( Aig_Man_t *, vAigs, pAig, i )
nIdMax += Aig_ManObjNumMax(pAig); nIdMax += Aig_ManObjNumMax(pAig);
// partition the first AIG in the array // partition the first AIG in the array
pAig = Vec_PtrEntry( vAigs, 0 ); pAig = (Aig_Man_t *)Vec_PtrEntry( vAigs, 0 );
vParts = Aig_ManPartitionSmart( pAig, nPartSize, 0, NULL ); vParts = Aig_ManPartitionSmart( pAig, nPartSize, 0, NULL );
// start the total fraiged AIG // start the total fraiged AIG
@ -1248,7 +1252,7 @@ Aig_Man_t * Aig_ManChoicePartitioned( Vec_Ptr_t * vAigs, int nPartSize, int nCon
vOutsTotal = Vec_PtrStart( Aig_ManPoNum(pAig) ); vOutsTotal = Vec_PtrStart( Aig_ManPoNum(pAig) );
// set the PI numbers // set the PI numbers
Vec_PtrForEachEntry( vAigs, pAig, i ) Vec_PtrForEachEntry( Aig_Man_t *, vAigs, pAig, i )
Aig_ManForEachPi( pAig, pObj, k ) Aig_ManForEachPi( pAig, pObj, k )
pObj->pNext = (Aig_Obj_t *)(long)k; pObj->pNext = (Aig_Obj_t *)(long)k;
@ -1256,18 +1260,18 @@ Aig_Man_t * Aig_ManChoicePartitioned( Vec_Ptr_t * vAigs, int nPartSize, int nCon
// create the total fraiged AIG // create the total fraiged AIG
vPartSupp = Vec_IntAlloc( 100 ); // maps part PI num into total PI num vPartSupp = Vec_IntAlloc( 100 ); // maps part PI num into total PI num
Vec_PtrForEachEntry( vParts, vPart, i ) Vec_PtrForEachEntry( Vec_Int_t *, vParts, vPart, i )
{ {
// derive the partition AIG // derive the partition AIG
pAigPart = Aig_ManStart( 5000 ); pAigPart = Aig_ManStart( 5000 );
// pAigPart->pName = Extra_UtilStrsav( pAigPart->pName ); // pAigPart->pName = Extra_UtilStrsav( pAigPart->pName );
Vec_IntClear( vPartSupp ); Vec_IntClear( vPartSupp );
Vec_PtrForEachEntry( vAigs, pAig, k ) Vec_PtrForEachEntry( Aig_Man_t *, vAigs, pAig, k )
{ {
vOuts = Aig_ManDupPart( pAigPart, pAig, vPart, vPartSupp, 0 ); vOuts = Aig_ManDupPart( pAigPart, pAig, vPart, vPartSupp, 0 );
if ( k == 0 ) if ( k == 0 )
{ {
Vec_PtrForEachEntry( vOuts, pObj, m ) Vec_PtrForEachEntry( Aig_Obj_t *, vOuts, pObj, m )
Aig_ObjCreatePo( pAigPart, pObj ); Aig_ObjCreatePo( pAigPart, pObj );
} }
Vec_PtrFree( vOuts ); Vec_PtrFree( vOuts );
@ -1275,7 +1279,7 @@ Aig_Man_t * Aig_ManChoicePartitioned( Vec_Ptr_t * vAigs, int nPartSize, int nCon
// derive the total AIG from the partitioned AIG // derive the total AIG from the partitioned AIG
vOuts = Aig_ManDupPart( pAigTotal, pAigPart, vPart, vPartSupp, 1 ); vOuts = Aig_ManDupPart( pAigTotal, pAigPart, vPart, vPartSupp, 1 );
// add to the outputs // add to the outputs
Vec_PtrForEachEntry( vOuts, pObj, k ) Vec_PtrForEachEntry( Aig_Obj_t *, vOuts, pObj, k )
{ {
assert( Vec_PtrEntry( vOutsTotal, Vec_IntEntry(vPart,k) ) == NULL ); assert( Vec_PtrEntry( vOutsTotal, Vec_IntEntry(vPart,k) ) == NULL );
Vec_PtrWriteEntry( vOutsTotal, Vec_IntEntry(vPart,k), pObj ); Vec_PtrWriteEntry( vOutsTotal, Vec_IntEntry(vPart,k), pObj );
@ -1310,12 +1314,12 @@ Aig_Man_t * Aig_ManChoicePartitioned( Vec_Ptr_t * vAigs, int nPartSize, int nCon
// Cmd_CommandExecute( Abc_FrameGetGlobalFrame(), "set progressbar" ); // Cmd_CommandExecute( Abc_FrameGetGlobalFrame(), "set progressbar" );
// clear the PI numbers // clear the PI numbers
Vec_PtrForEachEntry( vAigs, pAig, i ) Vec_PtrForEachEntry( Aig_Man_t *, vAigs, pAig, i )
Aig_ManForEachPi( pAig, pObj, k ) Aig_ManForEachPi( pAig, pObj, k )
pObj->pNext = NULL; pObj->pNext = NULL;
// add the outputs in the same order // add the outputs in the same order
Vec_PtrForEachEntry( vOutsTotal, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vOutsTotal, pObj, i )
Aig_ObjCreatePo( pAigTotal, pObj ); Aig_ObjCreatePo( pAigTotal, pObj );
Vec_PtrFree( vOutsTotal ); Vec_PtrFree( vOutsTotal );
@ -1324,14 +1328,14 @@ Aig_Man_t * Aig_ManChoicePartitioned( Vec_Ptr_t * vAigs, int nPartSize, int nCon
// create the equivalent nodes lists // create the equivalent nodes lists
Aig_ManMarkValidChoices( pAig ); Aig_ManMarkValidChoices( pAig );
// reconstruct the network // reconstruct the network
vPios = Aig_ManOrderPios( pAig, Vec_PtrEntry(vAigs,0) ); vPios = Aig_ManOrderPios( pAig, (Aig_Man_t *)Vec_PtrEntry(vAigs,0) );
pAig = Aig_ManDupDfsGuided( pTemp = pAig, vPios ); pAig = Aig_ManDupDfsGuided( pTemp = pAig, vPios );
Aig_ManStop( pTemp ); Aig_ManStop( pTemp );
Vec_PtrFree( vPios ); Vec_PtrFree( vPios );
// duplicate the timing manager // duplicate the timing manager
pTemp = Vec_PtrEntry( vAigs, 0 ); pTemp = (Aig_Man_t *)Vec_PtrEntry( vAigs, 0 );
if ( pTemp->pManTime ) if ( pTemp->pManTime )
pAig->pManTime = Tim_ManDup( pTemp->pManTime, 0 ); pAig->pManTime = Tim_ManDup( (Tim_Man_t *)pTemp->pManTime, 0 );
// reset levels // reset levels
Aig_ManChoiceLevel( pAig ); Aig_ManChoiceLevel( pAig );
return pAig; return pAig;
@ -1351,7 +1355,7 @@ Aig_Man_t * Aig_ManChoicePartitioned( Vec_Ptr_t * vAigs, int nPartSize, int nCon
***********************************************************************/ ***********************************************************************/
Aig_Man_t * Aig_ManFraigPartitioned( Aig_Man_t * pAig, int nPartSize, int nConfMax, int nLevelMax, int fVerbose ) Aig_Man_t * Aig_ManFraigPartitioned( Aig_Man_t * pAig, int nPartSize, int nConfMax, int nLevelMax, int fVerbose )
{ {
extern Aig_Man_t * Fra_FraigChoice( Aig_Man_t * pManAig, int nConfMax, int nLevelMax ); // extern Aig_Man_t * Fra_FraigChoice( Aig_Man_t * pManAig, int nConfMax, int nLevelMax );
Aig_Man_t * pAigPart, * pAigTemp; Aig_Man_t * pAigPart, * pAigTemp;
Vec_Int_t * vPart; Vec_Int_t * vPart;
@ -1370,7 +1374,7 @@ Aig_Man_t * Aig_ManFraigPartitioned( Aig_Man_t * pAig, int nPartSize, int nConfM
Aig_ManSetPioNumbers( pAig ); Aig_ManSetPioNumbers( pAig );
// create the total fraiged AIG // create the total fraiged AIG
Vec_PtrForEachEntry( vParts, vPart, i ) Vec_PtrForEachEntry( Vec_Int_t *, vParts, vPart, i )
{ {
// derive the partition AIG // derive the partition AIG
pAigPart = Aig_ManDupPartAll( pAig, vPart ); pAigPart = Aig_ManDupPartAll( pAig, vPart );
@ -1460,7 +1464,7 @@ void Aig_ManChoiceConstructiveOne( Aig_Man_t * pNew, Aig_Man_t * pPrev, Aig_Man_
Aig_ManForEachObj( pNew, pObj, i ) Aig_ManForEachObj( pNew, pObj, i )
pObj->fMarkB = 1; pObj->fMarkB = 1;
Aig_ManForEachObj( pPrev, pObj, i ) Aig_ManForEachObj( pPrev, pObj, i )
assert( Aig_Regular(pObj->pData)->fMarkB ); assert( Aig_Regular((Aig_Obj_t *)pObj->pData)->fMarkB );
Aig_ManForEachObj( pNew, pObj, i ) Aig_ManForEachObj( pNew, pObj, i )
pObj->fMarkB = 0; pObj->fMarkB = 0;
// make sure the nodes of pThis point to pPrev // make sure the nodes of pThis point to pPrev
@ -1484,14 +1488,14 @@ void Aig_ManChoiceConstructiveOne( Aig_Man_t * pNew, Aig_Man_t * pPrev, Aig_Man_
if ( pObj->pHaig == NULL ) if ( pObj->pHaig == NULL )
continue; continue;
// pObj->pData and pObj->pHaig->pData are equivalent // pObj->pData and pObj->pHaig->pData are equivalent
Aig_ObjSetRepr_( pNew, Aig_Regular(pObj->pData), Aig_Regular(pObj->pHaig->pData) ); Aig_ObjSetRepr_( pNew, Aig_Regular((Aig_Obj_t *)pObj->pData), Aig_Regular((Aig_Obj_t *)pObj->pHaig->pData) );
} }
// set the inputs of POs as equivalent // set the inputs of POs as equivalent
Aig_ManForEachPo( pThis, pObj, i ) Aig_ManForEachPo( pThis, pObj, i )
{ {
pObjNew = Aig_ObjFanin0( Aig_ManPo(pNew,i) ); pObjNew = Aig_ObjFanin0( Aig_ManPo(pNew,i) );
// pObjNew and Aig_ObjFanin0(pObj)->pData are equivalent // pObjNew and Aig_ObjFanin0(pObj)->pData are equivalent
Aig_ObjSetRepr_( pNew, pObjNew, Aig_Regular(Aig_ObjFanin0(pObj)->pData) ); Aig_ObjSetRepr_( pNew, pObjNew, Aig_Regular((Aig_Obj_t *)Aig_ObjFanin0(pObj)->pData) );
} }
} }
@ -1548,7 +1552,7 @@ Aig_Man_t * Aig_ManChoiceConstructive( Vec_Ptr_t * vAigs, int fVerbose )
Aig_Man_t * pNew, * pThis, * pPrev, * pTemp; Aig_Man_t * pNew, * pThis, * pPrev, * pTemp;
int i; int i;
// start AIG with choices // start AIG with choices
pPrev = Vec_PtrEntry( vAigs, 0 ); pPrev = (Aig_Man_t *)Vec_PtrEntry( vAigs, 0 );
pNew = Aig_ManDupOrdered( pPrev ); pNew = Aig_ManDupOrdered( pPrev );
// create room for equivalent nodes and representatives // create room for equivalent nodes and representatives
assert( pNew->pReprs == NULL ); assert( pNew->pReprs == NULL );
@ -1556,7 +1560,7 @@ Aig_Man_t * Aig_ManChoiceConstructive( Vec_Ptr_t * vAigs, int fVerbose )
pNew->pReprs = ABC_ALLOC( Aig_Obj_t *, pNew->nReprsAlloc ); pNew->pReprs = ABC_ALLOC( Aig_Obj_t *, pNew->nReprsAlloc );
memset( pNew->pReprs, 0, sizeof(Aig_Obj_t *) * pNew->nReprsAlloc ); memset( pNew->pReprs, 0, sizeof(Aig_Obj_t *) * pNew->nReprsAlloc );
// add other AIGs one by one // add other AIGs one by one
Vec_PtrForEachEntryStart( vAigs, pThis, i, 1 ) Vec_PtrForEachEntryStart( Aig_Man_t *, vAigs, pThis, i, 1 )
{ {
Aig_ManChoiceConstructiveOne( pNew, pPrev, pThis ); Aig_ManChoiceConstructiveOne( pNew, pPrev, pThis );
pPrev = pThis; pPrev = pThis;
@ -1566,14 +1570,14 @@ Aig_Man_t * Aig_ManChoiceConstructive( Vec_Ptr_t * vAigs, int fVerbose )
// create the equivalent nodes lists // create the equivalent nodes lists
Aig_ManMarkValidChoices( pNew ); Aig_ManMarkValidChoices( pNew );
// reconstruct the network // reconstruct the network
vPios = Aig_ManOrderPios( pNew, Vec_PtrEntry( vAigs, 0 ) ); vPios = Aig_ManOrderPios( pNew, (Aig_Man_t *)Vec_PtrEntry( vAigs, 0 ) );
pNew = Aig_ManDupDfsGuided( pTemp = pNew, vPios ); pNew = Aig_ManDupDfsGuided( pTemp = pNew, vPios );
Aig_ManStop( pTemp ); Aig_ManStop( pTemp );
Vec_PtrFree( vPios ); Vec_PtrFree( vPios );
// duplicate the timing manager // duplicate the timing manager
pTemp = Vec_PtrEntry( vAigs, 0 ); pTemp = (Aig_Man_t *)Vec_PtrEntry( vAigs, 0 );
if ( pTemp->pManTime ) if ( pTemp->pManTime )
pNew->pManTime = Tim_ManDup( pTemp->pManTime, 0 ); pNew->pManTime = Tim_ManDup( (Tim_Man_t *)pTemp->pManTime, 0 );
// reset levels // reset levels
Aig_ManChoiceLevel( pNew ); Aig_ManChoiceLevel( pNew );
return pNew; return pNew;
@ -1590,3 +1594,5 @@ Aig_Man_t * Aig_ManChoiceConstructive( Vec_Ptr_t * vAigs, int fVerbose )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

33
src/aig/aig/aigPartReg.c
View File

@ -21,6 +21,9 @@
#include "aig.h" #include "aig.h"
//#include "fra.h" //#include "fra.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -127,7 +130,7 @@ int Aig_ManRegFindSeed( Aig_ManPre_t * p )
if ( p->pfUsedRegs[i] ) if ( p->pfUsedRegs[i] )
continue; continue;
nRegsCur = 0; nRegsCur = 0;
vRegs = Vec_PtrEntry( p->vMatrix, i ); vRegs = (Vec_Int_t *)Vec_PtrEntry( p->vMatrix, i );
Vec_IntForEachEntry( vRegs, iReg, k ) Vec_IntForEachEntry( vRegs, iReg, k )
nRegsCur += !p->pfUsedRegs[iReg]; nRegsCur += !p->pfUsedRegs[iReg];
if ( nRegsMax < nRegsCur ) if ( nRegsMax < nRegsCur )
@ -155,13 +158,13 @@ int Aig_ManRegFindBestVar( Aig_ManPre_t * p )
Vec_Int_t * vSupp; Vec_Int_t * vSupp;
int nNewVars, nNewVarsBest = ABC_INFINITY; int nNewVars, nNewVarsBest = ABC_INFINITY;
int iVarFree, iVarSupp, iVarBest = -1, i, k; int iVarFree, iVarSupp, iVarBest = -1, i, k;
// go through the ABC_FREE variables // go through the free variables
Vec_IntForEachEntry( p->vFreeVars, iVarFree, i ) Vec_IntForEachEntry( p->vFreeVars, iVarFree, i )
{ {
// if ( p->pfUsedRegs[iVarFree] ) // if ( p->pfUsedRegs[iVarFree] )
// continue; // continue;
// get support of this variable // get support of this variable
vSupp = Vec_PtrEntry( p->vMatrix, iVarFree ); vSupp = (Vec_Int_t *)Vec_PtrEntry( p->vMatrix, iVarFree );
// count the number of new vars // count the number of new vars
nNewVars = 0; nNewVars = 0;
Vec_IntForEachEntry( vSupp, iVarSupp, k ) Vec_IntForEachEntry( vSupp, iVarSupp, k )
@ -205,7 +208,7 @@ void Aig_ManRegPartitionAdd( Aig_ManPre_t * p, int iReg )
p->pfUsedRegs[iReg] = 1; p->pfUsedRegs[iReg] = 1;
Vec_IntPush( p->vUniques, iReg ); Vec_IntPush( p->vUniques, iReg );
} }
// remove it from the ABC_FREE variables // remove it from the free variables
if ( Vec_IntSize(p->vFreeVars) > 0 ) if ( Vec_IntSize(p->vFreeVars) > 0 )
{ {
assert( p->pfPartVars[iReg] ); assert( p->pfPartVars[iReg] );
@ -218,7 +221,7 @@ void Aig_ManRegPartitionAdd( Aig_ManPre_t * p, int iReg )
p->pfPartVars[iReg] = 1; p->pfPartVars[iReg] = 1;
Vec_IntPush( p->vRegs, iReg ); Vec_IntPush( p->vRegs, iReg );
// add new variables // add new variables
vSupp = Vec_PtrEntry( p->vMatrix, iReg ); vSupp = (Vec_Int_t *)Vec_PtrEntry( p->vMatrix, iReg );
Vec_IntForEachEntry( vSupp, iVar, i ) Vec_IntForEachEntry( vSupp, iVar, i )
{ {
if ( p->pfPartVars[iVar] ) if ( p->pfPartVars[iVar] )
@ -253,7 +256,7 @@ Vec_Ptr_t * Aig_ManRegProjectOnehots( Aig_Man_t * pAig, Aig_Man_t * pPart, Vec_P
pObj->iData = i; pObj->iData = i;
// go through each group and check if registers are involved in this one // go through each group and check if registers are involved in this one
nOffset = Aig_ManPiNum(pAig)-Aig_ManRegNum(pAig); nOffset = Aig_ManPiNum(pAig)-Aig_ManRegNum(pAig);
Vec_PtrForEachEntry( vOnehots, vGroup, i ) Vec_PtrForEachEntry( Vec_Int_t *, vOnehots, vGroup, i )
{ {
vGroupNew = NULL; vGroupNew = NULL;
Vec_IntForEachEntry( vGroup, iReg, k ) Vec_IntForEachEntry( vGroup, iReg, k )
@ -263,7 +266,7 @@ Vec_Ptr_t * Aig_ManRegProjectOnehots( Aig_Man_t * pAig, Aig_Man_t * pPart, Vec_P
continue; continue;
if ( vGroupNew == NULL ) if ( vGroupNew == NULL )
vGroupNew = Vec_IntAlloc( Vec_IntSize(vGroup) ); vGroupNew = Vec_IntAlloc( Vec_IntSize(vGroup) );
pObjNew = pObj->pData; pObjNew = (Aig_Obj_t *)pObj->pData;
Vec_IntPush( vGroupNew, pObjNew->iData ); Vec_IntPush( vGroupNew, pObjNew->iData );
} }
if ( vGroupNew == NULL ) if ( vGroupNew == NULL )
@ -284,7 +287,7 @@ Vec_Ptr_t * Aig_ManRegProjectOnehots( Aig_Man_t * pAig, Aig_Man_t * pPart, Vec_P
if ( vOnehotsPart && fVerbose ) if ( vOnehotsPart && fVerbose )
{ {
printf( "Partition contains %d groups of 1-hot registers: { ", Vec_PtrSize(vOnehotsPart) ); printf( "Partition contains %d groups of 1-hot registers: { ", Vec_PtrSize(vOnehotsPart) );
Vec_PtrForEachEntry( vOnehotsPart, vGroup, k ) Vec_PtrForEachEntry( Vec_Int_t *, vOnehotsPart, vGroup, k )
printf( "%d ", Vec_IntSize(vGroup) ); printf( "%d ", Vec_IntSize(vGroup) );
printf( "}\n" ); printf( "}\n" );
} }
@ -354,11 +357,11 @@ Aig_Man_t * Aig_ManRegCreatePart( Aig_Man_t * pAig, Vec_Int_t * vPart, int * pnC
{ {
pObj = Aig_ManPi(pAig, nOffset+iOut); pObj = Aig_ManPi(pAig, nOffset+iOut);
pObj->pData = Aig_ObjCreatePi(pNew); pObj->pData = Aig_ObjCreatePi(pNew);
Aig_ObjCreatePo( pNew, pObj->pData ); Aig_ObjCreatePo( pNew, (Aig_Obj_t *)pObj->pData );
Aig_ObjSetTravIdCurrent( pAig, pObj ); // added Aig_ObjSetTravIdCurrent( pAig, pObj ); // added
} }
// create the nodes // create the nodes
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
if ( Aig_ObjIsNode(pObj) ) if ( Aig_ObjIsNode(pObj) )
pObj->pData = Aig_And(pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) ); pObj->pData = Aig_And(pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
// add real POs for the registers // add real POs for the registers
@ -377,9 +380,9 @@ Aig_Man_t * Aig_ManRegCreatePart( Aig_Man_t * pAig, Vec_Int_t * vPart, int * pnC
// map constant nodes // map constant nodes
pMapBack[0] = 0; pMapBack[0] = 0;
// logic cones of register outputs // logic cones of register outputs
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
{ {
pObjNew = Aig_Regular(pObj->pData); pObjNew = Aig_Regular((Aig_Obj_t *)pObj->pData);
pMapBack[pObjNew->Id] = pObj->Id; pMapBack[pObjNew->Id] = pObj->Id;
} }
// map register outputs // map register outputs
@ -387,7 +390,7 @@ Aig_Man_t * Aig_ManRegCreatePart( Aig_Man_t * pAig, Vec_Int_t * vPart, int * pnC
Vec_IntForEachEntry( vPart, iOut, i ) Vec_IntForEachEntry( vPart, iOut, i )
{ {
pObj = Aig_ManPi(pAig, nOffset+iOut); pObj = Aig_ManPi(pAig, nOffset+iOut);
pObjNew = pObj->pData; pObjNew = (Aig_Obj_t *)pObj->pData;
pMapBack[pObjNew->Id] = pObj->Id; pMapBack[pObjNew->Id] = pObj->Id;
} }
*ppMapBack = pMapBack; *ppMapBack = pMapBack;
@ -441,7 +444,7 @@ Vec_Ptr_t * Aig_ManRegPartitionSmart( Aig_Man_t * pAig, int nPartSize )
//printf( "Part %3d Reg %3d : Free = %4d. Total = %4d. Ratio = %6.2f. Unique = %4d.\n", i, k, //printf( "Part %3d Reg %3d : Free = %4d. Total = %4d. Ratio = %6.2f. Unique = %4d.\n", i, k,
// Vec_IntSize(p->vFreeVars), Vec_IntSize(p->vRegs), // Vec_IntSize(p->vFreeVars), Vec_IntSize(p->vRegs),
// 1.0*Vec_IntSize(p->vFreeVars)/Vec_IntSize(p->vRegs), Vec_IntSize(p->vUniques) ); // 1.0*Vec_IntSize(p->vFreeVars)/Vec_IntSize(p->vRegs), Vec_IntSize(p->vUniques) );
// quit if there are not ABC_FREE variables // quit if there are not free variables
if ( Vec_IntSize(p->vFreeVars) == 0 ) if ( Vec_IntSize(p->vFreeVars) == 0 )
break; break;
} }
@ -622,3 +625,5 @@ Vec_Ptr_t * Aig_ManRegPartitionLinear( Aig_Man_t * pAig, int nPartSize )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

35
src/aig/aig/aigPartSat.c
View File

@ -22,6 +22,9 @@
#include "satSolver.h" #include "satSolver.h"
#include "cnf.h" #include "cnf.h"
ABC_NAMESPACE_IMPL_START
/* /*
The node partitioners defined in this file return array of intergers The node partitioners defined in this file return array of intergers
@ -80,7 +83,7 @@ Vec_Int_t * Aig_ManPartitionLevelized( Aig_Man_t * p, int nPartSize )
int i, k, Counter = 0; int i, k, Counter = 0;
vNodes = Aig_ManLevelize( p ); vNodes = Aig_ManLevelize( p );
vId2Part = Vec_IntStart( Aig_ManObjNumMax(p) ); vId2Part = Vec_IntStart( Aig_ManObjNumMax(p) );
Vec_VecForEachEntryReverseReverse( vNodes, pObj, i, k ) Vec_VecForEachEntryReverseReverse( Aig_Obj_t *, vNodes, pObj, i, k )
Vec_IntWriteEntry( vId2Part, Aig_ObjId(pObj), Counter++/nPartSize ); Vec_IntWriteEntry( vId2Part, Aig_ObjId(pObj), Counter++/nPartSize );
Vec_VecFree( vNodes ); Vec_VecFree( vNodes );
return vId2Part; return vId2Part;
@ -107,13 +110,13 @@ Vec_Int_t * Aig_ManPartitionDfs( Aig_Man_t * p, int nPartSize, int fPreorder )
if ( fPreorder ) if ( fPreorder )
{ {
vNodes = Aig_ManDfsPreorder( p, 1 ); vNodes = Aig_ManDfsPreorder( p, 1 );
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
Vec_IntWriteEntry( vId2Part, Aig_ObjId(pObj), Counter++/nPartSize ); Vec_IntWriteEntry( vId2Part, Aig_ObjId(pObj), Counter++/nPartSize );
} }
else else
{ {
vNodes = Aig_ManDfs( p, 1 ); vNodes = Aig_ManDfs( p, 1 );
Vec_PtrForEachEntryReverse( vNodes, pObj, i ) Vec_PtrForEachEntryReverse( Aig_Obj_t *, vNodes, pObj, i )
Vec_IntWriteEntry( vId2Part, Aig_ObjId(pObj), Counter++/nPartSize ); Vec_IntWriteEntry( vId2Part, Aig_ObjId(pObj), Counter++/nPartSize );
} }
Vec_PtrFree( vNodes ); Vec_PtrFree( vNodes );
@ -179,7 +182,7 @@ Aig_Man_t * Aig_ManPartSplitOne( Aig_Man_t * p, Vec_Ptr_t * vNodes, Vec_Int_t **
int i; int i;
// mark these nodes // mark these nodes
Aig_ManIncrementTravId( p ); Aig_ManIncrementTravId( p );
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
{ {
Aig_ObjSetTravIdCurrent( p, pObj ); Aig_ObjSetTravIdCurrent( p, pObj );
pObj->pData = NULL; pObj->pData = NULL;
@ -187,14 +190,14 @@ Aig_Man_t * Aig_ManPartSplitOne( Aig_Man_t * p, Vec_Ptr_t * vNodes, Vec_Int_t **
// add these nodes in a DFS order // add these nodes in a DFS order
pNew = Aig_ManStart( Vec_PtrSize(vNodes) ); pNew = Aig_ManStart( Vec_PtrSize(vNodes) );
vPio2Id = Vec_IntAlloc( 100 ); vPio2Id = Vec_IntAlloc( 100 );
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
Aig_ManPartSplitOne_rec( pNew, p, pObj, vPio2Id ); Aig_ManPartSplitOne_rec( pNew, p, pObj, vPio2Id );
// add the POs // add the POs
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
if ( Aig_ObjRefs(pObj->pData) != Aig_ObjRefs(pObj) ) if ( Aig_ObjRefs((Aig_Obj_t *)pObj->pData) != Aig_ObjRefs(pObj) )
{ {
assert( Aig_ObjRefs(pObj->pData) < Aig_ObjRefs(pObj) ); assert( Aig_ObjRefs((Aig_Obj_t *)pObj->pData) < Aig_ObjRefs(pObj) );
Aig_ObjCreatePo( pNew, pObj->pData ); Aig_ObjCreatePo( pNew, (Aig_Obj_t *)pObj->pData );
Vec_IntPush( vPio2Id, Aig_ObjId(pObj) ); Vec_IntPush( vPio2Id, Aig_ObjId(pObj) );
} }
assert( Aig_ManNodeNum(pNew) == Vec_PtrSize(vNodes) ); assert( Aig_ManNodeNum(pNew) == Vec_PtrSize(vNodes) );
@ -440,7 +443,7 @@ int Aig_ManAddNewCnfToSolver( sat_solver * pSat, Aig_Man_t * pAig, Vec_Int_t * v
// remove the CNF // remove the CNF
Cnf_DataFree( pCnf ); Cnf_DataFree( pCnf );
// constrain the solver with the literals corresponding to the original POs // constrain the solver with the literals corresponding to the original POs
Vec_PtrForEachEntry( vPartPos, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vPartPos, pObj, i )
{ {
iNodeIdOld = Aig_ObjFaninId0( pObj ); iNodeIdOld = Aig_ObjFaninId0( pObj );
iSatVarOld = Vec_IntEntry( vNode2Var, iNodeIdOld ); iSatVarOld = Vec_IntEntry( vNode2Var, iNodeIdOld );
@ -537,7 +540,7 @@ int Aig_ManPartitionedSat( Aig_Man_t * p, int nAlgo, int nPartSize,
// synthesize partitions // synthesize partitions
if ( fSynthesize ) if ( fSynthesize )
Vec_PtrForEachEntry( vAigs, pAig, i ) Vec_PtrForEachEntry( Aig_Man_t *, vAigs, pAig, i )
{ {
pAig = Dar_ManRwsat( pTemp = pAig, 0, 0 ); pAig = Dar_ManRwsat( pTemp = pAig, 0, 0 );
Vec_PtrWriteEntry( vAigs, i, pAig ); Vec_PtrWriteEntry( vAigs, i, pAig );
@ -551,17 +554,17 @@ int Aig_ManPartitionedSat( Aig_Man_t * p, int nAlgo, int nPartSize,
vNode2Var = Vec_IntStart( Aig_ManObjNumMax(p) ); vNode2Var = Vec_IntStart( Aig_ManObjNumMax(p) );
// add partitions, one at a time, and run the SAT solver // add partitions, one at a time, and run the SAT solver
Vec_PtrForEachEntry( vAigs, pAig, i ) Vec_PtrForEachEntry( Aig_Man_t *, vAigs, pAig, i )
{ {
clk = clock(); clk = clock();
// transform polarity of the AIG // transform polarity of the AIG
if ( fAlignPol ) if ( fAlignPol )
Aig_ManPartSetNodePolarity( p, pAig, Vec_VecEntry(vPio2Id,i) ); Aig_ManPartSetNodePolarity( p, pAig, (Vec_Int_t *)Vec_VecEntry(vPio2Id,i) );
else else
Aig_ManPartResetNodePolarity( pAig ); Aig_ManPartResetNodePolarity( pAig );
// add CNF of this partition to the SAT solver // add CNF of this partition to the SAT solver
if ( Aig_ManAddNewCnfToSolver( pSat, pAig, vNode2Var, if ( Aig_ManAddNewCnfToSolver( pSat, pAig, vNode2Var,
Vec_VecEntry(vPio2Id,i), Vec_VecEntry(vPart2Pos,i), fAlignPol ) ) (Vec_Int_t *)Vec_VecEntry(vPio2Id,i), (Vec_Ptr_t *)Vec_VecEntry(vPart2Pos,i), fAlignPol ) )
{ {
RetValue = 1; RetValue = 1;
break; break;
@ -596,7 +599,7 @@ ABC_PRT( "Time", clock() - clk );
Aig_ManDeriveCounterExample( p, vNode2Var, pSat ); Aig_ManDeriveCounterExample( p, vNode2Var, pSat );
// cleanup // cleanup
sat_solver_delete( pSat ); sat_solver_delete( pSat );
Vec_PtrForEachEntry( vAigs, pTemp, i ) Vec_PtrForEachEntry( Aig_Man_t *, vAigs, pTemp, i )
Aig_ManStop( pTemp ); Aig_ManStop( pTemp );
Vec_PtrFree( vAigs ); Vec_PtrFree( vAigs );
Vec_VecFree( vPio2Id ); Vec_VecFree( vPio2Id );
@ -610,3 +613,5 @@ ABC_PRT( "Time", clock() - clk );
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

20
src/aig/aig/aigRepr.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -188,8 +191,8 @@ static inline Aig_Obj_t * Aig_ObjGetRepr( Aig_Man_t * p, Aig_Obj_t * pObj )
{ {
Aig_Obj_t * pRepr; Aig_Obj_t * pRepr;
if ( (pRepr = Aig_ObjFindRepr(p, pObj)) ) if ( (pRepr = Aig_ObjFindRepr(p, pObj)) )
return Aig_NotCond( pRepr->pData, pObj->fPhase ^ pRepr->fPhase ); return Aig_NotCond( (Aig_Obj_t *)pRepr->pData, pObj->fPhase ^ pRepr->fPhase );
return pObj->pData; return (Aig_Obj_t *)pObj->pData;
} }
static inline Aig_Obj_t * Aig_ObjChild0Repr( Aig_Man_t * p, Aig_Obj_t * pObj ) { return Aig_NotCond( Aig_ObjGetRepr(p, Aig_ObjFanin0(pObj)), Aig_ObjFaninC0(pObj) ); } static inline Aig_Obj_t * Aig_ObjChild0Repr( Aig_Man_t * p, Aig_Obj_t * pObj ) { return Aig_NotCond( Aig_ObjGetRepr(p, Aig_ObjFanin0(pObj)), Aig_ObjFaninC0(pObj) ); }
static inline Aig_Obj_t * Aig_ObjChild1Repr( Aig_Man_t * p, Aig_Obj_t * pObj ) { return Aig_NotCond( Aig_ObjGetRepr(p, Aig_ObjFanin1(pObj)), Aig_ObjFaninC1(pObj) ); } static inline Aig_Obj_t * Aig_ObjChild1Repr( Aig_Man_t * p, Aig_Obj_t * pObj ) { return Aig_NotCond( Aig_ObjGetRepr(p, Aig_ObjFanin1(pObj)), Aig_ObjFaninC1(pObj) ); }
@ -221,7 +224,7 @@ void Aig_ManTransferRepr( Aig_Man_t * pNew, Aig_Man_t * pOld )
// go through the nodes which have representatives // go through the nodes which have representatives
Aig_ManForEachObj( pOld, pObj, k ) Aig_ManForEachObj( pOld, pObj, k )
if ( (pRepr = Aig_ObjFindRepr(pOld, pObj)) ) if ( (pRepr = Aig_ObjFindRepr(pOld, pObj)) )
Aig_ObjSetRepr_( pNew, Aig_Regular(pRepr->pData), Aig_Regular(pObj->pData) ); Aig_ObjSetRepr_( pNew, Aig_Regular((Aig_Obj_t *)pRepr->pData), Aig_Regular((Aig_Obj_t *)pObj->pData) );
} }
/**Function************************************************************* /**Function*************************************************************
@ -239,15 +242,15 @@ Aig_Obj_t * Aig_ManDupRepr_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t * pOb
{ {
Aig_Obj_t * pRepr; Aig_Obj_t * pRepr;
if ( pObj->pData ) if ( pObj->pData )
return pObj->pData; return (Aig_Obj_t *)pObj->pData;
if ( (pRepr = Aig_ObjFindRepr(p, pObj)) ) if ( (pRepr = Aig_ObjFindRepr(p, pObj)) )
{ {
Aig_ManDupRepr_rec( pNew, p, pRepr ); Aig_ManDupRepr_rec( pNew, p, pRepr );
return pObj->pData = Aig_NotCond( pRepr->pData, pRepr->fPhase ^ pObj->fPhase ); return (Aig_Obj_t *)(pObj->pData = Aig_NotCond( (Aig_Obj_t *)pRepr->pData, pRepr->fPhase ^ pObj->fPhase ));
} }
Aig_ManDupRepr_rec( pNew, p, Aig_ObjFanin0(pObj) ); Aig_ManDupRepr_rec( pNew, p, Aig_ObjFanin0(pObj) );
Aig_ManDupRepr_rec( pNew, p, Aig_ObjFanin1(pObj) ); Aig_ManDupRepr_rec( pNew, p, Aig_ObjFanin1(pObj) );
return pObj->pData = Aig_And( pNew, Aig_ObjChild0Repr(p, pObj), Aig_ObjChild1Repr(p, pObj) ); return (Aig_Obj_t *)(pObj->pData = Aig_And( pNew, Aig_ObjChild0Repr(p, pObj), Aig_ObjChild1Repr(p, pObj) ));
} }
/**Function************************************************************* /**Function*************************************************************
@ -270,6 +273,7 @@ Aig_Man_t * Aig_ManDupRepr( Aig_Man_t * p, int fOrdered )
pNew = Aig_ManStart( Aig_ManObjNumMax(p) ); pNew = Aig_ManStart( Aig_ManObjNumMax(p) );
pNew->pName = Aig_UtilStrsav( p->pName ); pNew->pName = Aig_UtilStrsav( p->pName );
pNew->pSpec = Aig_UtilStrsav( p->pSpec ); pNew->pSpec = Aig_UtilStrsav( p->pSpec );
pNew->nConstrs = p->nConstrs;
if ( p->vFlopNums ) if ( p->vFlopNums )
pNew->vFlopNums = Vec_IntDup( p->vFlopNums ); pNew->vFlopNums = Vec_IntDup( p->vFlopNums );
// map the const and primary inputs // map the const and primary inputs
@ -327,7 +331,7 @@ Aig_Man_t * Aig_ManDupReprBasic( Aig_Man_t * p )
Aig_ManSeqCleanupBasic( pNew ); Aig_ManSeqCleanupBasic( pNew );
// remove pointers to the dead nodes // remove pointers to the dead nodes
Aig_ManForEachObj( p, pObj, i ) Aig_ManForEachObj( p, pObj, i )
if ( pObj->pData && Aig_ObjIsNone(pObj->pData) ) if ( pObj->pData && Aig_ObjIsNone((Aig_Obj_t *)pObj->pData) )
pObj->pData = NULL; pObj->pData = NULL;
return pNew; return pNew;
} }
@ -550,3 +554,5 @@ int Aig_TransferMappedClasses( Aig_Man_t * pAig, Aig_Man_t * pPart, int * pMapBa
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

71
src/aig/aig/aigRet.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -76,28 +79,28 @@ static inline Rtm_Obj_t * Rtm_ObjFanout( Rtm_Obj_t * pObj, int i ) { retur
static inline Rtm_Edg_t * Rtm_ObjEdge( Rtm_Obj_t * pObj, int i ) { return (Rtm_Edg_t *)(pObj->pFanio + 2*i + 1); } static inline Rtm_Edg_t * Rtm_ObjEdge( Rtm_Obj_t * pObj, int i ) { return (Rtm_Edg_t *)(pObj->pFanio + 2*i + 1); }
static inline Rtm_Edg_t * Rtm_ObjFanoutEdge( Rtm_Obj_t * pObj, int i ) { return (Rtm_Edg_t *)pObj->pFanio[2*(pObj->nFanins+i) + 1]; } static inline Rtm_Edg_t * Rtm_ObjFanoutEdge( Rtm_Obj_t * pObj, int i ) { return (Rtm_Edg_t *)pObj->pFanio[2*(pObj->nFanins+i) + 1]; }
static inline Rtm_Init_t Rtm_InitNot( Rtm_Init_t Val ) { if ( Val == RTM_VAL_ZERO ) return RTM_VAL_ONE; if ( Val == RTM_VAL_ONE ) return RTM_VAL_ZERO; assert( 0 ); return -1; } static inline Rtm_Init_t Rtm_InitNot( Rtm_Init_t Val ) { if ( Val == RTM_VAL_ZERO ) return (Rtm_Init_t)RTM_VAL_ONE; if ( Val == RTM_VAL_ONE ) return (Rtm_Init_t)RTM_VAL_ZERO; assert( 0 ); return (Rtm_Init_t)-1; }
static inline Rtm_Init_t Rtm_InitNotCond( Rtm_Init_t Val, int c ) { return c ? Rtm_InitNot(Val) : Val; } static inline Rtm_Init_t Rtm_InitNotCond( Rtm_Init_t Val, int c ) { return c ? Rtm_InitNot(Val) : Val; }
static inline Rtm_Init_t Rtm_InitAnd(Rtm_Init_t ValA, Rtm_Init_t ValB ) { if ( ValA == RTM_VAL_ONE && ValB == RTM_VAL_ONE ) return RTM_VAL_ONE; if ( ValA == RTM_VAL_ZERO || ValB == RTM_VAL_ZERO ) return RTM_VAL_ZERO; assert( 0 ); return -1; } static inline Rtm_Init_t Rtm_InitAnd(Rtm_Init_t ValA, Rtm_Init_t ValB ) { if ( ValA == RTM_VAL_ONE && ValB == RTM_VAL_ONE ) return (Rtm_Init_t)RTM_VAL_ONE; if ( ValA == RTM_VAL_ZERO || ValB == RTM_VAL_ZERO ) return (Rtm_Init_t)RTM_VAL_ZERO; assert( 0 ); return (Rtm_Init_t)-1; }
static inline int Rtm_InitWordsNum( int nLats ) { return (nLats >> 4) + ((nLats & 15) > 0); } static inline int Rtm_InitWordsNum( int nLats ) { return (nLats >> 4) + ((nLats & 15) > 0); }
static inline int Rtm_InitGetTwo( unsigned * p, int i ) { return (p[i>>4] >> ((i & 15)<<1)) & 3; } static inline int Rtm_InitGetTwo( unsigned * p, int i ) { return (p[i>>4] >> ((i & 15)<<1)) & 3; }
static inline void Rtm_InitSetTwo( unsigned * p, int i, int val ) { p[i>>4] |= (val << ((i & 15)<<1)); } static inline void Rtm_InitSetTwo( unsigned * p, int i, int val ) { p[i>>4] |= (val << ((i & 15)<<1)); }
static inline void Rtm_InitXorTwo( unsigned * p, int i, int val ) { p[i>>4] ^= (val << ((i & 15)<<1)); } static inline void Rtm_InitXorTwo( unsigned * p, int i, int val ) { p[i>>4] ^= (val << ((i & 15)<<1)); }
static inline Rtm_Init_t Rtm_ObjGetFirst1( Rtm_Edg_t * pEdge ) { return pEdge->LData & 3; } static inline Rtm_Init_t Rtm_ObjGetFirst1( Rtm_Edg_t * pEdge ) { return (Rtm_Init_t)(pEdge->LData & 3); }
static inline Rtm_Init_t Rtm_ObjGetLast1( Rtm_Edg_t * pEdge ) { return (pEdge->LData >> ((pEdge->nLats-1)<<1)) & 3; } static inline Rtm_Init_t Rtm_ObjGetLast1( Rtm_Edg_t * pEdge ) { return (Rtm_Init_t)((pEdge->LData >> ((pEdge->nLats-1)<<1)) & 3); }
static inline Rtm_Init_t Rtm_ObjGetOne1( Rtm_Edg_t * pEdge, int i ) { assert( i < (int)pEdge->nLats ); return (pEdge->LData >> (i << 1)) & 3; } static inline Rtm_Init_t Rtm_ObjGetOne1( Rtm_Edg_t * pEdge, int i ) { assert( i < (int)pEdge->nLats ); return (Rtm_Init_t)((pEdge->LData >> (i << 1)) & 3); }
static inline Rtm_Init_t Rtm_ObjRemFirst1( Rtm_Edg_t * pEdge ) { int Val = pEdge->LData & 3; pEdge->LData >>= 2; assert(pEdge->nLats > 0); pEdge->nLats--; return Val; } static inline Rtm_Init_t Rtm_ObjRemFirst1( Rtm_Edg_t * pEdge ) { int Val = pEdge->LData & 3; pEdge->LData >>= 2; assert(pEdge->nLats > 0); pEdge->nLats--; return (Rtm_Init_t)Val; }
static inline Rtm_Init_t Rtm_ObjRemLast1( Rtm_Edg_t * pEdge ) { int Val = (pEdge->LData >> ((pEdge->nLats-1)<<1)) & 3; pEdge->LData ^= Val << ((pEdge->nLats-1)<<1); assert(pEdge->nLats > 0); pEdge->nLats--; return Val; } static inline Rtm_Init_t Rtm_ObjRemLast1( Rtm_Edg_t * pEdge ) { int Val = (pEdge->LData >> ((pEdge->nLats-1)<<1)) & 3; pEdge->LData ^= Val << ((pEdge->nLats-1)<<1); assert(pEdge->nLats > 0); pEdge->nLats--; return (Rtm_Init_t)Val; }
static inline void Rtm_ObjAddFirst1( Rtm_Edg_t * pEdge, Rtm_Init_t Val ) { assert( Val > 0 && Val < 4 ); pEdge->LData = (pEdge->LData << 2) | Val; pEdge->nLats++; } static inline void Rtm_ObjAddFirst1( Rtm_Edg_t * pEdge, Rtm_Init_t Val ) { assert( Val > 0 && Val < 4 ); pEdge->LData = (pEdge->LData << 2) | Val; pEdge->nLats++; }
static inline void Rtm_ObjAddLast1( Rtm_Edg_t * pEdge, Rtm_Init_t Val ) { assert( Val > 0 && Val < 4 ); pEdge->LData |= Val << (pEdge->nLats<<1); pEdge->nLats++; } static inline void Rtm_ObjAddLast1( Rtm_Edg_t * pEdge, Rtm_Init_t Val ) { assert( Val > 0 && Val < 4 ); pEdge->LData |= Val << (pEdge->nLats<<1); pEdge->nLats++; }
static inline Rtm_Init_t Rtm_ObjGetFirst2( Rtm_Man_t * p, Rtm_Edg_t * pEdge ) { return Rtm_InitGetTwo( p->pExtra + pEdge->LData, 0 ); } static inline Rtm_Init_t Rtm_ObjGetFirst2( Rtm_Man_t * p, Rtm_Edg_t * pEdge ) { return (Rtm_Init_t)Rtm_InitGetTwo( p->pExtra + pEdge->LData, 0 ); }
static inline Rtm_Init_t Rtm_ObjGetLast2( Rtm_Man_t * p, Rtm_Edg_t * pEdge ) { return Rtm_InitGetTwo( p->pExtra + pEdge->LData, pEdge->nLats - 1 ); } static inline Rtm_Init_t Rtm_ObjGetLast2( Rtm_Man_t * p, Rtm_Edg_t * pEdge ) { return (Rtm_Init_t)Rtm_InitGetTwo( p->pExtra + pEdge->LData, pEdge->nLats - 1 ); }
static inline Rtm_Init_t Rtm_ObjGetOne2( Rtm_Man_t * p, Rtm_Edg_t * pEdge, int i ) { return Rtm_InitGetTwo( p->pExtra + pEdge->LData, i ); } static inline Rtm_Init_t Rtm_ObjGetOne2( Rtm_Man_t * p, Rtm_Edg_t * pEdge, int i ) { return (Rtm_Init_t)Rtm_InitGetTwo( p->pExtra + pEdge->LData, i ); }
static Rtm_Init_t Rtm_ObjRemFirst2( Rtm_Man_t * p, Rtm_Edg_t * pEdge ); static Rtm_Init_t Rtm_ObjRemFirst2( Rtm_Man_t * p, Rtm_Edg_t * pEdge );
static inline Rtm_Init_t Rtm_ObjRemLast2( Rtm_Man_t * p, Rtm_Edg_t * pEdge ) { Rtm_Init_t Val = Rtm_ObjGetLast2( p, pEdge ); Rtm_InitXorTwo( p->pExtra + pEdge->LData, pEdge->nLats - 1, Val ); pEdge->nLats--; return Val; } static inline Rtm_Init_t Rtm_ObjRemLast2( Rtm_Man_t * p, Rtm_Edg_t * pEdge ) { Rtm_Init_t Val = Rtm_ObjGetLast2( p, pEdge ); Rtm_InitXorTwo( p->pExtra + pEdge->LData, pEdge->nLats - 1, Val ); pEdge->nLats--; return (Rtm_Init_t)Val; }
static void Rtm_ObjAddFirst2( Rtm_Man_t * p, Rtm_Edg_t * pEdge, Rtm_Init_t Val ); static void Rtm_ObjAddFirst2( Rtm_Man_t * p, Rtm_Edg_t * pEdge, Rtm_Init_t Val );
static inline void Rtm_ObjAddLast2( Rtm_Man_t * p, Rtm_Edg_t * pEdge, Rtm_Init_t Val ) { Rtm_InitSetTwo( p->pExtra + pEdge->LData, pEdge->nLats, Val ); pEdge->nLats++; } static inline void Rtm_ObjAddLast2( Rtm_Man_t * p, Rtm_Edg_t * pEdge, Rtm_Init_t Val ) { Rtm_InitSetTwo( p->pExtra + pEdge->LData, pEdge->nLats, Val ); pEdge->nLats++; }
@ -116,13 +119,13 @@ static void Rtm_ObjAddLast( Rtm_Man_t * p, Rtm_Edg_t * pEdge, Rtm_
// iterator over the primary inputs // iterator over the primary inputs
#define Rtm_ManForEachPi( p, pObj, i ) \ #define Rtm_ManForEachPi( p, pObj, i ) \
Vec_PtrForEachEntry( p->vPis, pObj, i ) Vec_PtrForEachEntry( Rtm_Obj_t *, p->vPis, pObj, i )
// iterator over the primary outputs // iterator over the primary outputs
#define Rtm_ManForEachPo( p, pObj, i ) \ #define Rtm_ManForEachPo( p, pObj, i ) \
Vec_PtrForEachEntry( p->vPos, pObj, i ) Vec_PtrForEachEntry( Rtm_Obj_t *, p->vPos, pObj, i )
// iterator over all objects, including those currently not used // iterator over all objects, including those currently not used
#define Rtm_ManForEachObj( p, pObj, i ) \ #define Rtm_ManForEachObj( p, pObj, i ) \
Vec_PtrForEachEntry( p->vObjs, pObj, i ) Vec_PtrForEachEntry( Rtm_Obj_t *, p->vObjs, pObj, i )
// iterate through the fanins // iterate through the fanins
#define Rtm_ObjForEachFanin( pObj, pFanin, i ) \ #define Rtm_ObjForEachFanin( pObj, pFanin, i ) \
for ( i = 0; i < (int)(pObj)->nFanins && ((pFanin = Rtm_ObjFanin(pObj, i)), 1); i++ ) for ( i = 0; i < (int)(pObj)->nFanins && ((pFanin = Rtm_ObjFanin(pObj, i)), 1); i++ )
@ -222,11 +225,11 @@ void Rtm_ObjTransferToBigger( Rtm_Man_t * p, Rtm_Edg_t * pEdge )
***********************************************************************/ ***********************************************************************/
Rtm_Init_t Rtm_ObjRemFirst2( Rtm_Man_t * p, Rtm_Edg_t * pEdge ) Rtm_Init_t Rtm_ObjRemFirst2( Rtm_Man_t * p, Rtm_Edg_t * pEdge )
{ {
Rtm_Init_t Val = 0, Temp; Rtm_Init_t Val = (Rtm_Init_t)0, Temp;
unsigned * pB = p->pExtra + pEdge->LData, * pE = pB + Rtm_InitWordsNum( pEdge->nLats-- ) - 1; unsigned * pB = p->pExtra + pEdge->LData, * pE = pB + Rtm_InitWordsNum( pEdge->nLats-- ) - 1;
while ( pE >= pB ) while ( pE >= pB )
{ {
Temp = *pE & 3; Temp = (Rtm_Init_t)(*pE & 3);
*pE = (*pE >> 2) | (Val << 30); *pE = (*pE >> 2) | (Val << 30);
Val = Temp; Val = Temp;
pE--; pE--;
@ -253,7 +256,7 @@ void Rtm_ObjAddFirst2( Rtm_Man_t * p, Rtm_Edg_t * pEdge, Rtm_Init_t Val )
assert( Val != 0 ); assert( Val != 0 );
while ( pB < pE ) while ( pB < pE )
{ {
Temp = *pB >> 30; Temp = (Rtm_Init_t)(*pB >> 30);
*pB = (*pB << 2) | Val; *pB = (*pB << 2) | Val;
Val = Temp; Val = Temp;
pB++; pB++;
@ -590,7 +593,7 @@ int Rtm_ManMarkAutoFwd( Rtm_Man_t * pRtm )
Rtm_Obj_t * pObjRtm; Rtm_Obj_t * pObjRtm;
int i, Counter = 0; int i, Counter = 0;
// mark nodes reachable from the PIs // mark nodes reachable from the PIs
pObjRtm = Vec_PtrEntry( pRtm->vObjs, 0 ); pObjRtm = (Rtm_Obj_t *)Vec_PtrEntry( pRtm->vObjs, 0 );
Rtm_ObjMarkAutoFwd_rec( pObjRtm ); Rtm_ObjMarkAutoFwd_rec( pObjRtm );
Rtm_ManForEachPi( pRtm, pObjRtm, i ) Rtm_ManForEachPi( pRtm, pObjRtm, i )
Rtm_ObjMarkAutoFwd_rec( pObjRtm ); Rtm_ObjMarkAutoFwd_rec( pObjRtm );
@ -642,7 +645,7 @@ int Rtm_ManMarkAutoBwd( Rtm_Man_t * pRtm )
Rtm_Obj_t * pObjRtm; Rtm_Obj_t * pObjRtm;
int i, Counter = 0; int i, Counter = 0;
// mark nodes reachable from the PIs // mark nodes reachable from the PIs
pObjRtm = Vec_PtrEntry( pRtm->vObjs, 0 ); pObjRtm = (Rtm_Obj_t *)Vec_PtrEntry( pRtm->vObjs, 0 );
pObjRtm->fAuto = 1; pObjRtm->fAuto = 1;
Rtm_ManForEachPi( pRtm, pObjRtm, i ) Rtm_ManForEachPi( pRtm, pObjRtm, i )
pObjRtm->fAuto = 1; pObjRtm->fAuto = 1;
@ -699,15 +702,15 @@ Rtm_Man_t * Rtm_ManFromAig( Aig_Man_t * p )
pObj->pData = Rtm_ObjAlloc( pRtm, 2, pObj->nRefs ); pObj->pData = Rtm_ObjAlloc( pRtm, 2, pObj->nRefs );
// connect objects // connect objects
Aig_ManForEachPoSeq( p, pObj, i ) Aig_ManForEachPoSeq( p, pObj, i )
Rtm_ObjAddFanin( pObj->pData, Aig_ObjFanin0(pObj)->pData, Aig_ObjFaninC0(pObj) ); Rtm_ObjAddFanin( (Rtm_Obj_t *)pObj->pData, (Rtm_Obj_t *)Aig_ObjFanin0(pObj)->pData, Aig_ObjFaninC0(pObj) );
Aig_ManForEachLiSeq( p, pObj, i ) Aig_ManForEachLiSeq( p, pObj, i )
Rtm_ObjAddFanin( pObj->pData, Aig_ObjFanin0(pObj)->pData, Aig_ObjFaninC0(pObj) ); Rtm_ObjAddFanin( (Rtm_Obj_t *)pObj->pData, (Rtm_Obj_t *)Aig_ObjFanin0(pObj)->pData, Aig_ObjFaninC0(pObj) );
Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, i ) Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, i )
Rtm_ObjAddFanin( pObjLo->pData, pObjLi->pData, 0 ); Rtm_ObjAddFanin( (Rtm_Obj_t *)pObjLo->pData, (Rtm_Obj_t *)pObjLi->pData, 0 );
Aig_ManForEachNode( p, pObj, i ) Aig_ManForEachNode( p, pObj, i )
{ {
Rtm_ObjAddFanin( pObj->pData, Aig_ObjFanin0(pObj)->pData, Aig_ObjFaninC0(pObj) ); Rtm_ObjAddFanin( (Rtm_Obj_t *)pObj->pData, (Rtm_Obj_t *)Aig_ObjFanin0(pObj)->pData, Aig_ObjFaninC0(pObj) );
Rtm_ObjAddFanin( pObj->pData, Aig_ObjFanin1(pObj)->pData, Aig_ObjFaninC1(pObj) ); Rtm_ObjAddFanin( (Rtm_Obj_t *)pObj->pData, (Rtm_Obj_t *)Aig_ObjFanin1(pObj)->pData, Aig_ObjFaninC1(pObj) );
} }
return pRtm; return pRtm;
} }
@ -729,7 +732,7 @@ Aig_Obj_t * Rtm_ManToAig_rec( Aig_Man_t * pNew, Rtm_Man_t * pRtm, Rtm_Obj_t * pO
Aig_Obj_t * pRes, * pFanin; Aig_Obj_t * pRes, * pFanin;
int k, Val; int k, Val;
if ( pObjRtm->pCopy ) if ( pObjRtm->pCopy )
return pObjRtm->pCopy; return (Aig_Obj_t *)pObjRtm->pCopy;
// get the inputs // get the inputs
pRes = Aig_ManConst1( pNew ); pRes = Aig_ManConst1( pNew );
Rtm_ObjForEachFaninEdge( pObjRtm, pEdge, k ) Rtm_ObjForEachFaninEdge( pObjRtm, pEdge, k )
@ -745,7 +748,7 @@ Aig_Obj_t * Rtm_ManToAig_rec( Aig_Man_t * pNew, Rtm_Man_t * pRtm, Rtm_Obj_t * pO
pFanin = Aig_NotCond( pFanin, k ? pObjRtm->fCompl1 : pObjRtm->fCompl0 ); pFanin = Aig_NotCond( pFanin, k ? pObjRtm->fCompl1 : pObjRtm->fCompl0 );
pRes = Aig_And( pNew, pRes, pFanin ); pRes = Aig_And( pNew, pRes, pFanin );
} }
return pObjRtm->pCopy = pRes; return (Aig_Obj_t *)(pObjRtm->pCopy = pRes);
} }
/**Function************************************************************* /**Function*************************************************************
@ -778,7 +781,7 @@ Aig_Man_t * Rtm_ManToAig( Rtm_Man_t * pRtm )
// create the new manager // create the new manager
pNew = Aig_ManStart( Vec_PtrSize(pRtm->vObjs) + nLatches ); pNew = Aig_ManStart( Vec_PtrSize(pRtm->vObjs) + nLatches );
// create PIs/POs and latches // create PIs/POs and latches
pObjRtm = Vec_PtrEntry( pRtm->vObjs, 0 ); pObjRtm = (Rtm_Obj_t *)Vec_PtrEntry( pRtm->vObjs, 0 );
pObjRtm->pCopy = Aig_ManConst1(pNew); pObjRtm->pCopy = Aig_ManConst1(pNew);
Rtm_ManForEachPi( pRtm, pObjRtm, i ) Rtm_ManForEachPi( pRtm, pObjRtm, i )
pObjRtm->pCopy = Aig_ObjCreatePi(pNew); pObjRtm->pCopy = Aig_ObjCreatePi(pNew);
@ -789,14 +792,14 @@ Aig_Man_t * Rtm_ManToAig( Rtm_Man_t * pRtm )
Rtm_ManToAig_rec( pNew, pRtm, pObjRtm, pLatches ); Rtm_ManToAig_rec( pNew, pRtm, pObjRtm, pLatches );
// create POs // create POs
Rtm_ManForEachPo( pRtm, pObjRtm, i ) Rtm_ManForEachPo( pRtm, pObjRtm, i )
Aig_ObjCreatePo( pNew, pObjRtm->pCopy ); Aig_ObjCreatePo( pNew, (Aig_Obj_t *)pObjRtm->pCopy );
// connect latches // connect latches
Rtm_ManForEachObj( pRtm, pObjRtm, i ) Rtm_ManForEachObj( pRtm, pObjRtm, i )
Rtm_ObjForEachFaninEdge( pObjRtm, pEdge, k ) Rtm_ObjForEachFaninEdge( pObjRtm, pEdge, k )
{ {
if ( pEdge->nLats == 0 ) if ( pEdge->nLats == 0 )
continue; continue;
pObjNew = Rtm_ObjFanin( pObjRtm, k )->pCopy; pObjNew = (Aig_Obj_t *)Rtm_ObjFanin( pObjRtm, k )->pCopy;
for ( m = 0; m < (int)pEdge->nLats; m++ ) for ( m = 0; m < (int)pEdge->nLats; m++ )
{ {
Val = Rtm_ObjGetOne( pRtm, pEdge, pEdge->nLats - 1 - m ); Val = Rtm_ObjGetOne( pRtm, pEdge, pEdge->nLats - 1 - m );
@ -843,7 +846,7 @@ clk = clock();
pRtm = Rtm_ManFromAig( p ); pRtm = Rtm_ManFromAig( p );
// set registers // set registers
Aig_ManForEachLoSeq( p, pObjAig, i ) Aig_ManForEachLoSeq( p, pObjAig, i )
Rtm_ObjAddFirst( pRtm, Rtm_ObjEdge(pObjAig->pData, 0), fForward? RTM_VAL_ZERO : RTM_VAL_VOID ); Rtm_ObjAddFirst( pRtm, Rtm_ObjEdge((Rtm_Obj_t *)pObjAig->pData, 0), fForward? RTM_VAL_ZERO : RTM_VAL_VOID );
// detect and mark the autonomous components // detect and mark the autonomous components
if ( fForward ) if ( fForward )
nAutos = Rtm_ManMarkAutoFwd( pRtm ); nAutos = Rtm_ManMarkAutoFwd( pRtm );
@ -870,7 +873,7 @@ clk = clock();
{ {
Aig_ManForEachLoSeq( p, pObjAig, i ) Aig_ManForEachLoSeq( p, pObjAig, i )
{ {
pObj = pObjAig->pData; pObj = (Rtm_Obj_t *)pObjAig->pData;
if ( pObj->fAuto ) if ( pObj->fAuto )
continue; continue;
pObj->fMark = 1; pObj->fMark = 1;
@ -881,7 +884,7 @@ clk = clock();
{ {
Aig_ManForEachLiSeq( p, pObjAig, i ) Aig_ManForEachLiSeq( p, pObjAig, i )
{ {
pObj = pObjAig->pData; pObj = (Rtm_Obj_t *)pObjAig->pData;
if ( pObj->fAuto ) if ( pObj->fAuto )
continue; continue;
pObj->fMark = 1; pObj->fMark = 1;
@ -890,7 +893,7 @@ clk = clock();
} }
// perform retiming // perform retiming
DegreeMax = 0; DegreeMax = 0;
Vec_PtrForEachEntry( vQueue, pObj, i ) Vec_PtrForEachEntry( Rtm_Obj_t *, vQueue, pObj, i )
{ {
pObj->fMark = 0; pObj->fMark = 0;
// retime the node // retime the node
@ -968,3 +971,5 @@ clk = clock();
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

5
src/aig/aig/aigRetF.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -207,3 +210,5 @@ Aig_Man_t * Aig_ManRetimeFrontier( Aig_Man_t * p, int nStepsMax )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

28
src/aig/aig/aigScl.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -50,6 +53,7 @@ Aig_Man_t * Aig_ManRemap( Aig_Man_t * p, Vec_Ptr_t * vMap )
pNew->pName = Aig_UtilStrsav( p->pName ); pNew->pName = Aig_UtilStrsav( p->pName );
pNew->pSpec = Aig_UtilStrsav( p->pSpec ); pNew->pSpec = Aig_UtilStrsav( p->pSpec );
pNew->nAsserts = p->nAsserts; pNew->nAsserts = p->nAsserts;
pNew->nConstrs = p->nConstrs;
assert( p->vFlopNums == NULL || Vec_IntSize(p->vFlopNums) == p->nRegs ); assert( p->vFlopNums == NULL || Vec_IntSize(p->vFlopNums) == p->nRegs );
if ( p->vFlopNums ) if ( p->vFlopNums )
pNew->vFlopNums = Vec_IntDup( p->vFlopNums ); pNew->vFlopNums = Vec_IntDup( p->vFlopNums );
@ -69,8 +73,8 @@ Aig_Man_t * Aig_ManRemap( Aig_Man_t * p, Vec_Ptr_t * vMap )
} }
Aig_ManForEachPi( p, pObj, i ) Aig_ManForEachPi( p, pObj, i )
{ {
pObjMapped = Vec_PtrEntry( vMap, i ); pObjMapped = (Aig_Obj_t *)Vec_PtrEntry( vMap, i );
pObj->pData = Aig_NotCond( Aig_Regular(pObjMapped)->pData, Aig_IsComplement(pObjMapped) ); pObj->pData = Aig_NotCond( (Aig_Obj_t *)Aig_Regular(pObjMapped)->pData, Aig_IsComplement(pObjMapped) );
if ( pNew->vFlopReprs && i >= nTruePis && pObj != pObjMapped ) if ( pNew->vFlopReprs && i >= nTruePis && pObj != pObjMapped )
{ {
Vec_IntPush( pNew->vFlopReprs, Aig_ObjPioNum(pObj) ); Vec_IntPush( pNew->vFlopReprs, Aig_ObjPioNum(pObj) );
@ -172,7 +176,7 @@ int Aig_ManSeqCleanup( Aig_Man_t * p )
Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, i ) Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, i )
pObjLo->pNext = pObjLi; pObjLo->pNext = pObjLi;
// mark the nodes reachable from these nodes // mark the nodes reachable from these nodes
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
Aig_ManSeqCleanup_rec( p, pObj, vNodes ); Aig_ManSeqCleanup_rec( p, pObj, vNodes );
assert( Vec_PtrSize(vNodes) <= Aig_ManPoNum(p) ); assert( Vec_PtrSize(vNodes) <= Aig_ManPoNum(p) );
// clean latch output pointers // clean latch output pointers
@ -271,7 +275,7 @@ int Aig_ManSeqCleanupBasic( Aig_Man_t * p )
Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, i ) Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, i )
pObjLo->pNext = pObjLi; pObjLo->pNext = pObjLi;
// mark the nodes reachable from these nodes // mark the nodes reachable from these nodes
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
Aig_ManSeqCleanup_rec( p, pObj, vNodes ); Aig_ManSeqCleanup_rec( p, pObj, vNodes );
assert( Vec_PtrSize(vNodes) <= Aig_ManPoNum(p) ); assert( Vec_PtrSize(vNodes) <= Aig_ManPoNum(p) );
// clean latch output pointers // clean latch output pointers
@ -496,7 +500,7 @@ void Aig_ManComputeSccs( Aig_Man_t * p )
vSupports = Aig_ManSupports( p ); vSupports = Aig_ManSupports( p );
// transforms the supports into the latch dependency matrix // transforms the supports into the latch dependency matrix
vMatrix = Vec_PtrStart( Aig_ManRegNum(p) ); vMatrix = Vec_PtrStart( Aig_ManRegNum(p) );
Vec_PtrForEachEntry( vSupports, vSupp, i ) Vec_PtrForEachEntry( Vec_Int_t *, vSupports, vSupp, i )
{ {
// skip true POs // skip true POs
iOut = Vec_IntPop( vSupp ); iOut = Vec_IntPop( vSupp );
@ -522,11 +526,11 @@ void Aig_ManComputeSccs( Aig_Man_t * p )
vMatrix2 = Vec_PtrAlloc( Aig_ManRegNum(p) ); vMatrix2 = Vec_PtrAlloc( Aig_ManRegNum(p) );
for ( i = 0; i < Aig_ManRegNum(p); i++ ) for ( i = 0; i < Aig_ManRegNum(p); i++ )
Vec_PtrPush( vMatrix2, Vec_IntAlloc(8) ); Vec_PtrPush( vMatrix2, Vec_IntAlloc(8) );
Vec_PtrForEachEntry( vMatrix, vSupp, i ) Vec_PtrForEachEntry( Vec_Int_t *, vMatrix, vSupp, i )
{ {
Vec_IntForEachEntry( vSupp, iIn, k ) Vec_IntForEachEntry( vSupp, iIn, k )
{ {
vSupp2 = Vec_PtrEntry( vMatrix2, iIn ); vSupp2 = (Vec_Int_t *)Vec_PtrEntry( vMatrix2, iIn );
Vec_IntPush( vSupp2, i ); Vec_IntPush( vSupp2, i );
} }
} }
@ -548,7 +552,7 @@ void Aig_ManComputeSccs( Aig_Man_t * p )
Vec_IntPush( vComp, iOut ); Vec_IntPush( vComp, iOut );
Vec_IntForEachEntry( vComp, iOut, i ) Vec_IntForEachEntry( vComp, iOut, i )
{ {
vSupp = Vec_PtrEntry( vMatrix, iOut ); vSupp = (Vec_Int_t *)Vec_PtrEntry( vMatrix, iOut );
Vec_IntForEachEntry( vSupp, iIn, k ) Vec_IntForEachEntry( vSupp, iIn, k )
{ {
if ( pVarsTot[iIn] ) if ( pVarsTot[iIn] )
@ -556,7 +560,7 @@ void Aig_ManComputeSccs( Aig_Man_t * p )
pVarsTot[iIn] = 1; pVarsTot[iIn] = 1;
Vec_IntPush( vComp, iIn ); Vec_IntPush( vComp, iIn );
} }
vSupp2 = Vec_PtrEntry( vMatrix2, iOut ); vSupp2 = (Vec_Int_t *)Vec_PtrEntry( vMatrix2, iOut );
Vec_IntForEachEntry( vSupp2, iIn, k ) Vec_IntForEachEntry( vSupp2, iIn, k )
{ {
if ( pVarsTot[iIn] ) if ( pVarsTot[iIn] )
@ -602,14 +606,14 @@ Aig_Man_t * Aig_ManSclPart( Aig_Man_t * pAig, int fLatchConst, int fLatchEqual,
if ( pAig->vClockDoms ) if ( pAig->vClockDoms )
{ {
vResult = Vec_PtrAlloc( 100 ); vResult = Vec_PtrAlloc( 100 );
Vec_PtrForEachEntry( (Vec_Ptr_t *)pAig->vClockDoms, vPart, i ) Vec_PtrForEachEntry( Vec_Int_t *, (Vec_Ptr_t *)pAig->vClockDoms, vPart, i )
Vec_PtrPush( vResult, Vec_IntDup(vPart) ); Vec_PtrPush( vResult, Vec_IntDup(vPart) );
} }
else else
vResult = Aig_ManRegPartitionSimple( pAig, 0, 0 ); vResult = Aig_ManRegPartitionSimple( pAig, 0, 0 );
Aig_ManReprStart( pAig, Aig_ManObjNumMax(pAig) ); Aig_ManReprStart( pAig, Aig_ManObjNumMax(pAig) );
Vec_PtrForEachEntry( vResult, vPart, i ) Vec_PtrForEachEntry( Vec_Int_t *, vResult, vPart, i )
{ {
pTemp = Aig_ManRegCreatePart( pAig, vPart, &nCountPis, &nCountRegs, &pMapBack ); pTemp = Aig_ManRegCreatePart( pAig, vPart, &nCountPis, &nCountRegs, &pMapBack );
Aig_ManSetRegNum( pTemp, pTemp->nRegs ); Aig_ManSetRegNum( pTemp, pTemp->nRegs );
@ -699,3 +703,5 @@ Aig_Man_t * Aig_ManScl( Aig_Man_t * pAig, int fLatchConst, int fLatchEqual, int
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

9
src/aig/aig/aigShow.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -59,7 +62,7 @@ void Aig_WriteDotAig( Aig_Man_t * pMan, char * pFileName, int fHaig, Vec_Ptr_t *
// mark the nodes // mark the nodes
if ( vBold ) if ( vBold )
Vec_PtrForEachEntry( vBold, pNode, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vBold, pNode, i )
pNode->fMarkB = 1; pNode->fMarkB = 1;
// compute levels // compute levels
@ -308,7 +311,7 @@ void Aig_WriteDotAig( Aig_Man_t * pMan, char * pFileName, int fHaig, Vec_Ptr_t *
// unmark nodes // unmark nodes
if ( vBold ) if ( vBold )
Vec_PtrForEachEntry( vBold, pNode, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vBold, pNode, i )
pNode->fMarkB = 0; pNode->fMarkB = 0;
Aig_ManForEachPo( pMan, pNode, i ) Aig_ManForEachPo( pMan, pNode, i )
@ -354,3 +357,5 @@ void Aig_ManShow( Aig_Man_t * pMan, int fHaig, Vec_Ptr_t * vBold )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

316
src/aig/aig/aigSplit.c Normal file
View File

@ -0,0 +1,316 @@
/**CFile****************************************************************
FileName [aigSplit.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [AIG package.]
Synopsis [Splits the property output cone into a set of cofactor properties.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - April 28, 2007.]
Revision [$Id: aigSplit.c,v 1.00 2007/04/28 00:00:00 alanmi Exp $]
***********************************************************************/
#include "aig.h"
#include "saig.h"
#include "cuddInt.h"
#include "extra.h"
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Converts the node to MUXes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_NodeBddToMuxes_rec( DdManager * dd, DdNode * bFunc, Aig_Man_t * pNew, st_table * tBdd2Node )
{
Aig_Obj_t * pNode, * pNode0, * pNode1, * pNodeC;
assert( !Cudd_IsComplement(bFunc) );
if ( st_lookup( tBdd2Node, (char *)bFunc, (char **)&pNode ) )
return pNode;
// solve for the children nodes
pNode0 = Aig_NodeBddToMuxes_rec( dd, Cudd_Regular(cuddE(bFunc)), pNew, tBdd2Node );
pNode0 = Aig_NotCond( pNode0, Cudd_IsComplement(cuddE(bFunc)) );
pNode1 = Aig_NodeBddToMuxes_rec( dd, cuddT(bFunc), pNew, tBdd2Node );
if ( !st_lookup( tBdd2Node, (char *)Cudd_bddIthVar(dd, bFunc->index), (char **)&pNodeC ) )
assert( 0 );
// create the MUX node
pNode = Aig_Mux( pNew, pNodeC, pNode1, pNode0 );
st_insert( tBdd2Node, (char *)bFunc, (char *)pNode );
return pNode;
}
/**Function*************************************************************
Synopsis [Derives AIG for the BDDs of the cofactors.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Aig_ManConvertBddsToAigs( Aig_Man_t * p, DdManager * dd, Vec_Ptr_t * vCofs )
{
DdNode * bFunc;
st_table * tBdd2Node;
Aig_Man_t * pNew;
Aig_Obj_t * pObj;
int i;
Aig_ManCleanData( p );
// generate AIG for BDD
pNew = Aig_ManStart( Aig_ManObjNum(p) );
pNew->pName = Aig_UtilStrsav( p->pName );
Aig_ManConst1(p)->pData = Aig_ManConst1(pNew);
Aig_ManForEachPi( p, pObj, i )
pObj->pData = Aig_ObjCreatePi( pNew );
// create the table mapping BDD nodes into the ABC nodes
tBdd2Node = st_init_table( st_ptrcmp, st_ptrhash );
// add the constant and the elementary vars
st_insert( tBdd2Node, (char *)Cudd_ReadOne(dd), (char *)Aig_ManConst1(pNew) );
Aig_ManForEachPi( p, pObj, i )
st_insert( tBdd2Node, (char *)Cudd_bddIthVar(dd, i), (char *)pObj->pData );
// build primary outputs for the cofactors
Vec_PtrForEachEntry( DdNode *, vCofs, bFunc, i )
{
if ( bFunc == Cudd_ReadLogicZero(dd) )
continue;
pObj = Aig_NodeBddToMuxes_rec( dd, Cudd_Regular(bFunc), pNew, tBdd2Node );
pObj = Aig_NotCond( pObj, Cudd_IsComplement(bFunc) );
Aig_ObjCreatePo( pNew, pObj );
}
st_free_table( tBdd2Node );
// duplicate the rest of the AIG
// add the POs
Aig_ManForEachPo( p, pObj, i )
{
if ( i == 0 )
continue;
Aig_ManDupSimpleDfs_rec( pNew, p, Aig_ObjFanin0(pObj) );
pObj->pData = Aig_ObjCreatePo( pNew, Aig_ObjChild0Copy(pObj) );
}
Aig_ManCleanup( pNew );
Aig_ManSetRegNum( pNew, Aig_ManRegNum(p) );
// check the resulting network
if ( !Aig_ManCheck(pNew) )
printf( "Aig_ManConvertBddsToAigs(): The check has failed.\n" );
return pNew;
}
/**Function*************************************************************
Synopsis [Returns the array of constraint candidates.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
DdNode * Aig_ManBuildPoBdd_rec( Aig_Man_t * p, Aig_Obj_t * pObj, DdManager * dd )
{
DdNode * bBdd0, * bBdd1;
if ( pObj->pData != NULL )
return (DdNode *)pObj->pData;
assert( Aig_ObjIsNode(pObj) );
bBdd0 = Aig_ManBuildPoBdd_rec( p, Aig_ObjFanin0(pObj), dd );
bBdd1 = Aig_ManBuildPoBdd_rec( p, Aig_ObjFanin1(pObj), dd );
bBdd0 = Cudd_NotCond( bBdd0, Aig_ObjFaninC0(pObj) );
bBdd1 = Cudd_NotCond( bBdd1, Aig_ObjFaninC1(pObj) );
pObj->pData = Cudd_bddAnd( dd, bBdd0, bBdd1 ); Cudd_Ref( (DdNode *)pObj->pData );
return (DdNode *)pObj->pData;
}
/**Function*************************************************************
Synopsis [Derive BDDs for the cofactors.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Aig_ManCofactorBdds( Aig_Man_t * p, Vec_Ptr_t * vSubset, DdManager * dd, DdNode * bFunc )
{
Vec_Ptr_t * vCofs;
DdNode * bCube, * bTemp, * bCof, ** pbVars;
int i;
vCofs = Vec_PtrAlloc( 100 );
pbVars = (DdNode **)Vec_PtrArray(vSubset);
for ( i = 0; i < (1 << Vec_PtrSize(vSubset)); i++ )
{
bCube = Extra_bddBitsToCube( dd, i, Vec_PtrSize(vSubset), pbVars, 1 ); Cudd_Ref( bCube );
bCof = Cudd_Cofactor( dd, bFunc, bCube ); Cudd_Ref( bCof );
bCof = Cudd_bddAnd( dd, bTemp = bCof, bCube ); Cudd_Ref( bCof );
Cudd_RecursiveDeref( dd, bTemp );
Cudd_RecursiveDeref( dd, bCube );
Vec_PtrPush( vCofs, bCof );
}
return vCofs;
}
/**Function*************************************************************
Synopsis [Construct BDDs for the primary output.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
DdManager * Aig_ManBuildPoBdd( Aig_Man_t * p, DdNode ** pbFunc )
{
DdManager * dd;
Aig_Obj_t * pObj;
int i;
assert( Saig_ManPoNum(p) == 1 );
Aig_ManCleanData( p );
dd = Cudd_Init( Aig_ManPiNum(p), 0, CUDD_UNIQUE_SLOTS, CUDD_CACHE_SLOTS, 0 );
Cudd_AutodynEnable( dd, CUDD_REORDER_SYMM_SIFT );
pObj = Aig_ManConst1(p);
pObj->pData = Cudd_ReadOne(dd); Cudd_Ref( (DdNode *)pObj->pData );
Aig_ManForEachPi( p, pObj, i )
{
pObj->pData = Cudd_bddIthVar(dd, i); Cudd_Ref( (DdNode *)pObj->pData );
}
pObj = Aig_ManPo( p, 0 );
*pbFunc = Aig_ManBuildPoBdd_rec( p, Aig_ObjFanin0(pObj), dd ); Cudd_Ref( *pbFunc );
*pbFunc = Cudd_NotCond( *pbFunc, Aig_ObjFaninC0(pObj) );
Aig_ManForEachObj( p, pObj, i )
{
if ( pObj->pData )
Cudd_RecursiveDeref( dd, (DdNode *)pObj->pData );
}
Cudd_ReduceHeap( dd, CUDD_REORDER_SYMM_SIFT, 1 );
return dd;
}
/**Function*************************************************************
Synopsis [Randomly selects a random subset of inputs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Aig_ManVecRandSubset( Vec_Ptr_t * vVec, int nVars )
{
Vec_Ptr_t * vRes;
void * pEntry;
unsigned Rand;
vRes = Vec_PtrDup(vVec);
while ( Vec_PtrSize(vRes) > nVars )
{
Rand = Aig_ManRandom( 0 );
pEntry = Vec_PtrEntry( vRes, Rand % Vec_PtrSize(vRes) );
Vec_PtrRemove( vRes, pEntry );
}
return vRes;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Aig_ManSplit( Aig_Man_t * p, int nVars, int fVerbose )
{
Aig_Man_t * pRes;
Aig_Obj_t * pNode;
DdNode * bFunc;
DdManager * dd;
Vec_Ptr_t * vSupp, * vSubs, * vCofs;
int i, clk = clock();
if ( Saig_ManPoNum(p) != 1 )
{
printf( "Currently works only for one primary output.\n" );
return NULL;
}
if ( nVars < 1 )
{
printf( "The number of cofactoring variables should be a positive number.\n" );
return NULL;
}
if ( nVars > 16 )
{
printf( "The number of cofactoring variables should be less than 17.\n" );
return NULL;
}
vSupp = Aig_Support( p, Aig_ObjFanin0(Aig_ManPo(p,0)) );
if ( Vec_PtrSize(vSupp) == 0 )
{
printf( "Property output function is a constant.\n" );
Vec_PtrFree( vSupp );
return NULL;
}
dd = Aig_ManBuildPoBdd( p, &bFunc ); // bFunc is referenced
if ( fVerbose )
printf( "Support =%5d. BDD size =%6d. ", Vec_PtrSize(vSupp), Cudd_DagSize(bFunc) );
vSubs = Aig_ManVecRandSubset( vSupp, nVars );
// replace nodes by their BDD variables
Vec_PtrForEachEntry( Aig_Obj_t *, vSubs, pNode, i )
Vec_PtrWriteEntry( vSubs, i, pNode->pData );
// derive cofactors and functions
vCofs = Aig_ManCofactorBdds( p, vSubs, dd, bFunc );
pRes = Aig_ManConvertBddsToAigs( p, dd, vCofs );
Vec_PtrFree( vSupp );
Vec_PtrFree( vSubs );
if ( fVerbose )
printf( "Created %d cofactors (out of %d). ", Saig_ManPoNum(pRes), Vec_PtrSize(vCofs) );
if ( fVerbose )
Abc_PrintTime( 1, "Time", clock() - clk );
// dereference
Cudd_RecursiveDeref( dd, bFunc );
Vec_PtrForEachEntry( DdNode *, vCofs, bFunc, i )
Cudd_RecursiveDeref( dd, bFunc );
Vec_PtrFree( vCofs );
Extra_StopManager( dd );
return pRes;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

5
src/aig/aig/aigTable.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -269,3 +272,5 @@ void Aig_TableClear( Aig_Man_t * p )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

6
src/aig/aig/aigTest.c
View File

@ -2,6 +2,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
void Aig_ProcedureTest() void Aig_ProcedureTest()
{ {
Aig_Man_t * p; Aig_Man_t * p;
@ -32,4 +35,5 @@ void Aig_ProcedureTest()
Aig_ManDumpBlif( p, "aig_test_file.blif", NULL, NULL ); Aig_ManDumpBlif( p, "aig_test_file.blif", NULL, NULL );
Aig_ManStop( p ); Aig_ManStop( p );
} }ABC_NAMESPACE_IMPL_END

11
src/aig/aig/aigTiming.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -150,7 +153,7 @@ void Aig_ManStartReverseLevels( Aig_Man_t * p, int nMaxLevelIncrease )
Vec_IntFill( p->vLevelR, Aig_ManObjNumMax(p), 0 ); Vec_IntFill( p->vLevelR, Aig_ManObjNumMax(p), 0 );
// compute levels in reverse topological order // compute levels in reverse topological order
vNodes = Aig_ManDfsReverse( p ); vNodes = Aig_ManDfsReverse( p );
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
{ {
assert( pObj->fMarkA == 0 ); assert( pObj->fMarkA == 0 );
Aig_ObjSetReverseLevel( p, pObj, Aig_ObjReverseLevelNew(p, pObj) ); Aig_ObjSetReverseLevel( p, pObj, Aig_ObjReverseLevelNew(p, pObj) );
@ -209,7 +212,7 @@ void Aig_ManUpdateLevel( Aig_Man_t * p, Aig_Obj_t * pObjNew )
Vec_VecPush( p->vLevels, LevelOld, pObjNew ); Vec_VecPush( p->vLevels, LevelOld, pObjNew );
pObjNew->fMarkA = 1; pObjNew->fMarkA = 1;
// recursively update level // recursively update level
Vec_VecForEachEntryStart( p->vLevels, pTemp, Lev, k, LevelOld ) Vec_VecForEachEntryStart( Aig_Obj_t *, p->vLevels, pTemp, Lev, k, LevelOld )
{ {
pTemp->fMarkA = 0; pTemp->fMarkA = 0;
assert( Aig_ObjLevel(pTemp) == Lev ); assert( Aig_ObjLevel(pTemp) == Lev );
@ -261,7 +264,7 @@ void Aig_ManUpdateReverseLevel( Aig_Man_t * p, Aig_Obj_t * pObjNew )
Vec_VecPush( p->vLevels, LevelOld, pObjNew ); Vec_VecPush( p->vLevels, LevelOld, pObjNew );
pObjNew->fMarkA = 1; pObjNew->fMarkA = 1;
// recursively update level // recursively update level
Vec_VecForEachEntryStart( p->vLevels, pTemp, Lev, k, LevelOld ) Vec_VecForEachEntryStart( Aig_Obj_t *, p->vLevels, pTemp, Lev, k, LevelOld )
{ {
pTemp->fMarkA = 0; pTemp->fMarkA = 0;
LevelOld = Aig_ObjReverseLevel(p, pTemp); LevelOld = Aig_ObjReverseLevel(p, pTemp);
@ -349,3 +352,5 @@ void Aig_ManVerifyReverseLevel( Aig_Man_t * p )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

17
src/aig/aig/aigTruth.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -43,8 +46,8 @@ unsigned * Aig_ManCutTruthOne( Aig_Obj_t * pNode, unsigned * pTruth, int nWords
{ {
unsigned * pTruth0, * pTruth1; unsigned * pTruth0, * pTruth1;
int i; int i;
pTruth0 = Aig_ObjFanin0(pNode)->pData; pTruth0 = (unsigned *)Aig_ObjFanin0(pNode)->pData;
pTruth1 = Aig_ObjFanin1(pNode)->pData; pTruth1 = (unsigned *)Aig_ObjFanin1(pNode)->pData;
if ( Aig_ObjIsExor(pNode) ) if ( Aig_ObjIsExor(pNode) )
for ( i = 0; i < nWords; i++ ) for ( i = 0; i < nWords; i++ )
pTruth[i] = pTruth0[i] ^ pTruth1[i]; pTruth[i] = pTruth0[i] ^ pTruth1[i];
@ -82,13 +85,13 @@ unsigned * Aig_ManCutTruth( Aig_Obj_t * pRoot, Vec_Ptr_t * vLeaves, Vec_Ptr_t *
assert( Vec_PtrSize(vNodes) <= Vec_PtrSize(vTruthStore) ); assert( Vec_PtrSize(vNodes) <= Vec_PtrSize(vTruthStore) );
assert( Vec_PtrSize(vNodes) == 0 || pRoot == Vec_PtrEntryLast(vNodes) ); assert( Vec_PtrSize(vNodes) == 0 || pRoot == Vec_PtrEntryLast(vNodes) );
// assign elementary truth tables // assign elementary truth tables
Vec_PtrForEachEntry( vLeaves, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vLeaves, pObj, i )
pObj->pData = Vec_PtrEntry( vTruthElem, i ); pObj->pData = Vec_PtrEntry( vTruthElem, i );
// compute truths for other nodes // compute truths for other nodes
nWords = Aig_TruthWordNum( Vec_PtrSize(vLeaves) ); nWords = Aig_TruthWordNum( Vec_PtrSize(vLeaves) );
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
pObj->pData = Aig_ManCutTruthOne( pObj, Vec_PtrEntry(vTruthStore, i), nWords ); pObj->pData = Aig_ManCutTruthOne( pObj, (unsigned *)Vec_PtrEntry(vTruthStore, i), nWords );
return pRoot->pData; return (unsigned *)pRoot->pData;
} }
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -96,3 +99,5 @@ unsigned * Aig_ManCutTruth( Aig_Obj_t * pRoot, Vec_Ptr_t * vLeaves, Vec_Ptr_t *
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

9
src/aig/aig/aigTsim.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -321,7 +324,7 @@ void Aig_TsiStateOrAll( Aig_Tsi_t * pTsi, unsigned * pState )
{ {
unsigned * pPrev; unsigned * pPrev;
int i, k; int i, k;
Vec_PtrForEachEntry( pTsi->vStates, pPrev, i ) Vec_PtrForEachEntry( unsigned *, pTsi->vStates, pPrev, i )
{ {
for ( k = 0; k < pTsi->nWords; k++ ) for ( k = 0; k < pTsi->nWords; k++ )
pState[k] |= pPrev[k]; pState[k] |= pPrev[k];
@ -423,7 +426,7 @@ Vec_Ptr_t * Aig_ManTernarySimulate( Aig_Man_t * p, int fVerbose )
return NULL; return NULL;
} }
// OR all the states // OR all the states
pState = Vec_PtrEntry( pTsi->vStates, 0 ); pState = (unsigned *)Vec_PtrEntry( pTsi->vStates, 0 );
Aig_TsiStateOrAll( pTsi, pState ); Aig_TsiStateOrAll( pTsi, pState );
// check if there are constants // check if there are constants
fConstants = 0; fConstants = 0;
@ -506,3 +509,5 @@ Aig_Man_t * Aig_ManConstReduce( Aig_Man_t * p, int fVerbose )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

199
src/aig/aig/aigUtil.c
View File

@ -20,6 +20,8 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -82,6 +84,30 @@ void Aig_ManIncrementTravId( Aig_Man_t * p )
p->nTravIds++; p->nTravIds++;
} }
/**Function*************************************************************
Synopsis [Returns the time stamp.]
Description [The file should be closed.]
SideEffects []
SeeAlso []
***********************************************************************/
char * Aig_TimeStamp()
{
static char Buffer[100];
char * TimeStamp;
time_t ltime;
// get the current time
time( &ltime );
TimeStamp = asctime( localtime( &ltime ) );
TimeStamp[ strlen(TimeStamp) - 1 ] = 0;
strcpy( Buffer, TimeStamp );
return Buffer;
}
/**Function************************************************************* /**Function*************************************************************
Synopsis [Make sure AIG has not gaps in the numeric order.] Synopsis [Make sure AIG has not gaps in the numeric order.]
@ -548,10 +574,10 @@ void Aig_ObjPrintEqn( FILE * pFile, Aig_Obj_t * pObj, Vec_Vec_t * vLevels, int L
} }
// AND case // AND case
Vec_VecExpand( vLevels, Level ); Vec_VecExpand( vLevels, Level );
vSuper = Vec_VecEntry(vLevels, Level); vSuper = (Vec_Ptr_t *)Vec_VecEntry(vLevels, Level);
Aig_ObjCollectMulti( pObj, vSuper ); Aig_ObjCollectMulti( pObj, vSuper );
fprintf( pFile, "%s", (Level==0? "" : "(") ); fprintf( pFile, "%s", (Level==0? "" : "(") );
Vec_PtrForEachEntry( vSuper, pFanin, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vSuper, pFanin, i )
{ {
Aig_ObjPrintEqn( pFile, Aig_NotCond(pFanin, fCompl), vLevels, Level+1 ); Aig_ObjPrintEqn( pFile, Aig_NotCond(pFanin, fCompl), vLevels, Level+1 );
if ( i < Vec_PtrSize(vSuper) - 1 ) if ( i < Vec_PtrSize(vSuper) - 1 )
@ -597,10 +623,10 @@ void Aig_ObjPrintVerilog( FILE * pFile, Aig_Obj_t * pObj, Vec_Vec_t * vLevels, i
if ( Aig_ObjIsExor(pObj) ) if ( Aig_ObjIsExor(pObj) )
{ {
Vec_VecExpand( vLevels, Level ); Vec_VecExpand( vLevels, Level );
vSuper = Vec_VecEntry( vLevels, Level ); vSuper = (Vec_Ptr_t *)Vec_VecEntry( vLevels, Level );
Aig_ObjCollectMulti( pObj, vSuper ); Aig_ObjCollectMulti( pObj, vSuper );
fprintf( pFile, "%s", (Level==0? "" : "(") ); fprintf( pFile, "%s", (Level==0? "" : "(") );
Vec_PtrForEachEntry( vSuper, pFanin, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vSuper, pFanin, i )
{ {
Aig_ObjPrintVerilog( pFile, Aig_NotCond(pFanin, (fCompl && i==0)), vLevels, Level+1 ); Aig_ObjPrintVerilog( pFile, Aig_NotCond(pFanin, (fCompl && i==0)), vLevels, Level+1 );
if ( i < Vec_PtrSize(vSuper) - 1 ) if ( i < Vec_PtrSize(vSuper) - 1 )
@ -635,10 +661,10 @@ void Aig_ObjPrintVerilog( FILE * pFile, Aig_Obj_t * pObj, Vec_Vec_t * vLevels, i
} }
// AND case // AND case
Vec_VecExpand( vLevels, Level ); Vec_VecExpand( vLevels, Level );
vSuper = Vec_VecEntry(vLevels, Level); vSuper = (Vec_Ptr_t *)Vec_VecEntry(vLevels, Level);
Aig_ObjCollectMulti( pObj, vSuper ); Aig_ObjCollectMulti( pObj, vSuper );
fprintf( pFile, "%s", (Level==0? "" : "(") ); fprintf( pFile, "%s", (Level==0? "" : "(") );
Vec_PtrForEachEntry( vSuper, pFanin, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vSuper, pFanin, i )
{ {
Aig_ObjPrintVerilog( pFile, Aig_NotCond(pFanin, fCompl), vLevels, Level+1 ); Aig_ObjPrintVerilog( pFile, Aig_NotCond(pFanin, fCompl), vLevels, Level+1 );
if ( i < Vec_PtrSize(vSuper) - 1 ) if ( i < Vec_PtrSize(vSuper) - 1 )
@ -702,7 +728,7 @@ void Aig_ManPrintVerbose( Aig_Man_t * p, int fHaig )
printf( " %p", pObj ); printf( " %p", pObj );
printf( "\n" ); printf( "\n" );
vNodes = Aig_ManDfs( p, 0 ); vNodes = Aig_ManDfs( p, 0 );
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
Aig_ObjPrintVerbose( pObj, fHaig ), printf( "\n" ); Aig_ObjPrintVerbose( pObj, fHaig ), printf( "\n" );
printf( "\n" ); printf( "\n" );
} }
@ -762,7 +788,7 @@ void Aig_ManDumpBlif( Aig_Man_t * p, char * pFileName, Vec_Ptr_t * vPiNames, Vec
pObj->iData = Counter++; pObj->iData = Counter++;
Aig_ManForEachPo( p, pObj, i ) Aig_ManForEachPo( p, pObj, i )
pObj->iData = Counter++; pObj->iData = Counter++;
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
pObj->iData = Counter++; pObj->iData = Counter++;
nDigits = Aig_Base10Log( Counter ); nDigits = Aig_Base10Log( Counter );
// write the file // write the file
@ -809,7 +835,7 @@ void Aig_ManDumpBlif( Aig_Man_t * p, char * pFileName, Vec_Ptr_t * vPiNames, Vec
if ( pConst1 ) if ( pConst1 )
fprintf( pFile, ".names n%0*d\n 1\n", nDigits, pConst1->iData ); fprintf( pFile, ".names n%0*d\n 1\n", nDigits, pConst1->iData );
Aig_ManSetPioNumbers( p ); Aig_ManSetPioNumbers( p );
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
{ {
fprintf( pFile, ".names" ); fprintf( pFile, ".names" );
if ( vPiNames && Aig_ObjIsPi(Aig_ObjFanin0(pObj)) ) if ( vPiNames && Aig_ObjIsPi(Aig_ObjFanin0(pObj)) )
@ -877,7 +903,7 @@ void Aig_ManDumpVerilog( Aig_Man_t * p, char * pFileName )
pObj->iData = Counter++; pObj->iData = Counter++;
Aig_ManForEachPo( p, pObj, i ) Aig_ManForEachPo( p, pObj, i )
pObj->iData = Counter++; pObj->iData = Counter++;
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
pObj->iData = Counter++; pObj->iData = Counter++;
nDigits = Aig_Base10Log( Counter ); nDigits = Aig_Base10Log( Counter );
// write the file // write the file
@ -911,14 +937,14 @@ void Aig_ManDumpVerilog( Aig_Man_t * p, char * pFileName )
fprintf( pFile, "wire n%0*d;\n", nDigits, pObjLi->iData ); fprintf( pFile, "wire n%0*d;\n", nDigits, pObjLi->iData );
} }
// write nodes // write nodes
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
fprintf( pFile, "wire n%0*d;\n", nDigits, pObj->iData ); fprintf( pFile, "wire n%0*d;\n", nDigits, pObj->iData );
if ( pConst1 ) if ( pConst1 )
fprintf( pFile, "wire n%0*d;\n", nDigits, pConst1->iData ); fprintf( pFile, "wire n%0*d;\n", nDigits, pConst1->iData );
// write nodes // write nodes
if ( pConst1 ) if ( pConst1 )
fprintf( pFile, "assign n%0*d = 1\'b1;\n", nDigits, pConst1->iData ); fprintf( pFile, "assign n%0*d = 1\'b1;\n", nDigits, pConst1->iData );
Vec_PtrForEachEntry( vNodes, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
{ {
fprintf( pFile, "assign n%0*d = %sn%0*d & %sn%0*d;\n", fprintf( pFile, "assign n%0*d = %sn%0*d & %sn%0*d;\n",
nDigits, pObj->iData, nDigits, pObj->iData,
@ -1193,7 +1219,7 @@ void Aig_ManRandomInfo( Vec_Ptr_t * vInfo, int iInputStart, int iWordStart, int
{ {
unsigned * pInfo; unsigned * pInfo;
int i, w; int i, w;
Vec_PtrForEachEntryStart( vInfo, pInfo, i, iInputStart ) Vec_PtrForEachEntryStart( unsigned *, vInfo, pInfo, i, iInputStart )
for ( w = iWordStart; w < iWordStop; w++ ) for ( w = iWordStart; w < iWordStop; w++ )
pInfo[w] = Aig_ManRandom(0); pInfo[w] = Aig_ManRandom(0);
} }
@ -1278,10 +1304,15 @@ void Aig_NodeIntersectLists( Vec_Ptr_t * vArr1, Vec_Ptr_t * vArr2, Vec_Ptr_t * v
assert( vArr->nSize <= vArr2->nSize ); assert( vArr->nSize <= vArr2->nSize );
} }
ABC_NAMESPACE_IMPL_END
#include "fra.h" #include "fra.h"
#include "saig.h" #include "saig.h"
extern void Aig_ManCounterExampleValueStart( Aig_Man_t * pAig, Fra_Cex_t * pCex ); ABC_NAMESPACE_IMPL_START
extern void Aig_ManCounterExampleValueStart( Aig_Man_t * pAig, Abc_Cex_t * pCex );
extern void Aig_ManCounterExampleValueStop( Aig_Man_t * pAig ); extern void Aig_ManCounterExampleValueStop( Aig_Man_t * pAig );
extern int Aig_ManCounterExampleValueLookup( Aig_Man_t * pAig, int Id, int iFrame ); extern int Aig_ManCounterExampleValueLookup( Aig_Man_t * pAig, int Id, int iFrame );
@ -1297,7 +1328,7 @@ extern int Aig_ManCounterExampleValueLookup( Aig_Man_t * pAig, int Id, int iFra
SeeAlso [] SeeAlso []
***********************************************************************/ ***********************************************************************/
void Aig_ManCounterExampleValueStart( Aig_Man_t * pAig, Fra_Cex_t * pCex ) void Aig_ManCounterExampleValueStart( Aig_Man_t * pAig, Abc_Cex_t * pCex )
{ {
Aig_Obj_t * pObj, * pObjRi, * pObjRo; Aig_Obj_t * pObj, * pObjRi, * pObjRo;
int Val0, Val1, nObjs, i, k, iBit = 0; int Val0, Val1, nObjs, i, k, iBit = 0;
@ -1313,36 +1344,36 @@ void Aig_ManCounterExampleValueStart( Aig_Man_t * pAig, Fra_Cex_t * pCex )
for ( i = 0; i <= pCex->iFrame; i++ ) for ( i = 0; i <= pCex->iFrame; i++ )
{ {
// set constant 1 node // set constant 1 node
Aig_InfoSetBit( pAig->pData2, nObjs * i + 0 ); Aig_InfoSetBit( (unsigned *)pAig->pData2, nObjs * i + 0 );
// set primary inputs according to the counter-example // set primary inputs according to the counter-example
Saig_ManForEachPi( pAig, pObj, k ) Saig_ManForEachPi( pAig, pObj, k )
if ( Aig_InfoHasBit(pCex->pData, iBit++) ) if ( Aig_InfoHasBit(pCex->pData, iBit++) )
Aig_InfoSetBit( pAig->pData2, nObjs * i + Aig_ObjId(pObj) ); Aig_InfoSetBit( (unsigned *)pAig->pData2, nObjs * i + Aig_ObjId(pObj) );
// compute values for each node // compute values for each node
Aig_ManForEachNode( pAig, pObj, k ) Aig_ManForEachNode( pAig, pObj, k )
{ {
Val0 = Aig_InfoHasBit( pAig->pData2, nObjs * i + Aig_ObjFaninId0(pObj) ); Val0 = Aig_InfoHasBit( (unsigned *)pAig->pData2, nObjs * i + Aig_ObjFaninId0(pObj) );
Val1 = Aig_InfoHasBit( pAig->pData2, nObjs * i + Aig_ObjFaninId1(pObj) ); Val1 = Aig_InfoHasBit( (unsigned *)pAig->pData2, nObjs * i + Aig_ObjFaninId1(pObj) );
if ( (Val0 ^ Aig_ObjFaninC0(pObj)) & (Val1 ^ Aig_ObjFaninC1(pObj)) ) if ( (Val0 ^ Aig_ObjFaninC0(pObj)) & (Val1 ^ Aig_ObjFaninC1(pObj)) )
Aig_InfoSetBit( pAig->pData2, nObjs * i + Aig_ObjId(pObj) ); Aig_InfoSetBit( (unsigned *)pAig->pData2, nObjs * i + Aig_ObjId(pObj) );
} }
// derive values for combinational outputs // derive values for combinational outputs
Aig_ManForEachPo( pAig, pObj, k ) Aig_ManForEachPo( pAig, pObj, k )
{ {
Val0 = Aig_InfoHasBit( pAig->pData2, nObjs * i + Aig_ObjFaninId0(pObj) ); Val0 = Aig_InfoHasBit( (unsigned *)pAig->pData2, nObjs * i + Aig_ObjFaninId0(pObj) );
if ( Val0 ^ Aig_ObjFaninC0(pObj) ) if ( Val0 ^ Aig_ObjFaninC0(pObj) )
Aig_InfoSetBit( pAig->pData2, nObjs * i + Aig_ObjId(pObj) ); Aig_InfoSetBit( (unsigned *)pAig->pData2, nObjs * i + Aig_ObjId(pObj) );
} }
if ( i == pCex->iFrame ) if ( i == pCex->iFrame )
continue; continue;
// transfer values to the register output of the next frame // transfer values to the register output of the next frame
Saig_ManForEachLiLo( pAig, pObjRi, pObjRo, k ) Saig_ManForEachLiLo( pAig, pObjRi, pObjRo, k )
if ( Aig_InfoHasBit( pAig->pData2, nObjs * i + Aig_ObjId(pObjRi) ) ) if ( Aig_InfoHasBit( (unsigned *)pAig->pData2, nObjs * i + Aig_ObjId(pObjRi) ) )
Aig_InfoSetBit( pAig->pData2, nObjs * (i+1) + Aig_ObjId(pObjRo) ); Aig_InfoSetBit( (unsigned *)pAig->pData2, nObjs * (i+1) + Aig_ObjId(pObjRo) );
} }
assert( iBit == pCex->nBits ); assert( iBit == pCex->nBits );
// check that the counter-example is correct, that is, the corresponding output is asserted // check that the counter-example is correct, that is, the corresponding output is asserted
assert( Aig_InfoHasBit( pAig->pData2, nObjs * pCex->iFrame + Aig_ObjId(Aig_ManPo(pAig, pCex->iPo)) ) ); assert( Aig_InfoHasBit( (unsigned *)pAig->pData2, nObjs * pCex->iFrame + Aig_ObjId(Aig_ManPo(pAig, pCex->iPo)) ) );
} }
/**Function************************************************************* /**Function*************************************************************
@ -1379,7 +1410,7 @@ void Aig_ManCounterExampleValueStop( Aig_Man_t * pAig )
int Aig_ManCounterExampleValueLookup( Aig_Man_t * pAig, int Id, int iFrame ) int Aig_ManCounterExampleValueLookup( Aig_Man_t * pAig, int Id, int iFrame )
{ {
assert( Id >= 0 && Id < Aig_ManObjNum(pAig) ); assert( Id >= 0 && Id < Aig_ManObjNum(pAig) );
return Aig_InfoHasBit( pAig->pData2, Aig_ManObjNum(pAig) * iFrame + Id ); return Aig_InfoHasBit( (unsigned *)pAig->pData2, Aig_ManObjNum(pAig) * iFrame + Id );
} }
/**Function************************************************************* /**Function*************************************************************
@ -1393,7 +1424,7 @@ int Aig_ManCounterExampleValueLookup( Aig_Man_t * pAig, int Id, int iFrame )
SeeAlso [] SeeAlso []
***********************************************************************/ ***********************************************************************/
void Aig_ManCounterExampleValueTest( Aig_Man_t * pAig, Fra_Cex_t * pCex ) void Aig_ManCounterExampleValueTest( Aig_Man_t * pAig, Abc_Cex_t * pCex )
{ {
Aig_Obj_t * pObj = Aig_ManObj( pAig, Aig_ManObjNum(pAig)/2 ); Aig_Obj_t * pObj = Aig_ManObj( pAig, Aig_ManObjNum(pAig)/2 );
int iFrame = ABC_MAX( 0, pCex->iFrame - 1 ); int iFrame = ABC_MAX( 0, pCex->iFrame - 1 );
@ -1404,9 +1435,123 @@ void Aig_ManCounterExampleValueTest( Aig_Man_t * pAig, Fra_Cex_t * pCex )
Aig_ManCounterExampleValueStop( pAig ); Aig_ManCounterExampleValueStop( pAig );
} }
/**Function*************************************************************
Synopsis [Handle the counter-example.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_ManSetPhase( Aig_Man_t * pAig )
{
Aig_Obj_t * pObj;
int i;
// set the PI simulation information
Aig_ManConst1( pAig )->fPhase = 1;
Aig_ManForEachPi( pAig, pObj, i )
pObj->fPhase = 0;
// simulate internal nodes
Aig_ManForEachNode( pAig, pObj, i )
pObj->fPhase = ( Aig_ObjFanin0(pObj)->fPhase ^ Aig_ObjFaninC0(pObj) )
& ( Aig_ObjFanin1(pObj)->fPhase ^ Aig_ObjFaninC1(pObj) );
// simulate PO nodes
Aig_ManForEachPo( pAig, pObj, i )
pObj->fPhase = Aig_ObjFanin0(pObj)->fPhase ^ Aig_ObjFaninC0(pObj);
}
/**Function*************************************************************
Synopsis [Collects muxes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Aig_ManMuxesCollect( Aig_Man_t * pAig )
{
Vec_Ptr_t * vMuxes;
Aig_Obj_t * pObj;
int i;
vMuxes = Vec_PtrAlloc( 100 );
Aig_ManForEachNode( pAig, pObj, i )
if ( Aig_ObjIsMuxType(pObj) )
Vec_PtrPush( vMuxes, pObj );
return vMuxes;
}
/**Function*************************************************************
Synopsis [Dereferences muxes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_ManMuxesDeref( Aig_Man_t * pAig, Vec_Ptr_t * vMuxes )
{
Aig_Obj_t * pObj, * pNodeT, * pNodeE, * pNodeC;
int i;
Vec_PtrForEachEntry( Aig_Obj_t *, vMuxes, pObj, i )
{
if ( Aig_ObjRecognizeExor( pObj, &pNodeT, &pNodeE ) )
{
pNodeT->nRefs--;
pNodeE->nRefs--;
}
else
{
pNodeC = Aig_ObjRecognizeMux( pObj, &pNodeT, &pNodeE );
pNodeC->nRefs--;
}
}
}
/**Function*************************************************************
Synopsis [References muxes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_ManMuxesRef( Aig_Man_t * pAig, Vec_Ptr_t * vMuxes )
{
Aig_Obj_t * pObj, * pNodeT, * pNodeE, * pNodeC;
int i;
Vec_PtrForEachEntry( Aig_Obj_t *, vMuxes, pObj, i )
{
if ( Aig_ObjRecognizeExor( pObj, &pNodeT, &pNodeE ) )
{
pNodeT->nRefs++;
pNodeE->nRefs++;
}
else
{
pNodeC = Aig_ObjRecognizeMux( pObj, &pNodeT, &pNodeE );
pNodeC->nRefs++;
}
}
}
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// END OF FILE /// /// END OF FILE ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

9
src/aig/aig/aigWin.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -82,7 +85,7 @@ int Aig_ManFindCut_int( Vec_Ptr_t * vFront, Vec_Ptr_t * vVisited, int nSizeLimit
CostBest = 100; CostBest = 100;
pFaninBest = NULL; pFaninBest = NULL;
//printf( "Evaluating fanins of the cut:\n" ); //printf( "Evaluating fanins of the cut:\n" );
Vec_PtrForEachEntry( vFront, pNode, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vFront, pNode, i )
{ {
CostCur = Aig_NodeGetLeafCostOne( pNode, nFanoutLimit ); CostCur = Aig_NodeGetLeafCostOne( pNode, nFanoutLimit );
//printf( " Fanin %s has cost %d.\n", Aig_ObjName(pNode), CostCur ); //printf( " Fanin %s has cost %d.\n", Aig_ObjName(pNode), CostCur );
@ -173,7 +176,7 @@ void Aig_ManFindCut( Aig_Obj_t * pRoot, Vec_Ptr_t * vFront, Vec_Ptr_t * vVisited
assert( Vec_PtrSize(vFront) <= nSizeLimit ); assert( Vec_PtrSize(vFront) <= nSizeLimit );
// clean the visit markings // clean the visit markings
Vec_PtrForEachEntry( vVisited, pNode, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vVisited, pNode, i )
pNode->fMarkA = 0; pNode->fMarkA = 0;
} }
@ -182,3 +185,5 @@ void Aig_ManFindCut( Aig_Obj_t * pRoot, Vec_Ptr_t * vFront, Vec_Ptr_t * vVisited
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

5
src/aig/aig/aig_.c
View File

@ -20,6 +20,9 @@
#include "aig.h" #include "aig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -46,3 +49,5 @@
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

1
src/aig/aig/module.make
View File

@ -20,6 +20,7 @@ SRC += src/aig/aig/aigCheck.c \
src/aig/aig/aigRetF.c \ src/aig/aig/aigRetF.c \
src/aig/aig/aigScl.c \ src/aig/aig/aigScl.c \
src/aig/aig/aigShow.c \ src/aig/aig/aigShow.c \
src/aig/aig/aigSplit.c \
src/aig/aig/aigTable.c \ src/aig/aig/aigTable.c \
src/aig/aig/aigTiming.c \ src/aig/aig/aigTiming.c \
src/aig/aig/aigTruth.c \ src/aig/aig/aigTruth.c \

11
src/aig/bar/bar.c
View File

@ -21,9 +21,14 @@
#include <stdio.h> #include <stdio.h>
#include <stdlib.h> #include <stdlib.h>
#include <string.h> #include <string.h>
#include "abc_global.h" #include "abc_global.h"
#include "main.h"
#include "bar.h" #include "bar.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -61,9 +66,7 @@ static void Bar_ProgressClean( Bar_Progress_t * p );
Bar_Progress_t * Bar_ProgressStart( FILE * pFile, int nItemsTotal ) Bar_Progress_t * Bar_ProgressStart( FILE * pFile, int nItemsTotal )
{ {
Bar_Progress_t * p; Bar_Progress_t * p;
void * pFrame; Abc_Frame_t * pFrame;
extern int Abc_FrameShowProgress( void * p );
extern void * Abc_FrameReadGlobalFrame();
pFrame = Abc_FrameReadGlobalFrame(); pFrame = Abc_FrameReadGlobalFrame();
if ( pFrame == NULL ) if ( pFrame == NULL )
return NULL; return NULL;
@ -180,3 +183,5 @@ void Bar_ProgressClean( Bar_Progress_t * p )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

16
src/aig/bar/bar.h
View File

@ -21,6 +21,7 @@
#ifndef __BAR_H__ #ifndef __BAR_H__
#define __BAR_H__ #define __BAR_H__
#ifdef _WIN32 #ifdef _WIN32
#define inline __inline // compatible with MS VS 6.0 #define inline __inline // compatible with MS VS 6.0
#endif #endif
@ -33,9 +34,10 @@
/// PARAMETERS /// /// PARAMETERS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
extern "C" {
#endif ABC_NAMESPACE_HEADER_START
#define BAR_PROGRESS_USE 1 #define BAR_PROGRESS_USE 1
@ -62,9 +64,11 @@ static inline void Bar_ProgressUpdate( Bar_Progress_t * p, int nItemsCur,
if ( BAR_PROGRESS_USE && p && (nItemsCur < *((int*)p)) ) return; Bar_ProgressUpdate_int(p, nItemsCur, pString); } if ( BAR_PROGRESS_USE && p && (nItemsCur < *((int*)p)) ) return; Bar_ProgressUpdate_int(p, nItemsCur, pString); }
#ifdef __cplusplus
}
#endif ABC_NAMESPACE_HEADER_END
#endif #endif

11
src/aig/bbl/bblif.c
View File

@ -24,8 +24,12 @@
#include <assert.h> #include <assert.h>
#include <time.h> #include <time.h>
#include "abc_global.h"
#include "bblif.h" #include "bblif.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -375,9 +379,10 @@ static inline void Vec_IntFillExtra( Vec_Int_t * p, int nSize, int Fill )
int i; int i;
if ( p->nSize >= nSize ) if ( p->nSize >= nSize )
return; return;
if ( nSize < 2 * p->nSize ) if ( nSize > 2 * p->nCap )
nSize = 2 * p->nSize;
Vec_IntGrow( p, nSize ); Vec_IntGrow( p, nSize );
else if ( nSize > p->nCap )
Vec_IntGrow( p, 2 * p->nCap );
for ( i = p->nSize; i < nSize; i++ ) for ( i = p->nSize; i < nSize; i++ )
p->pArray[i] = Fill; p->pArray[i] = Fill;
p->nSize = nSize; p->nSize = nSize;
@ -1509,3 +1514,5 @@ void Bbl_ManSimpleDemo()
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

16
src/aig/bbl/bblif.h
View File

@ -21,6 +21,7 @@
#ifndef __BBLIF_H__ #ifndef __BBLIF_H__
#define __BBLIF_H__ #define __BBLIF_H__
/* /*
This file (taken together with "bblif.c") implements a stand-alone This file (taken together with "bblif.c") implements a stand-alone
interface between ABC and an application that uses ABC. interface between ABC and an application that uses ABC.
@ -186,9 +187,10 @@
/// PARAMETERS /// /// PARAMETERS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
extern "C" {
#endif ABC_NAMESPACE_HEADER_START
#ifdef _WIN32 #ifdef _WIN32
#define inline __inline #define inline __inline
@ -269,9 +271,11 @@ extern void Bbl_ManDumpBlif( Bbl_Man_t * p, char * pFileName );
extern void Bbl_ManSimpleDemo(); extern void Bbl_ManSimpleDemo();
#ifdef __cplusplus
}
#endif ABC_NAMESPACE_HEADER_END
#endif #endif

23
src/aig/bbr/bbr.h
View File

@ -21,22 +21,24 @@
#ifndef __BBR_H__ #ifndef __BBR_H__
#define __BBR_H__ #define __BBR_H__
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// INCLUDES /// /// INCLUDES ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
#include <stdio.h> #include <stdio.h>
#include "cuddInt.h"
#include "aig.h" #include "aig.h"
#include "saig.h" #include "saig.h"
#include "cuddInt.h"
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// PARAMETERS /// /// PARAMETERS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
extern "C" {
#endif ABC_NAMESPACE_HEADER_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// BASIC TYPES /// /// BASIC TYPES ///
@ -46,7 +48,7 @@ extern "C" {
/// MACRO DEFINITIONS /// /// MACRO DEFINITIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
static inline DdNode * Aig_ObjGlobalBdd( Aig_Obj_t * pObj ) { return pObj->pData; } static inline DdNode * Aig_ObjGlobalBdd( Aig_Obj_t * pObj ) { return (DdNode *)pObj->pData; }
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// FUNCTION DECLARATIONS /// /// FUNCTION DECLARATIONS ///
@ -74,11 +76,14 @@ extern void Aig_ManFreeGlobalBdds( Aig_Man_t * p, DdManager * dd );
extern int Aig_ManSizeOfGlobalBdds( Aig_Man_t * p ); extern int Aig_ManSizeOfGlobalBdds( Aig_Man_t * p );
extern DdManager * Aig_ManComputeGlobalBdds( Aig_Man_t * p, int nBddSizeMax, int fDropInternal, int fReorder, int fVerbose ); extern DdManager * Aig_ManComputeGlobalBdds( Aig_Man_t * p, int nBddSizeMax, int fDropInternal, int fReorder, int fVerbose );
/*=== bbrReach.c ==========================================================*/ /*=== bbrReach.c ==========================================================*/
extern int Aig_ManVerifyUsingBdds( Aig_Man_t * p, int nBddMax, int nIterMax, int fPartition, int fReorder, int fReorderImage, int fVerbose, int fSilent ); extern int Aig_ManVerifyUsingBdds( Aig_Man_t * p, Saig_ParBbr_t * pPars );
extern void Bbr_ManSetDefaultParams( Saig_ParBbr_t * p );
ABC_NAMESPACE_HEADER_END
#ifdef __cplusplus
}
#endif
#endif #endif

11
src/aig/bbr/bbrCex.c
View File

@ -21,6 +21,9 @@
#include "bbr.h" #include "bbr.h"
#include "ssw.h" #include "ssw.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -42,11 +45,11 @@ extern DdNode * Bbr_bddComputeRangeCube( DdManager * dd, int iStart, int iStop )
SeeAlso [] SeeAlso []
***********************************************************************/ ***********************************************************************/
Ssw_Cex_t * Aig_ManVerifyUsingBddsCountExample( Aig_Man_t * p, DdManager * dd, Abc_Cex_t * Aig_ManVerifyUsingBddsCountExample( Aig_Man_t * p, DdManager * dd,
DdNode ** pbParts, Vec_Ptr_t * vOnionRings, DdNode * bCubeFirst, DdNode ** pbParts, Vec_Ptr_t * vOnionRings, DdNode * bCubeFirst,
int iOutput, int fVerbose, int fSilent ) int iOutput, int fVerbose, int fSilent )
{ {
Ssw_Cex_t * pCex; Abc_Cex_t * pCex;
Aig_Obj_t * pObj; Aig_Obj_t * pObj;
Bbr_ImageTree_t * pTree; Bbr_ImageTree_t * pTree;
DdNode * bCubeNs, * bState, * bImage; DdNode * bCubeNs, * bState, * bImage;
@ -96,7 +99,7 @@ Ssw_Cex_t * Aig_ManVerifyUsingBddsCountExample( Aig_Man_t * p, DdManager * dd,
} }
// perform backward analysis // perform backward analysis
Vec_PtrForEachEntryReverse( vOnionRings, bRing, v ) Vec_PtrForEachEntryReverse( DdNode *, vOnionRings, bRing, v )
{ {
// compute the next states // compute the next states
bImage = Bbr_bddImageCompute( pTree, bState ); bImage = Bbr_bddImageCompute( pTree, bState );
@ -166,3 +169,5 @@ Ssw_Cex_t * Aig_ManVerifyUsingBddsCountExample( Aig_Man_t * p, DdManager * dd,
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

5
src/aig/bbr/bbrImage.c
View File

@ -21,6 +21,9 @@
#include "bbr.h" #include "bbr.h"
#include "mtr.h" #include "mtr.h"
ABC_NAMESPACE_IMPL_START
/* /*
The ideas implemented in this file are inspired by the paper: The ideas implemented in this file are inspired by the paper:
Pankaj Chauhan, Edmund Clarke, Somesh Jha, Jim Kukula, Tom Shiple, Pankaj Chauhan, Edmund Clarke, Somesh Jha, Jim Kukula, Tom Shiple,
@ -1320,3 +1323,5 @@ DdNode * Bbr_bddImageRead2( Bbr_ImageTree2_t * pTree )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

7
src/aig/bbr/bbrNtbdd.c
View File

@ -21,6 +21,9 @@
#include "bbr.h" #include "bbr.h"
//#include "bar.h" //#include "bar.h"
ABC_NAMESPACE_IMPL_START
typedef char ProgressBar; typedef char ProgressBar;
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -28,7 +31,7 @@ typedef char ProgressBar;
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
static inline void Aig_ObjSetGlobalBdd( Aig_Obj_t * pObj, DdNode * bFunc ) { pObj->pData = bFunc; } static inline void Aig_ObjSetGlobalBdd( Aig_Obj_t * pObj, DdNode * bFunc ) { pObj->pData = bFunc; }
static inline void Aig_ObjCleanGlobalBdd( DdManager * dd, Aig_Obj_t * pObj ) { Cudd_RecursiveDeref( dd, pObj->pData ); pObj->pData = NULL; } static inline void Aig_ObjCleanGlobalBdd( DdManager * dd, Aig_Obj_t * pObj ) { Cudd_RecursiveDeref( dd, (DdNode *)pObj->pData ); pObj->pData = NULL; }
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS /// /// FUNCTION DEFINITIONS ///
@ -211,3 +214,5 @@ DdManager * Aig_ManComputeGlobalBdds( Aig_Man_t * p, int nBddSizeMax, int fDropI
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

165
src/aig/bbr/bbrReach.c
View File

@ -21,11 +21,14 @@
#include "bbr.h" #include "bbr.h"
#include "ssw.h" #include "ssw.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
extern void * Aig_ManVerifyUsingBddsCountExample( Aig_Man_t * p, DdManager * dd, extern Abc_Cex_t * Aig_ManVerifyUsingBddsCountExample( Aig_Man_t * p, DdManager * dd,
DdNode ** pbParts, Vec_Ptr_t * vOnionRings, DdNode * bCubeFirst, DdNode ** pbParts, Vec_Ptr_t * vOnionRings, DdNode * bCubeFirst,
int iOutput, int fVerbose, int fSilent ); int iOutput, int fVerbose, int fSilent );
@ -33,6 +36,31 @@ extern void * Aig_ManVerifyUsingBddsCountExample( Aig_Man_t * p, DdManager * dd,
/// FUNCTION DEFINITIONS /// /// FUNCTION DEFINITIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [This procedure sets default resynthesis parameters.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Bbr_ManSetDefaultParams( Saig_ParBbr_t * p )
{
memset( p, 0, sizeof(Saig_ParBbr_t) );
p->TimeLimit = 0;
p->nBddMax = 50000;
p->nIterMax = 1000;
p->fPartition = 1;
p->fReorder = 1;
p->fReorderImage = 1;
p->fVerbose = 0;
p->fSilent = 0;
p->iFrame = -1;
}
/**Function******************************************************************** /**Function********************************************************************
Synopsis [Performs the reordering-sensitive step of Extra_bddMove().] Synopsis [Performs the reordering-sensitive step of Extra_bddMove().]
@ -208,7 +236,7 @@ DdNode ** Aig_ManCreatePartitions( DdManager * dd, Aig_Man_t * p, int fReorder,
SeeAlso [] SeeAlso []
***********************************************************************/ ***********************************************************************/
int Aig_ManComputeReachable( DdManager * dd, Aig_Man_t * p, DdNode ** pbParts, DdNode * bInitial, DdNode ** pbOutputs, int nBddMax, int nIterMax, int fPartition, int fReorder, int fVerbose, int fSilent ) int Aig_ManComputeReachable( DdManager * dd, Aig_Man_t * p, DdNode ** pbParts, DdNode * bInitial, DdNode ** pbOutputs, Saig_ParBbr_t * pPars, int fCheckOutputs )
{ {
int fInternalReorder = 0; int fInternalReorder = 0;
Bbr_ImageTree_t * pTree = NULL; // Suppress "might be used uninitialized" Bbr_ImageTree_t * pTree = NULL; // Suppress "might be used uninitialized"
@ -217,10 +245,10 @@ int Aig_ManComputeReachable( DdManager * dd, Aig_Man_t * p, DdNode ** pbParts, D
DdNode * bCurrent; DdNode * bCurrent;
DdNode * bNext = NULL; // Suppress "might be used uninitialized" DdNode * bNext = NULL; // Suppress "might be used uninitialized"
DdNode * bTemp; DdNode * bTemp;
int i, nIters, nBddSize; Cudd_ReorderingType method;
int nThreshold = 10000; int i, nIters, nBddSize, status;
int nThreshold = 10000, clk = clock();
Vec_Ptr_t * vOnionRings; Vec_Ptr_t * vOnionRings;
int status, method;
status = Cudd_ReorderingStatus( dd, &method ); status = Cudd_ReorderingStatus( dd, &method );
if ( status ) if ( status )
@ -228,14 +256,14 @@ int Aig_ManComputeReachable( DdManager * dd, Aig_Man_t * p, DdNode ** pbParts, D
// start the image computation // start the image computation
bCubeCs = Bbr_bddComputeRangeCube( dd, Saig_ManPiNum(p), Saig_ManCiNum(p) ); Cudd_Ref( bCubeCs ); bCubeCs = Bbr_bddComputeRangeCube( dd, Saig_ManPiNum(p), Saig_ManCiNum(p) ); Cudd_Ref( bCubeCs );
if ( fPartition ) if ( pPars->fPartition )
pTree = Bbr_bddImageStart( dd, bCubeCs, Saig_ManRegNum(p), pbParts, Saig_ManRegNum(p), dd->vars+Saig_ManCiNum(p), nBddMax, fVerbose ); pTree = Bbr_bddImageStart( dd, bCubeCs, Saig_ManRegNum(p), pbParts, Saig_ManRegNum(p), dd->vars+Saig_ManCiNum(p), pPars->nBddMax, pPars->fVerbose );
else else
pTree2 = Bbr_bddImageStart2( dd, bCubeCs, Saig_ManRegNum(p), pbParts, Saig_ManRegNum(p), dd->vars+Saig_ManCiNum(p), fVerbose ); pTree2 = Bbr_bddImageStart2( dd, bCubeCs, Saig_ManRegNum(p), pbParts, Saig_ManRegNum(p), dd->vars+Saig_ManCiNum(p), pPars->fVerbose );
Cudd_RecursiveDeref( dd, bCubeCs ); Cudd_RecursiveDeref( dd, bCubeCs );
if ( pTree == NULL ) if ( pTree == NULL )
{ {
if ( !fSilent ) if ( !pPars->fSilent )
printf( "BDDs blew up during qualitification scheduling. " ); printf( "BDDs blew up during qualitification scheduling. " );
return -1; return -1;
} }
@ -246,30 +274,46 @@ int Aig_ManComputeReachable( DdManager * dd, Aig_Man_t * p, DdNode ** pbParts, D
// start the onion rings // start the onion rings
vOnionRings = Vec_PtrAlloc( 1000 ); vOnionRings = Vec_PtrAlloc( 1000 );
// perform reachability analisys // perform reachability analysis
bCurrent = bInitial; Cudd_Ref( bCurrent ); bCurrent = bInitial; Cudd_Ref( bCurrent );
bReached = bInitial; Cudd_Ref( bReached ); bReached = bInitial; Cudd_Ref( bReached );
Vec_PtrPush( vOnionRings, bCurrent ); Cudd_Ref( bCurrent ); Vec_PtrPush( vOnionRings, bCurrent ); Cudd_Ref( bCurrent );
for ( nIters = 1; nIters <= nIterMax; nIters++ ) for ( nIters = 0; nIters < pPars->nIterMax; nIters++ )
{ {
// check the runtime limit
if ( pPars->TimeLimit && ((float)pPars->TimeLimit <= (float)(clock()-clk)/(float)(CLOCKS_PER_SEC)) )
{
printf( "Reached timeout after image computation (%d seconds).\n", pPars->TimeLimit );
Vec_PtrFree( vOnionRings );
// undo the image tree
if ( pPars->fPartition )
Bbr_bddImageTreeDelete( pTree );
else
Bbr_bddImageTreeDelete2( pTree2 );
pPars->iFrame = nIters - 1;
return -1;
}
// compute the next states // compute the next states
if ( fPartition ) if ( pPars->fPartition )
bNext = Bbr_bddImageCompute( pTree, bCurrent ); bNext = Bbr_bddImageCompute( pTree, bCurrent );
else else
bNext = Bbr_bddImageCompute2( pTree2, bCurrent ); bNext = Bbr_bddImageCompute2( pTree2, bCurrent );
if ( bNext == NULL ) if ( bNext == NULL )
{ {
if ( !fSilent ) if ( !pPars->fSilent )
printf( "BDDs blew up during image computation. " ); printf( "BDDs blew up during image computation. " );
if ( fPartition ) if ( pPars->fPartition )
Bbr_bddImageTreeDelete( pTree ); Bbr_bddImageTreeDelete( pTree );
else else
Bbr_bddImageTreeDelete2( pTree2 ); Bbr_bddImageTreeDelete2( pTree2 );
Vec_PtrFree( vOnionRings ); Vec_PtrFree( vOnionRings );
pPars->iFrame = nIters - 1;
return -1; return -1;
} }
Cudd_Ref( bNext ); Cudd_Ref( bNext );
Cudd_RecursiveDeref( dd, bCurrent ); Cudd_RecursiveDeref( dd, bCurrent );
// remap these states into the current state vars // remap these states into the current state vars
bNext = Cudd_bddVarMap( dd, bTemp = bNext ); Cudd_Ref( bNext ); bNext = Cudd_bddVarMap( dd, bTemp = bNext ); Cudd_Ref( bNext );
Cudd_RecursiveDeref( dd, bTemp ); Cudd_RecursiveDeref( dd, bTemp );
@ -278,23 +322,24 @@ int Aig_ManComputeReachable( DdManager * dd, Aig_Man_t * p, DdNode ** pbParts, D
break; break;
// check the BDD size // check the BDD size
nBddSize = Cudd_DagSize(bNext); nBddSize = Cudd_DagSize(bNext);
if ( nBddSize > nBddMax ) if ( nBddSize > pPars->nBddMax )
break; break;
// check the result // check the result
for ( i = 0; i < Saig_ManPoNum(p); i++ ) for ( i = 0; i < Saig_ManPoNum(p); i++ )
{ {
if ( !Cudd_bddLeq( dd, bNext, Cudd_Not(pbOutputs[i]) ) ) if ( fCheckOutputs && !Cudd_bddLeq( dd, bNext, Cudd_Not(pbOutputs[i]) ) )
{ {
DdNode * bIntersect; DdNode * bIntersect;
bIntersect = Cudd_bddIntersect( dd, bNext, pbOutputs[i] ); Cudd_Ref( bIntersect ); bIntersect = Cudd_bddIntersect( dd, bNext, pbOutputs[i] ); Cudd_Ref( bIntersect );
assert( p->pSeqModel == NULL ); assert( p->pSeqModel == NULL );
p->pSeqModel = Aig_ManVerifyUsingBddsCountExample( p, dd, pbParts, p->pSeqModel = Aig_ManVerifyUsingBddsCountExample( p, dd, pbParts,
vOnionRings, bIntersect, i, fVerbose, fSilent ); vOnionRings, bIntersect, i, pPars->fVerbose, pPars->fSilent );
Cudd_RecursiveDeref( dd, bIntersect ); Cudd_RecursiveDeref( dd, bIntersect );
if ( !fSilent ) if ( !pPars->fSilent )
printf( "Output %d was asserted in frame %d (use \"write_counter\" to dump a witness). ", i, Vec_PtrSize(vOnionRings) ); printf( "Output %d was asserted in frame %d (use \"write_counter\" to dump a witness). ", i, Vec_PtrSize(vOnionRings) );
Cudd_RecursiveDeref( dd, bReached ); Cudd_RecursiveDeref( dd, bReached );
bReached = NULL; bReached = NULL;
pPars->iFrame = nIters;
break; break;
} }
} }
@ -310,38 +355,39 @@ int Aig_ManComputeReachable( DdManager * dd, Aig_Man_t * p, DdNode ** pbParts, D
bReached = Cudd_bddOr( dd, bTemp = bReached, bNext ); Cudd_Ref( bReached ); bReached = Cudd_bddOr( dd, bTemp = bReached, bNext ); Cudd_Ref( bReached );
Cudd_RecursiveDeref( dd, bTemp ); Cudd_RecursiveDeref( dd, bTemp );
Cudd_RecursiveDeref( dd, bNext ); Cudd_RecursiveDeref( dd, bNext );
if ( fVerbose ) if ( pPars->fVerbose )
fprintf( stdout, "Frame = %3d. BDD = %5d. ", nIters, nBddSize ); fprintf( stdout, "Frame = %3d. BDD = %5d. ", nIters, nBddSize );
if ( fInternalReorder && fReorder && nBddSize > nThreshold ) if ( fInternalReorder && pPars->fReorder && nBddSize > nThreshold )
{ {
if ( fVerbose ) if ( pPars->fVerbose )
fprintf( stdout, "Reordering... Before = %5d. ", Cudd_DagSize(bReached) ); fprintf( stdout, "Reordering... Before = %5d. ", Cudd_DagSize(bReached) );
Cudd_ReduceHeap( dd, CUDD_REORDER_SYMM_SIFT, 100 ); Cudd_ReduceHeap( dd, CUDD_REORDER_SYMM_SIFT, 100 );
Cudd_AutodynDisable( dd ); Cudd_AutodynDisable( dd );
if ( fVerbose ) if ( pPars->fVerbose )
fprintf( stdout, "After = %5d.\r", Cudd_DagSize(bReached) ); fprintf( stdout, "After = %5d.\r", Cudd_DagSize(bReached) );
nThreshold *= 2; nThreshold *= 2;
} }
if ( fVerbose ) if ( pPars->fVerbose )
fprintf( stdout, "\r" ); // fprintf( stdout, "\r" );
fprintf( stdout, "\n" );
} }
Cudd_RecursiveDeref( dd, bNext ); Cudd_RecursiveDeref( dd, bNext );
// free the onion rings // free the onion rings
Vec_PtrForEachEntry( vOnionRings, bTemp, i ) Vec_PtrForEachEntry( DdNode *, vOnionRings, bTemp, i )
Cudd_RecursiveDeref( dd, bTemp ); Cudd_RecursiveDeref( dd, bTemp );
Vec_PtrFree( vOnionRings ); Vec_PtrFree( vOnionRings );
// undo the image tree // undo the image tree
if ( fPartition ) if ( pPars->fPartition )
Bbr_bddImageTreeDelete( pTree ); Bbr_bddImageTreeDelete( pTree );
else else
Bbr_bddImageTreeDelete2( pTree2 ); Bbr_bddImageTreeDelete2( pTree2 );
if ( bReached == NULL ) if ( bReached == NULL )
return 0; // proved reachable return 0; // proved reachable
// report the stats // report the stats
if ( fVerbose ) if ( pPars->fVerbose )
{ {
double nMints = Cudd_CountMinterm(dd, bReached, Saig_ManRegNum(p) ); double nMints = Cudd_CountMinterm(dd, bReached, Saig_ManRegNum(p) );
if ( nIters > nIterMax || Cudd_DagSize(bReached) > nBddMax ) if ( nIters > pPars->nIterMax || nBddSize > pPars->nBddMax )
fprintf( stdout, "Reachability analysis is stopped after %d frames.\n", nIters ); fprintf( stdout, "Reachability analysis is stopped after %d frames.\n", nIters );
else else
fprintf( stdout, "Reachability analysis completed after %d frames.\n", nIters ); fprintf( stdout, "Reachability analysis completed after %d frames.\n", nIters );
@ -350,14 +396,15 @@ int Aig_ManComputeReachable( DdManager * dd, Aig_Man_t * p, DdNode ** pbParts, D
} }
//ABC_PRB( dd, bReached ); //ABC_PRB( dd, bReached );
Cudd_RecursiveDeref( dd, bReached ); Cudd_RecursiveDeref( dd, bReached );
if ( nIters > nIterMax || Cudd_DagSize(bReached) > nBddMax ) if ( nIters > pPars->nIterMax || nBddSize > pPars->nBddMax )
{ {
if ( !fSilent ) if ( !pPars->fSilent )
printf( "Verified only for states reachable in %d frames. ", nIters ); printf( "Verified only for states reachable in %d frames. ", nIters );
return -1; // undecided return -1; // undecided
} }
if ( !fSilent ) if ( !pPars->fSilent )
printf( "The miter is proved unreachable after %d iterations. ", nIters ); printf( "The miter is proved unreachable after %d iterations. ", nIters );
pPars->iFrame = nIters - 1;
return 1; // unreachable return 1; // unreachable
} }
@ -372,8 +419,9 @@ int Aig_ManComputeReachable( DdManager * dd, Aig_Man_t * p, DdNode ** pbParts, D
SeeAlso [] SeeAlso []
***********************************************************************/ ***********************************************************************/
int Aig_ManVerifyUsingBdds_int( Aig_Man_t * p, int nBddMax, int nIterMax, int fPartition, int fReorder, int fReorderImage, int fVerbose, int fSilent ) int Aig_ManVerifyUsingBdds_int( Aig_Man_t * p, Saig_ParBbr_t * pPars )
{ {
int fCheckOutputs = !pPars->fSkipOutCheck;
DdManager * dd; DdManager * dd;
DdNode ** pbParts, ** pbOutputs; DdNode ** pbParts, ** pbOutputs;
DdNode * bInitial, * bTemp; DdNode * bInitial, * bTemp;
@ -383,16 +431,24 @@ int Aig_ManVerifyUsingBdds_int( Aig_Man_t * p, int nBddMax, int nIterMax, int fP
assert( Saig_ManRegNum(p) > 0 ); assert( Saig_ManRegNum(p) > 0 );
// compute the global BDDs of the latches // compute the global BDDs of the latches
dd = Aig_ManComputeGlobalBdds( p, nBddMax, 1, fReorder, fVerbose ); dd = Aig_ManComputeGlobalBdds( p, pPars->nBddMax, 1, pPars->fReorder, pPars->fVerbose );
if ( dd == NULL ) if ( dd == NULL )
{ {
if ( !fSilent ) if ( !pPars->fSilent )
printf( "The number of intermediate BDD nodes exceeded the limit (%d).\n", nBddMax ); printf( "The number of intermediate BDD nodes exceeded the limit (%d).\n", pPars->nBddMax );
return -1; return -1;
} }
if ( fVerbose ) if ( pPars->fVerbose )
printf( "Shared BDD size is %6d nodes.\n", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) ); printf( "Shared BDD size is %6d nodes.\n", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
// check the runtime limit
if ( pPars->TimeLimit && ((float)pPars->TimeLimit <= (float)(clock()-clk)/(float)(CLOCKS_PER_SEC)) )
{
printf( "Reached timeout after constructing global BDDs (%d seconds).\n", pPars->TimeLimit );
Cudd_Quit( dd );
return -1;
}
// start the onion rings // start the onion rings
vOnionRings = Vec_PtrAlloc( 1000 ); vOnionRings = Vec_PtrAlloc( 1000 );
@ -400,40 +456,40 @@ int Aig_ManVerifyUsingBdds_int( Aig_Man_t * p, int nBddMax, int nIterMax, int fP
pbOutputs = Aig_ManCreateOutputs( dd, p ); pbOutputs = Aig_ManCreateOutputs( dd, p );
// create partitions // create partitions
pbParts = Aig_ManCreatePartitions( dd, p, fReorder, fVerbose ); pbParts = Aig_ManCreatePartitions( dd, p, pPars->fReorder, pPars->fVerbose );
// create the initial state and the variable map // create the initial state and the variable map
bInitial = Aig_ManInitStateVarMap( dd, p, fVerbose ); Cudd_Ref( bInitial ); bInitial = Aig_ManInitStateVarMap( dd, p, pPars->fVerbose ); Cudd_Ref( bInitial );
// set reordering // set reordering
if ( fReorderImage ) if ( pPars->fReorderImage )
Cudd_AutodynEnable( dd, CUDD_REORDER_SYMM_SIFT ); Cudd_AutodynEnable( dd, CUDD_REORDER_SYMM_SIFT );
// check the result // check the result
RetValue = -1; RetValue = -1;
for ( i = 0; i < Saig_ManPoNum(p); i++ ) for ( i = 0; i < Saig_ManPoNum(p); i++ )
{ {
if ( !Cudd_bddLeq( dd, bInitial, Cudd_Not(pbOutputs[i]) ) ) if ( fCheckOutputs && !Cudd_bddLeq( dd, bInitial, Cudd_Not(pbOutputs[i]) ) )
{ {
DdNode * bIntersect; DdNode * bIntersect;
bIntersect = Cudd_bddIntersect( dd, bInitial, pbOutputs[i] ); Cudd_Ref( bIntersect ); bIntersect = Cudd_bddIntersect( dd, bInitial, pbOutputs[i] ); Cudd_Ref( bIntersect );
assert( p->pSeqModel == NULL ); assert( p->pSeqModel == NULL );
p->pSeqModel = Aig_ManVerifyUsingBddsCountExample( p, dd, pbParts, p->pSeqModel = Aig_ManVerifyUsingBddsCountExample( p, dd, pbParts,
vOnionRings, bIntersect, i, fVerbose, fSilent ); vOnionRings, bIntersect, i, pPars->fVerbose, pPars->fSilent );
Cudd_RecursiveDeref( dd, bIntersect ); Cudd_RecursiveDeref( dd, bIntersect );
if ( !fSilent ) if ( !pPars->fSilent )
printf( "The miter output %d is proved REACHABLE in the initial state (use \"write_counter\" to dump a witness). ", i ); printf( "The miter output %d is proved REACHABLE in the initial state (use \"write_counter\" to dump a witness). ", i );
RetValue = 0; RetValue = 0;
break; break;
} }
} }
// free the onion rings // free the onion rings
Vec_PtrForEachEntry( vOnionRings, bTemp, i ) Vec_PtrForEachEntry( DdNode *, vOnionRings, bTemp, i )
Cudd_RecursiveDeref( dd, bTemp ); Cudd_RecursiveDeref( dd, bTemp );
Vec_PtrFree( vOnionRings ); Vec_PtrFree( vOnionRings );
// explore reachable states // explore reachable states
if ( RetValue == -1 ) if ( RetValue == -1 )
RetValue = Aig_ManComputeReachable( dd, p, pbParts, bInitial, pbOutputs, nBddMax, nIterMax, fPartition, fReorder, fVerbose, fSilent ); RetValue = Aig_ManComputeReachable( dd, p, pbParts, bInitial, pbOutputs, pPars, fCheckOutputs );
// cleanup // cleanup
Cudd_RecursiveDeref( dd, bInitial ); Cudd_RecursiveDeref( dd, bInitial );
@ -443,13 +499,13 @@ int Aig_ManVerifyUsingBdds_int( Aig_Man_t * p, int nBddMax, int nIterMax, int fP
for ( i = 0; i < Saig_ManPoNum(p); i++ ) for ( i = 0; i < Saig_ManPoNum(p); i++ )
Cudd_RecursiveDeref( dd, pbOutputs[i] ); Cudd_RecursiveDeref( dd, pbOutputs[i] );
ABC_FREE( pbOutputs ); ABC_FREE( pbOutputs );
if ( RetValue == -1 ) // if ( RetValue == -1 )
Cudd_Quit( dd ); Cudd_Quit( dd );
else // else
Bbr_StopManager( dd ); // Bbr_StopManager( dd );
// report the runtime // report the runtime
if ( !fSilent ) if ( !pPars->fSilent )
{ {
ABC_PRT( "Time", clock() - clk ); ABC_PRT( "Time", clock() - clk );
fflush( stdout ); fflush( stdout );
@ -468,24 +524,25 @@ int Aig_ManVerifyUsingBdds_int( Aig_Man_t * p, int nBddMax, int nIterMax, int fP
SeeAlso [] SeeAlso []
***********************************************************************/ ***********************************************************************/
int Aig_ManVerifyUsingBdds( Aig_Man_t * pInit, int nBddMax, int nIterMax, int fPartition, int fReorder, int fReorderImage, int fVerbose, int fSilent ) int Aig_ManVerifyUsingBdds( Aig_Man_t * pInit, Saig_ParBbr_t * pPars )
{ {
Ssw_Cex_t * pCexOld, * pCexNew; Abc_Cex_t * pCexOld, * pCexNew;
Aig_Man_t * p; Aig_Man_t * p;
Aig_Obj_t * pObj; Aig_Obj_t * pObj;
Vec_Int_t * vInputMap; Vec_Int_t * vInputMap;
int i, k, Entry, iBitOld, iBitNew, RetValue; int i, k, Entry, iBitOld, iBitNew, RetValue;
// pPars->fVerbose = 1;
// check if there are PIs without fanout // check if there are PIs without fanout
Saig_ManForEachPi( pInit, pObj, i ) Saig_ManForEachPi( pInit, pObj, i )
if ( Aig_ObjRefs(pObj) == 0 ) if ( Aig_ObjRefs(pObj) == 0 )
break; break;
if ( i == Saig_ManPiNum(pInit) ) if ( i == Saig_ManPiNum(pInit) )
return Aig_ManVerifyUsingBdds_int( pInit, nBddMax, nIterMax, fPartition, fReorder, fReorderImage, fVerbose, fSilent ); return Aig_ManVerifyUsingBdds_int( pInit, pPars );
// create new AIG // create new AIG
p = Aig_ManDupTrim( pInit ); p = Aig_ManDupTrim( pInit );
assert( Aig_ManPiNum(p) < Aig_ManPiNum(pInit) ); assert( Aig_ManPiNum(p) < Aig_ManPiNum(pInit) );
assert( Aig_ManRegNum(p) == Aig_ManRegNum(pInit) ); assert( Aig_ManRegNum(p) == Aig_ManRegNum(pInit) );
RetValue = Aig_ManVerifyUsingBdds_int( p, nBddMax, nIterMax, fPartition, fReorder, fReorderImage, fVerbose, fSilent ); RetValue = Aig_ManVerifyUsingBdds_int( p, pPars );
if ( RetValue != 0 ) if ( RetValue != 0 )
{ {
Aig_ManStop( p ); Aig_ManStop( p );
@ -498,7 +555,7 @@ int Aig_ManVerifyUsingBdds( Aig_Man_t * pInit, int nBddMax, int nIterMax, int fP
vInputMap = Vec_IntAlloc( Saig_ManPiNum(pInit) ); vInputMap = Vec_IntAlloc( Saig_ManPiNum(pInit) );
Saig_ManForEachPi( pInit, pObj, i ) Saig_ManForEachPi( pInit, pObj, i )
if ( pObj->pData != NULL ) if ( pObj->pData != NULL )
Vec_IntPush( vInputMap, Aig_ObjPioNum(pObj->pData) ); Vec_IntPush( vInputMap, Aig_ObjPioNum((Aig_Obj_t *)pObj->pData) );
else else
Vec_IntPush( vInputMap, -1 ); Vec_IntPush( vInputMap, -1 );
// create new pattern // create new pattern
@ -537,3 +594,5 @@ int Aig_ManVerifyUsingBdds( Aig_Man_t * pInit, int nBddMax, int nIterMax, int fP
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

5
src/aig/bbr/bbr_.c
View File

@ -20,6 +20,9 @@
#include "__Int.h" #include "__Int.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -45,3 +48,5 @@
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

17
src/aig/bdc/bdc.h
View File

@ -21,6 +21,7 @@
#ifndef __BDC_H__ #ifndef __BDC_H__
#define __BDC_H__ #define __BDC_H__
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// INCLUDES /// /// INCLUDES ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -29,9 +30,10 @@
/// PARAMETERS /// /// PARAMETERS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
extern "C" {
#endif ABC_NAMESPACE_HEADER_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// BASIC TYPES /// /// BASIC TYPES ///
@ -72,12 +74,15 @@ extern int Bdc_ManNodeNum( Bdc_Man_t * p );
extern Bdc_Fun_t * Bdc_FuncFanin0( Bdc_Fun_t * p ); extern Bdc_Fun_t * Bdc_FuncFanin0( Bdc_Fun_t * p );
extern Bdc_Fun_t * Bdc_FuncFanin1( Bdc_Fun_t * p ); extern Bdc_Fun_t * Bdc_FuncFanin1( Bdc_Fun_t * p );
extern void * Bdc_FuncCopy( Bdc_Fun_t * p ); extern void * Bdc_FuncCopy( Bdc_Fun_t * p );
extern int Bdc_FuncCopyInt( Bdc_Fun_t * p );
extern void Bdc_FuncSetCopy( Bdc_Fun_t * p, void * pCopy ); extern void Bdc_FuncSetCopy( Bdc_Fun_t * p, void * pCopy );
extern void Bdc_FuncSetCopyInt( Bdc_Fun_t * p, int iCopy );
ABC_NAMESPACE_HEADER_END
#ifdef __cplusplus
}
#endif
#endif #endif

11
src/aig/bdc/bdcCore.c
View File

@ -20,6 +20,9 @@
#include "bdcInt.h" #include "bdcInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -46,7 +49,9 @@ int Bdc_ManNodeNum( Bdc_Man_t * p ) { return p->nNode
Bdc_Fun_t * Bdc_FuncFanin0( Bdc_Fun_t * p ) { return p->pFan0; } Bdc_Fun_t * Bdc_FuncFanin0( Bdc_Fun_t * p ) { return p->pFan0; }
Bdc_Fun_t * Bdc_FuncFanin1( Bdc_Fun_t * p ) { return p->pFan1; } Bdc_Fun_t * Bdc_FuncFanin1( Bdc_Fun_t * p ) { return p->pFan1; }
void * Bdc_FuncCopy( Bdc_Fun_t * p ) { return p->pCopy; } void * Bdc_FuncCopy( Bdc_Fun_t * p ) { return p->pCopy; }
int Bdc_FuncCopyInt( Bdc_Fun_t * p ) { return p->iCopy; }
void Bdc_FuncSetCopy( Bdc_Fun_t * p, void * pCopy ) { p->pCopy = pCopy; } void Bdc_FuncSetCopy( Bdc_Fun_t * p, void * pCopy ) { p->pCopy = pCopy; }
void Bdc_FuncSetCopyInt( Bdc_Fun_t * p, int iCopy ) { p->iCopy = iCopy; }
/**Function************************************************************* /**Function*************************************************************
@ -160,13 +165,13 @@ void Bdc_ManPrepare( Bdc_Man_t * p, Vec_Ptr_t * vDivs )
{ {
pNode = Bdc_FunNew( p ); pNode = Bdc_FunNew( p );
pNode->Type = BDC_TYPE_PI; pNode->Type = BDC_TYPE_PI;
pNode->puFunc = Vec_PtrEntry( p->vTruths, i ); pNode->puFunc = (unsigned *)Vec_PtrEntry( p->vTruths, i );
pNode->uSupp = (1 << i); pNode->uSupp = (1 << i);
Bdc_TableAdd( p, pNode ); Bdc_TableAdd( p, pNode );
} }
// add the divisors // add the divisors
if ( vDivs ) if ( vDivs )
Vec_PtrForEachEntry( vDivs, puTruth, i ) Vec_PtrForEachEntry( unsigned *, vDivs, puTruth, i )
{ {
pNode = Bdc_FunNew( p ); pNode = Bdc_FunNew( p );
pNode->Type = BDC_TYPE_PI; pNode->Type = BDC_TYPE_PI;
@ -305,3 +310,5 @@ void Bdc_ManDecomposeTest( unsigned uTruth, int nVars )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

5
src/aig/bdc/bdcDec.c
View File

@ -20,6 +20,9 @@
#include "bdcInt.h" #include "bdcInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -744,3 +747,5 @@ Extra_PrintBinary( stdout, pIsf->puOff, 1<<4 );printf("\n");
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

20
src/aig/bdc/bdcInt.h
View File

@ -21,6 +21,7 @@
#ifndef __BDC_INT_H__ #ifndef __BDC_INT_H__
#define __BDC_INT_H__ #define __BDC_INT_H__
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// INCLUDES /// /// INCLUDES ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -32,9 +33,10 @@
/// PARAMETERS /// /// PARAMETERS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
extern "C" {
#endif ABC_NAMESPACE_HEADER_START
#define BDC_SCALE 1000 // value used to compute the cost #define BDC_SCALE 1000 // value used to compute the cost
@ -62,7 +64,9 @@ struct Bdc_Fun_t_
unsigned uSupp; // bit mask of current support unsigned uSupp; // bit mask of current support
unsigned * puFunc; // the function of the node unsigned * puFunc; // the function of the node
Bdc_Fun_t * pNext; // next function with same support Bdc_Fun_t * pNext; // next function with same support
void * pCopy; // the copy field union { int iCopy; // the literal of the node (AIG)
void * pCopy; }; // the function of the node (BDD or AIG)
}; };
typedef struct Bdc_Isf_t_ Bdc_Isf_t; typedef struct Bdc_Isf_t_ Bdc_Isf_t;
@ -147,9 +151,11 @@ extern void Bdc_TableAdd( Bdc_Man_t * p, Bdc_Fun_t * pFunc );
extern void Bdc_TableClear( Bdc_Man_t * p ); extern void Bdc_TableClear( Bdc_Man_t * p );
extern int Bdc_TableCheckContainment( Bdc_Man_t * p, Bdc_Isf_t * pIsf, unsigned * puTruth ); extern int Bdc_TableCheckContainment( Bdc_Man_t * p, Bdc_Isf_t * pIsf, unsigned * puTruth );
#ifdef __cplusplus
}
#endif ABC_NAMESPACE_HEADER_END
#endif #endif

5
src/aig/bdc/bdcTable.c
View File

@ -20,6 +20,9 @@
#include "bdcInt.h" #include "bdcInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -127,3 +130,5 @@ void Bdc_TableClear( Bdc_Man_t * p )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

5
src/aig/bdc/bdc_.c
View File

@ -20,6 +20,9 @@
#include "bdcInt.h" #include "bdcInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -47,3 +50,5 @@
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

5
src/aig/cec/cec.c
View File

@ -20,6 +20,9 @@
#include "cecInt.h" #include "cecInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -46,3 +49,5 @@
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

50
src/aig/cec/cec.h
View File

@ -21,6 +21,7 @@
#ifndef __CEC_H__ #ifndef __CEC_H__
#define __CEC_H__ #define __CEC_H__
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// INCLUDES /// /// INCLUDES ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -29,9 +30,10 @@
/// PARAMETERS /// /// PARAMETERS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
extern "C" {
#endif ABC_NAMESPACE_HEADER_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// BASIC TYPES /// /// BASIC TYPES ///
@ -103,8 +105,10 @@ struct Cec_ParFra_t_
// int fFirstStop; // stop on the first sat output // int fFirstStop; // stop on the first sat output
int fDualOut; // miter with separate outputs int fDualOut; // miter with separate outputs
int fColorDiff; // miter with separate outputs int fColorDiff; // miter with separate outputs
int fSatSweeping; // enable SAT sweeping
int fVeryVerbose; // verbose stats int fVeryVerbose; // verbose stats
int fVerbose; // verbose stats int fVerbose; // verbose stats
int iOutFail; // the failed output
}; };
// combinational equivalence checking parameters // combinational equivalence checking parameters
@ -118,6 +122,7 @@ struct Cec_ParCec_t_
int fRewriting; // enables AIG rewriting int fRewriting; // enables AIG rewriting
int fVeryVerbose; // verbose stats int fVeryVerbose; // verbose stats
int fVerbose; // verbose stats int fVerbose; // verbose stats
int iOutFail; // the number of failed output
}; };
// sequential register correspodence parameters // sequential register correspodence parameters
@ -129,6 +134,8 @@ struct Cec_ParCor_t_
int nFrames; // the number of time frames int nFrames; // the number of time frames
int nPrefix; // the number of time frames in the prefix int nPrefix; // the number of time frames in the prefix
int nBTLimit; // conflict limit at a node int nBTLimit; // conflict limit at a node
int nLevelMax; // (scorr only) the max number of levels
int nStepsMax; // (scorr only) the max number of induction steps
int fLatchCorr; // consider only latch outputs int fLatchCorr; // consider only latch outputs
int fUseRings; // use rings int fUseRings; // use rings
int fMakeChoices; // use equilvaences as choices int fMakeChoices; // use equilvaences as choices
@ -138,6 +145,9 @@ struct Cec_ParCor_t_
int fVerboseFlops; // verbose stats int fVerboseFlops; // verbose stats
int fVeryVerbose; // verbose stats int fVeryVerbose; // verbose stats
int fVerbose; // verbose stats int fVerbose; // verbose stats
// callback
void * pData;
void * pFunc;
}; };
// sequential register correspodence parameters // sequential register correspodence parameters
@ -153,6 +163,23 @@ struct Cec_ParChc_t_
int fVerbose; // verbose stats int fVerbose; // verbose stats
}; };
// sequential synthesis parameters
typedef struct Cec_ParSeq_t_ Cec_ParSeq_t;
struct Cec_ParSeq_t_
{
int fUseLcorr; // enables latch correspondence
int fUseScorr; // enables signal correspondence
int nBTLimit; // (scorr/lcorr) conflict limit at a node
int nFrames; // (scorr/lcorr) the number of timeframes
int nLevelMax; // (scorr only) the max number of levels
int fConsts; // (scl only) merging constants
int fEquivs; // (scl only) merging equivalences
int fUseMiniSat; // enables MiniSat in lcorr/scorr
int nMinDomSize; // the size of minimum clock domain
int fVeryVerbose; // verbose stats
int fVerbose; // verbose stats
};
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// MACRO DEFINITIONS /// /// MACRO DEFINITIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -167,6 +194,7 @@ extern int Cec_ManVerifyTwo( Gia_Man_t * p0, Gia_Man_t * p1, int fVerb
/*=== cecChoice.c ==========================================================*/ /*=== cecChoice.c ==========================================================*/
extern Gia_Man_t * Cec_ManChoiceComputation( Gia_Man_t * pAig, Cec_ParChc_t * pPars ); extern Gia_Man_t * Cec_ManChoiceComputation( Gia_Man_t * pAig, Cec_ParChc_t * pPars );
/*=== cecCorr.c ==========================================================*/ /*=== cecCorr.c ==========================================================*/
extern int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars );
extern Gia_Man_t * Cec_ManLSCorrespondence( Gia_Man_t * pAig, Cec_ParCor_t * pPars ); extern Gia_Man_t * Cec_ManLSCorrespondence( Gia_Man_t * pAig, Cec_ParCor_t * pPars );
/*=== cecCore.c ==========================================================*/ /*=== cecCore.c ==========================================================*/
extern void Cec_ManSatSetDefaultParams( Cec_ParSat_t * p ); extern void Cec_ManSatSetDefaultParams( Cec_ParSat_t * p );
@ -180,12 +208,20 @@ extern Gia_Man_t * Cec_ManSatSweeping( Gia_Man_t * pAig, Cec_ParFra_t * pPars
extern Gia_Man_t * Cec_ManSatSolving( Gia_Man_t * pAig, Cec_ParSat_t * pPars ); extern Gia_Man_t * Cec_ManSatSolving( Gia_Man_t * pAig, Cec_ParSat_t * pPars );
extern void Cec_ManSimulation( Gia_Man_t * pAig, Cec_ParSim_t * pPars ); extern void Cec_ManSimulation( Gia_Man_t * pAig, Cec_ParSim_t * pPars );
/*=== cecSeq.c ==========================================================*/ /*=== cecSeq.c ==========================================================*/
extern int Cec_ManSeqResimulateCounter( Gia_Man_t * pAig, Cec_ParSim_t * pPars, Gia_Cex_t * pCex ); extern int Cec_ManSeqResimulateCounter( Gia_Man_t * pAig, Cec_ParSim_t * pPars, Abc_Cex_t * pCex );
extern int Cec_ManSeqSemiformal( Gia_Man_t * pAig, Cec_ParSmf_t * pPars ); extern int Cec_ManSeqSemiformal( Gia_Man_t * pAig, Cec_ParSmf_t * pPars );
extern int Cec_ManCheckNonTrivialCands( Gia_Man_t * pAig );
/*=== cecSynth.c ==========================================================*/
extern int Cec_SeqReadMinDomSize( Cec_ParSeq_t * p );
extern int Cec_SeqReadVerbose( Cec_ParSeq_t * p );
extern void Cec_SeqSynthesisSetDefaultParams( Cec_ParSeq_t * pPars );
extern int Cec_SequentialSynthesisPart( Gia_Man_t * p, Cec_ParSeq_t * pPars );
ABC_NAMESPACE_HEADER_END
#ifdef __cplusplus
}
#endif
#endif #endif

122
src/aig/cec/cecCec.c
View File

@ -19,8 +19,12 @@
***********************************************************************/ ***********************************************************************/
#include "cecInt.h" #include "cecInt.h"
#include "fra.h"
#include "giaAig.h" #include "giaAig.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -44,8 +48,8 @@ void Cec_ManTransformPattern( Gia_Man_t * p, int iOut, int * pValues )
{ {
int i; int i;
assert( p->pCexComb == NULL ); assert( p->pCexComb == NULL );
p->pCexComb = (Gia_Cex_t *)ABC_CALLOC( char, p->pCexComb = (Abc_Cex_t *)ABC_CALLOC( char,
sizeof(Gia_Cex_t) + sizeof(unsigned) * Gia_BitWordNum(Gia_ManCiNum(p)) ); sizeof(Abc_Cex_t) + sizeof(unsigned) * Gia_BitWordNum(Gia_ManCiNum(p)) );
p->pCexComb->iPo = iOut; p->pCexComb->iPo = iOut;
p->pCexComb->nPis = Gia_ManCiNum(p); p->pCexComb->nPis = Gia_ManCiNum(p);
p->pCexComb->nBits = Gia_ManCiNum(p); p->pCexComb->nBits = Gia_ManCiNum(p);
@ -65,45 +69,53 @@ void Cec_ManTransformPattern( Gia_Man_t * p, int iOut, int * pValues )
SeeAlso [] SeeAlso []
***********************************************************************/ ***********************************************************************/
int Cec_ManVerifyOld( Gia_Man_t * pMiter, int fVerbose ) int Cec_ManVerifyOld( Gia_Man_t * pMiter, int fVerbose, int * piOutFail )
{ {
extern int Fra_FraigCec( Aig_Man_t ** ppAig, int nConfLimit, int fVerbose ); // extern int Fra_FraigCec( Aig_Man_t ** ppAig, int nConfLimit, int fVerbose );
extern int Ssw_SecCexResimulate( Aig_Man_t * p, int * pModel, int * pnOutputs ); extern int Ssw_SecCexResimulate( Aig_Man_t * p, int * pModel, int * pnOutputs );
Gia_Man_t * pTemp = Gia_ManTransformMiter( pMiter ); Gia_Man_t * pTemp = Gia_ManTransformMiter( pMiter );
Aig_Man_t * pMiterCec = Gia_ManToAig( pTemp, 0 ); Aig_Man_t * pMiterCec = Gia_ManToAig( pTemp, 0 );
int RetValue, iOut, nOuts, clkTotal = clock(); int RetValue, iOut, nOuts, clkTotal = clock();
if ( piOutFail )
*piOutFail = -1;
Gia_ManStop( pTemp ); Gia_ManStop( pTemp );
// run CEC on this miter // run CEC on this miter
RetValue = Fra_FraigCec( &pMiterCec, 100000, fVerbose ); RetValue = Fra_FraigCec( &pMiterCec, 10000000, fVerbose );
// report the miter // report the miter
if ( RetValue == 1 ) if ( RetValue == 1 )
{ {
printf( "Networks are equivalent. " ); Abc_Print( 1, "Networks are equivalent. " );
ABC_PRT( "Time", clock() - clkTotal ); Abc_PrintTime( 1, "Time", clock() - clkTotal );
} }
else if ( RetValue == 0 ) else if ( RetValue == 0 )
{ {
printf( "Networks are NOT EQUIVALENT. " ); Abc_Print( 1, "Networks are NOT EQUIVALENT. " );
ABC_PRT( "Time", clock() - clkTotal ); Abc_PrintTime( 1, "Time", clock() - clkTotal );
if ( pMiterCec->pData == NULL ) if ( pMiterCec->pData == NULL )
printf( "Counter-example is not available.\n" ); Abc_Print( 1, "Counter-example is not available.\n" );
else else
{ {
iOut = Ssw_SecCexResimulate( pMiterCec, pMiterCec->pData, &nOuts ); iOut = Ssw_SecCexResimulate( pMiterCec, (int *)pMiterCec->pData, &nOuts );
if ( iOut == -1 ) if ( iOut == -1 )
printf( "Counter-example verification has failed.\n" ); Abc_Print( 1, "Counter-example verification has failed.\n" );
else else
{ {
printf( "Primary output %d has failed in frame %d.\n", iOut ); // Aig_Obj_t * pObj = Aig_ManPo(pMiterCec, iOut);
printf( "The counter-example detected %d incorrect outputs.\n", nOuts ); // Aig_Obj_t * pFan = Aig_ObjFanin0(pObj);
Abc_Print( 1, "Primary output %d has failed", iOut );
if ( nOuts-1 >= 0 )
Abc_Print( 1, ", along with other %d incorrect outputs", nOuts-1 );
Abc_Print( 1, ".\n" );
if ( piOutFail )
*piOutFail = iOut;
} }
Cec_ManTransformPattern( pMiter, iOut, pMiterCec->pData ); Cec_ManTransformPattern( pMiter, iOut, (int *)pMiterCec->pData );
} }
} }
else else
{ {
printf( "Networks are UNDECIDED. " ); Abc_Print( 1, "Networks are UNDECIDED. " );
ABC_PRT( "Time", clock() - clkTotal ); Abc_PrintTime( 1, "Time", clock() - clkTotal );
} }
fflush( stdout ); fflush( stdout );
Aig_ManStop( pMiterCec ); Aig_ManStop( pMiterCec );
@ -121,13 +133,18 @@ ABC_PRT( "Time", clock() - clkTotal );
SeeAlso [] SeeAlso []
***********************************************************************/ ***********************************************************************/
int Cec_ManVerify( Gia_Man_t * p, Cec_ParCec_t * pPars ) int Cec_ManVerify( Gia_Man_t * pInit, Cec_ParCec_t * pPars )
{ {
int fDumpUndecided = 1; int fDumpUndecided = 0;
Cec_ParFra_t ParsFra, * pParsFra = &ParsFra; Cec_ParFra_t ParsFra, * pParsFra = &ParsFra;
Gia_Man_t * pNew; Gia_Man_t * p, * pNew;
int RetValue, clk = clock(); int RetValue, clk = clock();
double clkTotal = clock(); double clkTotal = clock();
// preprocess
p = Gia_ManDup( pInit );
Gia_ManEquivFixOutputPairs( p );
p = Gia_ManCleanup( pNew = p );
Gia_ManStop( pNew );
// sweep for equivalences // sweep for equivalences
Cec_ManFraSetDefaultParams( pParsFra ); Cec_ManFraSetDefaultParams( pParsFra );
pParsFra->nItersMax = 1000; pParsFra->nItersMax = 1000;
@ -137,27 +154,60 @@ int Cec_ManVerify( Gia_Man_t * p, Cec_ParCec_t * pPars )
pParsFra->fCheckMiter = 1; pParsFra->fCheckMiter = 1;
pParsFra->fDualOut = 1; pParsFra->fDualOut = 1;
pNew = Cec_ManSatSweeping( p, pParsFra ); pNew = Cec_ManSatSweeping( p, pParsFra );
pPars->iOutFail = pParsFra->iOutFail;
// update
pInit->pCexComb = p->pCexComb; p->pCexComb = NULL;
Gia_ManStop( p );
p = pInit;
// continue
if ( pNew == NULL ) if ( pNew == NULL )
{ {
if ( !Gia_ManVerifyCounterExample( p, p->pCexComb, 1 ) ) if ( p->pCexComb != NULL )
printf( "Counter-example simulation has failed.\n" ); {
printf( "Networks are NOT EQUIVALENT. " ); if ( p->pCexComb && !Gia_ManVerifyCounterExample( p, p->pCexComb, 1 ) )
ABC_PRT( "Time", clock() - clk ); Abc_Print( 1, "Counter-example simulation has failed.\n" );
Abc_Print( 1, "Networks are NOT EQUIVALENT. " );
Abc_PrintTime( 1, "Time", clock() - clk );
return 0; return 0;
} }
p = Gia_ManDup( pInit );
Gia_ManEquivFixOutputPairs( p );
p = Gia_ManCleanup( pNew = p );
Gia_ManStop( pNew );
pNew = p;
}
if ( Gia_ManAndNum(pNew) == 0 ) if ( Gia_ManAndNum(pNew) == 0 )
{ {
printf( "Networks are equivalent. " ); Gia_Obj_t * pObj1, * pObj2;
ABC_PRT( "Time", clock() - clk ); int i;
Gia_ManForEachPo( pNew, pObj1, i )
{
pObj2 = Gia_ManPo( pNew, ++i );
if ( Gia_ObjChild0(pObj1) != Gia_ObjChild0(pObj2) )
{
Abc_Print( 1, "Networks are NOT EQUIVALENT. Outputs %d trivially differ. ", i/2 );
Abc_PrintTime( 1, "Time", clock() - clk );
Gia_ManStop( pNew );
pPars->iOutFail = i/2;
return 0;
}
}
Abc_Print( 1, "Networks are equivalent. " );
Abc_PrintTime( 1, "Time", clock() - clk );
Gia_ManStop( pNew ); Gia_ManStop( pNew );
return 1; return 1;
} }
printf( "Networks are UNDECIDED after the new CEC engine. " ); if ( pPars->fVerbose )
ABC_PRT( "Time", clock() - clk ); {
Abc_Print( 1, "Networks are UNDECIDED after the new CEC engine. " );
Abc_PrintTime( 1, "Time", clock() - clk );
}
if ( fDumpUndecided ) if ( fDumpUndecided )
{ {
ABC_FREE( pNew->pReprs );
ABC_FREE( pNew->pNexts );
Gia_WriteAiger( pNew, "gia_cec_undecided.aig", 0, 0 ); Gia_WriteAiger( pNew, "gia_cec_undecided.aig", 0, 0 );
printf( "The result is written into file \"%s\".\n", "gia_cec_undecided.aig" ); Abc_Print( 1, "The result is written into file \"%s\".\n", "gia_cec_undecided.aig" );
} }
if ( pPars->TimeLimit && ((double)clock() - clkTotal)/CLOCKS_PER_SEC >= pPars->TimeLimit ) if ( pPars->TimeLimit && ((double)clock() - clkTotal)/CLOCKS_PER_SEC >= pPars->TimeLimit )
{ {
@ -165,12 +215,13 @@ int Cec_ManVerify( Gia_Man_t * p, Cec_ParCec_t * pPars )
return -1; return -1;
} }
// call other solver // call other solver
printf( "Calling the old CEC engine.\n" ); if ( pPars->fVerbose )
Abc_Print( 1, "Calling the old CEC engine.\n" );
fflush( stdout ); fflush( stdout );
RetValue = Cec_ManVerifyOld( pNew, pPars->fVerbose ); RetValue = Cec_ManVerifyOld( pNew, pPars->fVerbose, &pPars->iOutFail );
p->pCexComb = pNew->pCexComb; pNew->pCexComb = NULL; p->pCexComb = pNew->pCexComb; pNew->pCexComb = NULL;
if ( p->pCexComb && !Gia_ManVerifyCounterExample( p, p->pCexComb, 1 ) ) if ( p->pCexComb && !Gia_ManVerifyCounterExample( p, p->pCexComb, 1 ) )
printf( "Counter-example simulation has failed.\n" ); Abc_Print( 1, "Counter-example simulation has failed.\n" );
Gia_ManStop( pNew ); Gia_ManStop( pNew );
return RetValue; return RetValue;
} }
@ -208,7 +259,7 @@ int Cec_ManVerifyTwo( Gia_Man_t * p0, Gia_Man_t * p1, int fVerbose )
Description [Returns 1 if equivalent, 0 if counter-example, -1 if undecided. Description [Returns 1 if equivalent, 0 if counter-example, -1 if undecided.
Counter-example is returned in the first manager as pAig0->pSeqModel. Counter-example is returned in the first manager as pAig0->pSeqModel.
The format is given in Gia_Cex_t (file "abc\src\aig\gia\gia.h").] The format is given in Abc_Cex_t (file "abc\src\aig\gia\gia.h").]
SideEffects [] SideEffects []
@ -248,7 +299,6 @@ int Cec_ManVerifyTwoAigs( Aig_Man_t * pAig0, Aig_Man_t * pAig1, int fVerbose )
***********************************************************************/ ***********************************************************************/
Aig_Man_t * Cec_LatchCorrespondence( Aig_Man_t * pAig, int nConfs, int fUseCSat ) Aig_Man_t * Cec_LatchCorrespondence( Aig_Man_t * pAig, int nConfs, int fUseCSat )
{ {
extern int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars );
Gia_Man_t * pGia; Gia_Man_t * pGia;
Cec_ParCor_t CorPars, * pCorPars = &CorPars; Cec_ParCor_t CorPars, * pCorPars = &CorPars;
Cec_ManCorSetDefaultParams( pCorPars ); Cec_ManCorSetDefaultParams( pCorPars );
@ -275,7 +325,6 @@ Aig_Man_t * Cec_LatchCorrespondence( Aig_Man_t * pAig, int nConfs, int fUseCSat
***********************************************************************/ ***********************************************************************/
Aig_Man_t * Cec_SignalCorrespondence( Aig_Man_t * pAig, int nConfs, int fUseCSat ) Aig_Man_t * Cec_SignalCorrespondence( Aig_Man_t * pAig, int nConfs, int fUseCSat )
{ {
extern int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars );
Gia_Man_t * pGia; Gia_Man_t * pGia;
Cec_ParCor_t CorPars, * pCorPars = &CorPars; Cec_ParCor_t CorPars, * pCorPars = &CorPars;
Cec_ManCorSetDefaultParams( pCorPars ); Cec_ManCorSetDefaultParams( pCorPars );
@ -304,6 +353,7 @@ Aig_Man_t * Cec_FraigCombinational( Aig_Man_t * pAig, int nConfs, int fVerbose )
Gia_Man_t * pGia; Gia_Man_t * pGia;
Cec_ParFra_t FraPars, * pFraPars = &FraPars; Cec_ParFra_t FraPars, * pFraPars = &FraPars;
Cec_ManFraSetDefaultParams( pFraPars ); Cec_ManFraSetDefaultParams( pFraPars );
pFraPars->fSatSweeping = 1;
pFraPars->nBTLimit = nConfs; pFraPars->nBTLimit = nConfs;
pFraPars->nItersMax = 20; pFraPars->nItersMax = 20;
pFraPars->fVerbose = fVerbose; pFraPars->fVerbose = fVerbose;
@ -319,3 +369,5 @@ Aig_Man_t * Cec_FraigCombinational( Aig_Man_t * pAig, int nConfs, int fVerbose )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

106
src/aig/cec/cecChoice.c
View File

@ -22,6 +22,9 @@
#include "giaAig.h" #include "giaAig.h"
#include "dch.h" #include "dch.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -175,9 +178,9 @@ Gia_Man_t * Cec_ManCombSpecReduce( Gia_Man_t * p, Vec_Int_t ** pvOutputs, int fR
Gia_ManAppendCo( pNew, iObjNew ); Gia_ManAppendCo( pNew, iObjNew );
Vec_IntFree( vXorLits ); Vec_IntFree( vXorLits );
Gia_ManHashStop( pNew ); Gia_ManHashStop( pNew );
//printf( "Before sweeping = %d\n", Gia_ManAndNum(pNew) ); //Abc_Print( 1, "Before sweeping = %d\n", Gia_ManAndNum(pNew) );
pNew = Gia_ManCleanup( pTemp = pNew ); pNew = Gia_ManCleanup( pTemp = pNew );
//printf( "After sweeping = %d\n", Gia_ManAndNum(pNew) ); //Abc_Print( 1, "After sweeping = %d\n", Gia_ManAndNum(pNew) );
Gia_ManStop( pTemp ); Gia_ManStop( pTemp );
return pNew; return pNew;
} }
@ -219,7 +222,7 @@ int Cec_ManChoiceComputation_int( Gia_Man_t * pAig, Cec_ParChc_t * pPars )
pParsSim->fSeqSimulate = 0; pParsSim->fSeqSimulate = 0;
// create equivalence classes of registers // create equivalence classes of registers
pSim = Cec_ManSimStart( pAig, pParsSim ); pSim = Cec_ManSimStart( pAig, pParsSim );
Cec_ManSimClassesPrepare( pSim ); Cec_ManSimClassesPrepare( pSim, -1 );
Cec_ManSimClassesRefine( pSim ); Cec_ManSimClassesRefine( pSim );
// prepare SAT solving // prepare SAT solving
Cec_ManSatSetDefaultParams( pParsSat ); Cec_ManSatSetDefaultParams( pParsSat );
@ -227,7 +230,7 @@ int Cec_ManChoiceComputation_int( Gia_Man_t * pAig, Cec_ParChc_t * pPars )
pParsSat->fVerbose = pPars->fVerbose; pParsSat->fVerbose = pPars->fVerbose;
if ( pPars->fVerbose ) if ( pPars->fVerbose )
{ {
printf( "Obj = %7d. And = %7d. Conf = %5d. Ring = %d. CSat = %d.\n", Abc_Print( 1, "Obj = %7d. And = %7d. Conf = %5d. Ring = %d. CSat = %d.\n",
Gia_ManObjNum(pAig), Gia_ManAndNum(pAig), pPars->nBTLimit, pPars->fUseRings, pPars->fUseCSat ); Gia_ManObjNum(pAig), Gia_ManAndNum(pAig), pPars->nBTLimit, pPars->fUseRings, pPars->fUseCSat );
Cec_ManRefinedClassPrintStats( pAig, NULL, 0, clock() - clk ); Cec_ManRefinedClassPrintStats( pAig, NULL, 0, clock() - clk );
} }
@ -280,95 +283,21 @@ int Cec_ManChoiceComputation_int( Gia_Man_t * pAig, Cec_ParChc_t * pPars )
} }
// check the overflow // check the overflow
if ( r == nItersMax ) if ( r == nItersMax )
printf( "The refinement was not finished. The result may be incorrect.\n" ); Abc_Print( 1, "The refinement was not finished. The result may be incorrect.\n" );
Cec_ManSimStop( pSim ); Cec_ManSimStop( pSim );
clkTotal = clock() - clkTotal; clkTotal = clock() - clkTotal;
// report the results // report the results
if ( pPars->fVerbose ) if ( pPars->fVerbose )
{ {
ABC_PRTP( "Srm ", clkSrm, clkTotal ); Abc_PrintTimeP( 1, "Srm ", clkSrm, clkTotal );
ABC_PRTP( "Sat ", clkSat, clkTotal ); Abc_PrintTimeP( 1, "Sat ", clkSat, clkTotal );
ABC_PRTP( "Sim ", clkSim, clkTotal ); Abc_PrintTimeP( 1, "Sim ", clkSim, clkTotal );
ABC_PRTP( "Other", clkTotal-clkSat-clkSrm-clkSim, clkTotal ); Abc_PrintTimeP( 1, "Other", clkTotal-clkSat-clkSrm-clkSim, clkTotal );
ABC_PRT( "TOTAL", clkTotal ); Abc_PrintTime( 1, "TOTAL", clkTotal );
} }
return 0; return 0;
} }
/**Function*************************************************************
Synopsis [Duplicates the AIG in the DFS order.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_ManChoiceMiter_rec( Gia_Man_t * pNew, Gia_Man_t * p, Gia_Obj_t * pObj )
{
if ( ~pObj->Value )
return pObj->Value;
Gia_ManChoiceMiter_rec( pNew, p, Gia_ObjFanin0(pObj) );
if ( Gia_ObjIsCo(pObj) )
return pObj->Value = Gia_ManAppendCo( pNew, Gia_ObjFanin0Copy(pObj) );
Gia_ManChoiceMiter_rec( pNew, p, Gia_ObjFanin1(pObj) );
return pObj->Value = Gia_ManHashAnd( pNew, Gia_ObjFanin0Copy(pObj), Gia_ObjFanin1Copy(pObj) );
}
/**Function*************************************************************
Synopsis [Derives the miter of several AIGs for choice computation.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Gia_ManChoiceMiter( Vec_Ptr_t * vGias )
{
Gia_Man_t * pNew, * pGia, * pGia0;
int i, k, iNode, nNodes;
// make sure they have equal parameters
assert( Vec_PtrSize(vGias) > 0 );
pGia0 = Vec_PtrEntry( vGias, 0 );
Vec_PtrForEachEntry( vGias, pGia, i )
{
assert( Gia_ManCiNum(pGia) == Gia_ManCiNum(pGia0) );
assert( Gia_ManCoNum(pGia) == Gia_ManCoNum(pGia0) );
assert( Gia_ManRegNum(pGia) == Gia_ManRegNum(pGia0) );
Gia_ManFillValue( pGia );
Gia_ManConst0(pGia)->Value = 0;
}
// start the new manager
pNew = Gia_ManStart( Vec_PtrSize(vGias) * Gia_ManObjNum(pGia0) );
pNew->pName = Gia_UtilStrsav( pGia0->pName );
// create new CIs and assign them to the old manager CIs
for ( k = 0; k < Gia_ManCiNum(pGia0); k++ )
{
iNode = Gia_ManAppendCi(pNew);
Vec_PtrForEachEntry( vGias, pGia, i )
Gia_ManCi( pGia, k )->Value = iNode;
}
// create internal nodes
Gia_ManHashAlloc( pNew );
for ( k = 0; k < Gia_ManCoNum(pGia0); k++ )
{
Vec_PtrForEachEntry( vGias, pGia, i )
Gia_ManChoiceMiter_rec( pNew, pGia, Gia_ManCo( pGia, k ) );
}
Gia_ManHashStop( pNew );
// check the presence of dangling nodes
nNodes = Gia_ManHasDandling( pNew );
assert( nNodes == 0 );
// finalize
// Gia_ManSetRegNum( pNew, Gia_ManRegNum(pGia0) );
return pNew;
}
/**Function************************************************************* /**Function*************************************************************
Synopsis [Computes choices for the vector of AIGs.] Synopsis [Computes choices for the vector of AIGs.]
@ -386,6 +315,7 @@ Gia_Man_t * Cec_ManChoiceComputationVec( Gia_Man_t * pGia, int nGias, Cec_ParChc
int RetValue; int RetValue;
// compute equivalences of the miter // compute equivalences of the miter
// pMiter = Gia_ManChoiceMiter( vGias ); // pMiter = Gia_ManChoiceMiter( vGias );
// Gia_ManSetRegNum( pMiter, 0 );
RetValue = Cec_ManChoiceComputation_int( pGia, pPars ); RetValue = Cec_ManChoiceComputation_int( pGia, pPars );
// derive AIG with choices // derive AIG with choices
pNew = Gia_ManEquivToChoices( pGia, nGias ); pNew = Gia_ManEquivToChoices( pGia, nGias );
@ -394,7 +324,7 @@ Gia_Man_t * Cec_ManChoiceComputationVec( Gia_Man_t * pGia, int nGias, Cec_ParChc
// report the results // report the results
if ( pPars->fVerbose ) if ( pPars->fVerbose )
{ {
// printf( "NBeg = %d. NEnd = %d. (Gain = %6.2f %%). RBeg = %d. REnd = %d. (Gain = %6.2f %%).\n", // Abc_Print( 1, "NBeg = %d. NEnd = %d. (Gain = %6.2f %%). RBeg = %d. REnd = %d. (Gain = %6.2f %%).\n",
// Gia_ManAndNum(pAig), Gia_ManAndNum(pNew), // Gia_ManAndNum(pAig), Gia_ManAndNum(pNew),
// 100.0*(Gia_ManAndNum(pAig)-Gia_ManAndNum(pNew))/(Gia_ManAndNum(pAig)?Gia_ManAndNum(pAig):1), // 100.0*(Gia_ManAndNum(pAig)-Gia_ManAndNum(pNew))/(Gia_ManAndNum(pAig)?Gia_ManAndNum(pAig):1),
// Gia_ManRegNum(pAig), Gia_ManRegNum(pNew), // Gia_ManRegNum(pAig), Gia_ManRegNum(pNew),
@ -416,7 +346,7 @@ Gia_Man_t * Cec_ManChoiceComputationVec( Gia_Man_t * pGia, int nGias, Cec_ParChc
***********************************************************************/ ***********************************************************************/
Gia_Man_t * Cec_ManChoiceComputation( Gia_Man_t * pAig, Cec_ParChc_t * pParsChc ) Gia_Man_t * Cec_ManChoiceComputation( Gia_Man_t * pAig, Cec_ParChc_t * pParsChc )
{ {
extern Aig_Man_t * Dar_ManChoiceNew( Aig_Man_t * pAig, Dch_Pars_t * pPars ); // extern Aig_Man_t * Dar_ManChoiceNew( Aig_Man_t * pAig, Dch_Pars_t * pPars );
Dch_Pars_t Pars, * pPars = &Pars; Dch_Pars_t Pars, * pPars = &Pars;
Aig_Man_t * pMan, * pManNew; Aig_Man_t * pMan, * pManNew;
Gia_Man_t * pGia; Gia_Man_t * pGia;
@ -456,7 +386,7 @@ Aig_Man_t * Cec_ComputeChoices( Gia_Man_t * pGia, Dch_Pars_t * pPars )
Cec_ParChc_t ParsChc, * pParsChc = &ParsChc; Cec_ParChc_t ParsChc, * pParsChc = &ParsChc;
Aig_Man_t * pAig; Aig_Man_t * pAig;
if ( pPars->fVerbose ) if ( pPars->fVerbose )
ABC_PRT( "Synthesis time", pPars->timeSynth ); Abc_PrintTime( 1, "Synthesis time", pPars->timeSynth );
Cec_ManChcSetDefaultParams( pParsChc ); Cec_ManChcSetDefaultParams( pParsChc );
pParsChc->nBTLimit = pPars->nBTLimit; pParsChc->nBTLimit = pPars->nBTLimit;
pParsChc->fUseCSat = pPars->fUseCSat; pParsChc->fUseCSat = pPars->fUseCSat;
@ -475,3 +405,5 @@ Aig_Man_t * Cec_ComputeChoices( Gia_Man_t * pGia, Dch_Pars_t * pPars )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

48
src/aig/cec/cecClass.c
View File

@ -20,6 +20,9 @@
#include "cecInt.h" #include "cecInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -375,7 +378,7 @@ int Cec_ManSimHashKey( unsigned * pSim, int nWords, int nTableSize )
void Cec_ManSimMemRelink( Cec_ManSim_t * p ) void Cec_ManSimMemRelink( Cec_ManSim_t * p )
{ {
unsigned * pPlace, Ent; unsigned * pPlace, Ent;
pPlace = &p->MemFree; pPlace = (unsigned *)&p->MemFree;
for ( Ent = p->nMems * (p->nWords + 1); for ( Ent = p->nMems * (p->nWords + 1);
Ent + p->nWords + 1 < (unsigned)p->nWordsAlloc; Ent + p->nWords + 1 < (unsigned)p->nWordsAlloc;
Ent += p->nWords + 1 ) Ent += p->nWords + 1 )
@ -518,14 +521,14 @@ void Cec_ManSimSavePattern( Cec_ManSim_t * p, int iPat )
int i; int i;
assert( p->pCexComb == NULL ); assert( p->pCexComb == NULL );
assert( iPat >= 0 && iPat < 32 * p->nWords ); assert( iPat >= 0 && iPat < 32 * p->nWords );
p->pCexComb = (Gia_Cex_t *)ABC_CALLOC( char, p->pCexComb = (Abc_Cex_t *)ABC_CALLOC( char,
sizeof(Gia_Cex_t) + sizeof(unsigned) * Gia_BitWordNum(Gia_ManCiNum(p->pAig)) ); sizeof(Abc_Cex_t) + sizeof(unsigned) * Gia_BitWordNum(Gia_ManCiNum(p->pAig)) );
p->pCexComb->iPo = p->iOut; p->pCexComb->iPo = p->iOut;
p->pCexComb->nPis = Gia_ManCiNum(p->pAig); p->pCexComb->nPis = Gia_ManCiNum(p->pAig);
p->pCexComb->nBits = Gia_ManCiNum(p->pAig); p->pCexComb->nBits = Gia_ManCiNum(p->pAig);
for ( i = 0; i < Gia_ManCiNum(p->pAig); i++ ) for ( i = 0; i < Gia_ManCiNum(p->pAig); i++ )
{ {
pInfo = Vec_PtrEntry( p->vCiSimInfo, i ); pInfo = (unsigned *)Vec_PtrEntry( p->vCiSimInfo, i );
if ( Gia_InfoHasBit( pInfo, iPat ) ) if ( Gia_InfoHasBit( pInfo, iPat ) )
Gia_InfoSetBit( p->pCexComb->pData, i ); Gia_InfoSetBit( p->pCexComb->pData, i );
} }
@ -559,7 +562,7 @@ void Cec_ManSimFindBestPattern( Cec_ManSim_t * p )
assert( p->pBestState->nRegs == Gia_ManRegNum(p->pAig) ); assert( p->pBestState->nRegs == Gia_ManRegNum(p->pAig) );
for ( i = 0; i < Gia_ManRegNum(p->pAig); i++ ) for ( i = 0; i < Gia_ManRegNum(p->pAig); i++ )
{ {
pInfo = Vec_PtrEntry( p->vCiSimInfo, Gia_ManPiNum(p->pAig) + i ); pInfo = (unsigned *)Vec_PtrEntry( p->vCiSimInfo, Gia_ManPiNum(p->pAig) + i );
if ( Gia_InfoHasBit(p->pBestState->pData, i) != Gia_InfoHasBit(pInfo, iPatBest) ) if ( Gia_InfoHasBit(p->pBestState->pData, i) != Gia_InfoHasBit(pInfo, iPatBest) )
Gia_InfoXorBit( p->pBestState->pData, i ); Gia_InfoXorBit( p->pBestState->pData, i );
} }
@ -591,8 +594,8 @@ int Cec_ManSimAnalyzeOutputs( Cec_ManSim_t * p )
assert( (Gia_ManPoNum(p->pAig) & 1) == 0 ); assert( (Gia_ManPoNum(p->pAig) & 1) == 0 );
for ( i = 0; i < Gia_ManPoNum(p->pAig); i++ ) for ( i = 0; i < Gia_ManPoNum(p->pAig); i++ )
{ {
pInfo = Vec_PtrEntry( p->vCoSimInfo, i ); pInfo = (unsigned *)Vec_PtrEntry( p->vCoSimInfo, i );
pInfo2 = Vec_PtrEntry( p->vCoSimInfo, ++i ); pInfo2 = (unsigned *)Vec_PtrEntry( p->vCoSimInfo, ++i );
if ( !Cec_ManSimCompareEqual( pInfo, pInfo2, p->nWords ) ) if ( !Cec_ManSimCompareEqual( pInfo, pInfo2, p->nWords ) )
{ {
if ( p->iOut == -1 ) if ( p->iOut == -1 )
@ -614,7 +617,7 @@ int Cec_ManSimAnalyzeOutputs( Cec_ManSim_t * p )
{ {
for ( i = 0; i < Gia_ManPoNum(p->pAig); i++ ) for ( i = 0; i < Gia_ManPoNum(p->pAig); i++ )
{ {
pInfo = Vec_PtrEntry( p->vCoSimInfo, i ); pInfo = (unsigned *)Vec_PtrEntry( p->vCoSimInfo, i );
if ( !Cec_ManSimCompareConst( pInfo, p->nWords ) ) if ( !Cec_ManSimCompareConst( pInfo, p->nWords ) )
{ {
if ( p->iOut == -1 ) if ( p->iOut == -1 )
@ -679,7 +682,7 @@ int Cec_ManSimSimulateRound( Cec_ManSim_t * p, Vec_Ptr_t * vInfoCis, Vec_Ptr_t *
pRes = Cec_ManSimSimRef( p, i ); pRes = Cec_ManSimSimRef( p, i );
if ( vInfoCis ) if ( vInfoCis )
{ {
pRes0 = Vec_PtrEntry( vInfoCis, iCiId++ ); pRes0 = (unsigned *)Vec_PtrEntry( vInfoCis, iCiId++ );
for ( w = 1; w <= p->nWords; w++ ) for ( w = 1; w <= p->nWords; w++ )
pRes[w] = pRes0[w-1]; pRes[w] = pRes0[w-1];
} }
@ -697,7 +700,7 @@ int Cec_ManSimSimulateRound( Cec_ManSim_t * p, Vec_Ptr_t * vInfoCis, Vec_Ptr_t *
pRes0 = Cec_ManSimSimDeref( p, Gia_ObjFaninId0(pObj,i) ); pRes0 = Cec_ManSimSimDeref( p, Gia_ObjFaninId0(pObj,i) );
if ( vInfoCos ) if ( vInfoCos )
{ {
pRes = Vec_PtrEntry( vInfoCos, iCoId++ ); pRes = (unsigned *)Vec_PtrEntry( vInfoCos, iCoId++ );
if ( Gia_ObjFaninC0(pObj) ) if ( Gia_ObjFaninC0(pObj) )
for ( w = 1; w <= p->nWords; w++ ) for ( w = 1; w <= p->nWords; w++ )
pRes[w-1] = ~pRes0[w]; pRes[w-1] = ~pRes0[w];
@ -712,7 +715,7 @@ int Cec_ManSimSimulateRound( Cec_ManSim_t * p, Vec_Ptr_t * vInfoCis, Vec_Ptr_t *
pRes0 = Cec_ManSimSimDeref( p, Gia_ObjFaninId0(pObj,i) ); pRes0 = Cec_ManSimSimDeref( p, Gia_ObjFaninId0(pObj,i) );
pRes1 = Cec_ManSimSimDeref( p, Gia_ObjFaninId1(pObj,i) ); pRes1 = Cec_ManSimSimDeref( p, Gia_ObjFaninId1(pObj,i) );
// printf( "%d,%d ", Gia_ObjValue( Gia_ObjFanin0(pObj) ), Gia_ObjValue( Gia_ObjFanin1(pObj) ) ); // Abc_Print( 1, "%d,%d ", Gia_ObjValue( Gia_ObjFanin0(pObj) ), Gia_ObjValue( Gia_ObjFanin1(pObj) ) );
if ( Gia_ObjFaninC0(pObj) ) if ( Gia_ObjFaninC0(pObj) )
{ {
@ -762,7 +765,7 @@ references:
assert( vInfoCos == NULL || iCoId == Gia_ManCoNum(p->pAig) ); assert( vInfoCos == NULL || iCoId == Gia_ManCoNum(p->pAig) );
assert( p->nMems == 1 ); assert( p->nMems == 1 );
if ( p->nMems != 1 ) if ( p->nMems != 1 )
printf( "Cec_ManSimSimulateRound(): Memory management error!\n" ); Abc_Print( 1, "Cec_ManSimSimulateRound(): Memory management error!\n" );
if ( p->pPars->fVeryVerbose ) if ( p->pPars->fVeryVerbose )
Gia_ManEquivPrintClasses( p->pAig, 0, Cec_MemUsage(p) ); Gia_ManEquivPrintClasses( p->pAig, 0, Cec_MemUsage(p) );
if ( p->pBestState ) if ( p->pBestState )
@ -800,14 +803,14 @@ void Cec_ManSimCreateInfo( Cec_ManSim_t * p, Vec_Ptr_t * vInfoCis, Vec_Ptr_t * v
assert( vInfoCis && vInfoCos ); assert( vInfoCis && vInfoCos );
for ( i = 0; i < Gia_ManPiNum(p->pAig); i++ ) for ( i = 0; i < Gia_ManPiNum(p->pAig); i++ )
{ {
pRes0 = Vec_PtrEntry( vInfoCis, i ); pRes0 = (unsigned *)Vec_PtrEntry( vInfoCis, i );
for ( w = 0; w < p->nWords; w++ ) for ( w = 0; w < p->nWords; w++ )
pRes0[w] = Gia_ManRandom( 0 ); pRes0[w] = Gia_ManRandom( 0 );
} }
for ( i = 0; i < Gia_ManRegNum(p->pAig); i++ ) for ( i = 0; i < Gia_ManRegNum(p->pAig); i++ )
{ {
pRes0 = Vec_PtrEntry( vInfoCis, Gia_ManPiNum(p->pAig) + i ); pRes0 = (unsigned *)Vec_PtrEntry( vInfoCis, Gia_ManPiNum(p->pAig) + i );
pRes1 = Vec_PtrEntry( vInfoCos, Gia_ManPoNum(p->pAig) + i ); pRes1 = (unsigned *)Vec_PtrEntry( vInfoCos, Gia_ManPoNum(p->pAig) + i );
for ( w = 0; w < p->nWords; w++ ) for ( w = 0; w < p->nWords; w++ )
pRes0[w] = pRes1[w]; pRes0[w] = pRes1[w];
} }
@ -816,7 +819,7 @@ void Cec_ManSimCreateInfo( Cec_ManSim_t * p, Vec_Ptr_t * vInfoCis, Vec_Ptr_t * v
{ {
for ( i = 0; i < Gia_ManCiNum(p->pAig); i++ ) for ( i = 0; i < Gia_ManCiNum(p->pAig); i++ )
{ {
pRes0 = Vec_PtrEntry( vInfoCis, i ); pRes0 = (unsigned *)Vec_PtrEntry( vInfoCis, i );
for ( w = 0; w < p->nWords; w++ ) for ( w = 0; w < p->nWords; w++ )
pRes0[w] = Gia_ManRandom( 0 ); pRes0[w] = Gia_ManRandom( 0 );
} }
@ -834,7 +837,7 @@ void Cec_ManSimCreateInfo( Cec_ManSim_t * p, Vec_Ptr_t * vInfoCis, Vec_Ptr_t * v
SeeAlso [] SeeAlso []
***********************************************************************/ ***********************************************************************/
int Cec_ManSimClassesPrepare( Cec_ManSim_t * p ) int Cec_ManSimClassesPrepare( Cec_ManSim_t * p, int LevelMax )
{ {
Gia_Obj_t * pObj; Gia_Obj_t * pObj;
int i; int i;
@ -848,9 +851,16 @@ int Cec_ManSimClassesPrepare( Cec_ManSim_t * p )
if ( p->pPars->fLatchCorr ) if ( p->pPars->fLatchCorr )
Gia_ManForEachObj( p->pAig, pObj, i ) Gia_ManForEachObj( p->pAig, pObj, i )
Gia_ObjSetRepr( p->pAig, i, GIA_VOID ); Gia_ObjSetRepr( p->pAig, i, GIA_VOID );
else else if ( LevelMax == -1 )
Gia_ManForEachObj( p->pAig, pObj, i ) Gia_ManForEachObj( p->pAig, pObj, i )
Gia_ObjSetRepr( p->pAig, i, Gia_ObjIsAnd(pObj) ? 0 : GIA_VOID ); Gia_ObjSetRepr( p->pAig, i, Gia_ObjIsAnd(pObj) ? 0 : GIA_VOID );
else
{
Gia_ManLevelNum( p->pAig );
Gia_ManForEachObj( p->pAig, pObj, i )
Gia_ObjSetRepr( p->pAig, i, (Gia_ObjIsAnd(pObj) && Gia_ObjLevel(p->pAig,pObj) <= LevelMax) ? 0 : GIA_VOID );
Vec_IntFreeP( &p->pAig->vLevels );
}
// if sequential simulation, set starting representative of ROs to be constant 0 // if sequential simulation, set starting representative of ROs to be constant 0
if ( p->pPars->fSeqSimulate ) if ( p->pPars->fSeqSimulate )
Gia_ManForEachRo( p->pAig, pObj, i ) Gia_ManForEachRo( p->pAig, pObj, i )
@ -906,3 +916,5 @@ int Cec_ManSimClassesRefine( Cec_ManSim_t * p )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

73
src/aig/cec/cecCore.c
View File

@ -20,6 +20,9 @@
#include "cecInt.h" #include "cecInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -133,8 +136,10 @@ void Cec_ManFraSetDefaultParams( Cec_ParFra_t * p )
// p->fFirstStop = 0; // stop on the first sat output // p->fFirstStop = 0; // stop on the first sat output
p->fDualOut = 0; // miter with separate outputs p->fDualOut = 0; // miter with separate outputs
p->fColorDiff = 0; // miter with separate outputs p->fColorDiff = 0; // miter with separate outputs
p->fSatSweeping = 0; // enable SAT sweeping
p->fVeryVerbose = 0; // verbose stats p->fVeryVerbose = 0; // verbose stats
p->fVerbose = 0; // verbose stats p->fVerbose = 0; // verbose stats
p->iOutFail = -1; // the failed output
} }
/**Function************************************************************* /**Function*************************************************************
@ -158,6 +163,7 @@ void Cec_ManCecSetDefaultParams( Cec_ParCec_t * p )
p->fRewriting = 0; // enables AIG rewriting p->fRewriting = 0; // enables AIG rewriting
p->fVeryVerbose = 0; // verbose stats p->fVeryVerbose = 0; // verbose stats
p->fVerbose = 0; // verbose stats p->fVerbose = 0; // verbose stats
p->iOutFail = -1; // the number of failed output
} }
/**Function************************************************************* /**Function*************************************************************
@ -178,6 +184,8 @@ void Cec_ManCorSetDefaultParams( Cec_ParCor_t * p )
p->nRounds = 15; // the number of simulation rounds p->nRounds = 15; // the number of simulation rounds
p->nFrames = 1; // the number of time frames p->nFrames = 1; // the number of time frames
p->nBTLimit = 100; // conflict limit at a node p->nBTLimit = 100; // conflict limit at a node
p->nLevelMax = -1; // (scorr only) the max number of levels
p->nStepsMax = -1; // (scorr only) the max number of induction steps
p->fLatchCorr = 0; // consider only latch outputs p->fLatchCorr = 0; // consider only latch outputs
p->fUseRings = 1; // combine classes into rings p->fUseRings = 1; // combine classes into rings
p->fUseCSat = 1; // use circuit-based solver p->fUseCSat = 1; // use circuit-based solver
@ -249,12 +257,12 @@ int Cec_ManSimulationOne( Gia_Man_t * pAig, Cec_ParSim_t * pPars )
Cec_ManSim_t * pSim; Cec_ManSim_t * pSim;
int RetValue = 0, clkTotal = clock(); int RetValue = 0, clkTotal = clock();
pSim = Cec_ManSimStart( pAig, pPars ); pSim = Cec_ManSimStart( pAig, pPars );
if ( (pAig->pReprs == NULL && (RetValue = Cec_ManSimClassesPrepare( pSim ))) || if ( (pAig->pReprs == NULL && (RetValue = Cec_ManSimClassesPrepare( pSim, -1 ))) ||
(RetValue == 0 && (RetValue = Cec_ManSimClassesRefine( pSim ))) ) (RetValue == 0 && (RetValue = Cec_ManSimClassesRefine( pSim ))) )
printf( "The number of failed outputs of the miter = %6d. (Words = %4d. Frames = %4d.)\n", Abc_Print( 1, "The number of failed outputs of the miter = %6d. (Words = %4d. Frames = %4d.)\n",
pSim->nOuts, pPars->nWords, pPars->nFrames ); pSim->nOuts, pPars->nWords, pPars->nFrames );
if ( pPars->fVerbose ) if ( pPars->fVerbose )
ABC_PRT( "Time", clock() - clkTotal ); Abc_PrintTime( 1, "Time", clock() - clkTotal );
Cec_ManSimStop( pSim ); Cec_ManSimStop( pSim );
return RetValue; return RetValue;
} }
@ -275,7 +283,7 @@ void Cec_ManSimulation( Gia_Man_t * pAig, Cec_ParSim_t * pPars )
int r, nLitsOld, nLitsNew, nCountNoRef = 0, fStop = 0; int r, nLitsOld, nLitsNew, nCountNoRef = 0, fStop = 0;
Gia_ManRandom( 1 ); Gia_ManRandom( 1 );
if ( pPars->fSeqSimulate ) if ( pPars->fSeqSimulate )
printf( "Performing rounds of random simulation of %d frames with %d words.\n", Abc_Print( 1, "Performing rounds of random simulation of %d frames with %d words.\n",
pPars->nRounds, pPars->nFrames, pPars->nWords ); pPars->nRounds, pPars->nFrames, pPars->nWords );
nLitsOld = Gia_ManEquivCountLits( pAig ); nLitsOld = Gia_ManEquivCountLits( pAig );
for ( r = 0; r < pPars->nRounds; r++ ) for ( r = 0; r < pPars->nRounds; r++ )
@ -301,14 +309,14 @@ void Cec_ManSimulation( Gia_Man_t * pAig, Cec_ParSim_t * pPars )
} }
// if ( pPars->fVerbose ) // if ( pPars->fVerbose )
if ( r == pPars->nRounds || fStop ) if ( r == pPars->nRounds || fStop )
printf( "Random simulation is stopped after %d rounds.\n", r ); Abc_Print( 1, "Random simulation is stopped after %d rounds.\n", r );
else else
printf( "Random simulation saturated after %d rounds.\n", r ); Abc_Print( 1, "Random simulation saturated after %d rounds.\n", r );
if ( pPars->fCheckMiter ) if ( pPars->fCheckMiter )
{ {
int nNonConsts = Cec_ManCountNonConstOutputs( pAig ); int nNonConsts = Cec_ManCountNonConstOutputs( pAig );
if ( nNonConsts ) if ( nNonConsts )
printf( "The number of POs that are not const-0 candidates = %d.\n", nNonConsts ); Abc_Print( 1, "The number of POs that are not const-0 candidates = %d.\n", nNonConsts );
} }
} }
@ -366,7 +374,7 @@ Gia_Man_t * Cec_ManSatSweeping( Gia_Man_t * pAig, Cec_ParFra_t * pPars )
clk = clock(); clk = clock();
if ( p->pAig->pReprs == NULL ) if ( p->pAig->pReprs == NULL )
{ {
if ( Cec_ManSimClassesPrepare(pSim) || Cec_ManSimClassesRefine(pSim) ) if ( Cec_ManSimClassesPrepare(pSim, -1) || Cec_ManSimClassesRefine(pSim) )
{ {
Gia_ManStop( p->pAig ); Gia_ManStop( p->pAig );
p->pAig = NULL; p->pAig = NULL;
@ -395,19 +403,19 @@ p->timeSim += clock() - clk;
{ {
Gia_ManStop( pSrm ); Gia_ManStop( pSrm );
if ( p->pPars->fVerbose ) if ( p->pPars->fVerbose )
printf( "Considered all available candidate equivalences.\n" ); Abc_Print( 1, "Considered all available candidate equivalences.\n" );
if ( pPars->fDualOut && Gia_ManAndNum(p->pAig) > 0 ) if ( pPars->fDualOut && Gia_ManAndNum(p->pAig) > 0 )
{ {
if ( pPars->fColorDiff ) if ( pPars->fColorDiff )
{ {
if ( p->pPars->fVerbose ) if ( p->pPars->fVerbose )
printf( "Switching into reduced mode.\n" ); Abc_Print( 1, "Switching into reduced mode.\n" );
pPars->fColorDiff = 0; pPars->fColorDiff = 0;
} }
else else
{ {
if ( p->pPars->fVerbose ) if ( p->pPars->fVerbose )
printf( "Switching into normal mode.\n" ); Abc_Print( 1, "Switching into normal mode.\n" );
pPars->fDualOut = 0; pPars->fDualOut = 0;
} }
continue; continue;
@ -433,14 +441,14 @@ p->timeSat += clock() - clk;
break; break;
if ( p->pPars->fVerbose ) if ( p->pPars->fVerbose )
{ {
printf( "%3d : P =%7d. D =%7d. F =%6d. M = %7d. And =%8d. ", Abc_Print( 1, "%3d : P =%7d. D =%7d. F =%6d. M = %7d. And =%8d. ",
i, p->nAllProved, p->nAllDisproved, p->nAllFailed, nMatches, Gia_ManAndNum(p->pAig) ); i, p->nAllProved, p->nAllDisproved, p->nAllFailed, nMatches, Gia_ManAndNum(p->pAig) );
ABC_PRT( "Time", clock() - clk2 ); Abc_PrintTime( 1, "Time", clock() - clk2 );
} }
if ( Gia_ManAndNum(p->pAig) == 0 ) if ( Gia_ManAndNum(p->pAig) == 0 )
{ {
if ( p->pPars->fVerbose ) if ( p->pPars->fVerbose )
printf( "Network after reduction is empty.\n" ); Abc_Print( 1, "Network after reduction is empty.\n" );
break; break;
} }
// check resource limits // check resource limits
@ -454,54 +462,63 @@ p->timeSat += clock() - clk;
{ {
if ( pParsSat->nBTLimit >= 10001 ) if ( pParsSat->nBTLimit >= 10001 )
break; break;
if ( pPars->fSatSweeping )
{
if ( p->pPars->fVerbose )
Abc_Print( 1, "Exceeded the limit on the number of conflicts (%d).\n", pParsSat->nBTLimit );
break;
}
pParsSat->nBTLimit *= 10; pParsSat->nBTLimit *= 10;
if ( p->pPars->fVerbose ) if ( p->pPars->fVerbose )
{ {
if ( p->pPars->fVerbose ) if ( p->pPars->fVerbose )
printf( "Increasing conflict limit to %d.\n", pParsSat->nBTLimit ); Abc_Print( 1, "Increasing conflict limit to %d.\n", pParsSat->nBTLimit );
if ( fOutputResult ) if ( fOutputResult )
{ {
Gia_WriteAiger( p->pAig, "gia_cec_temp.aig", 0, 0 ); Gia_WriteAiger( p->pAig, "gia_cec_temp.aig", 0, 0 );
printf("The result is written into file \"%s\".\n", "gia_cec_temp.aig" ); Abc_Print( 1,"The result is written into file \"%s\".\n", "gia_cec_temp.aig" );
} }
} }
} }
if ( pPars->fDualOut && pPars->fColorDiff && (Gia_ManAndNum(p->pAig) < 100000 || p->nAllProved + p->nAllDisproved < 10) ) if ( pPars->fDualOut && pPars->fColorDiff && (Gia_ManAndNum(p->pAig) < 100000 || p->nAllProved + p->nAllDisproved < 10) )
{ {
if ( p->pPars->fVerbose ) if ( p->pPars->fVerbose )
printf( "Switching into reduced mode.\n" ); Abc_Print( 1, "Switching into reduced mode.\n" );
pPars->fColorDiff = 0; pPars->fColorDiff = 0;
} }
// if ( pPars->fDualOut && Gia_ManAndNum(p->pAig) < 20000 ) // if ( pPars->fDualOut && Gia_ManAndNum(p->pAig) < 20000 )
else if ( pPars->fDualOut && (Gia_ManAndNum(p->pAig) < 20000 || p->nAllProved + p->nAllDisproved < 10) ) else if ( pPars->fDualOut && (Gia_ManAndNum(p->pAig) < 20000 || p->nAllProved + p->nAllDisproved < 10) )
{ {
if ( p->pPars->fVerbose ) if ( p->pPars->fVerbose )
printf( "Switching into normal mode.\n" ); Abc_Print( 1, "Switching into normal mode.\n" );
pPars->fColorDiff = 0; pPars->fColorDiff = 0;
pPars->fDualOut = 0; pPars->fDualOut = 0;
} }
} }
finalize: finalize:
if ( p->pPars->fVerbose ) if ( p->pPars->fVerbose && p->pAig )
{ {
printf( "NBeg = %d. NEnd = %d. (Gain = %6.2f %%). RBeg = %d. REnd = %d. (Gain = %6.2f %%).\n", Abc_Print( 1, "NBeg = %d. NEnd = %d. (Gain = %6.2f %%). RBeg = %d. REnd = %d. (Gain = %6.2f %%).\n",
Gia_ManAndNum(pAig), Gia_ManAndNum(p->pAig), Gia_ManAndNum(pAig), Gia_ManAndNum(p->pAig),
100.0*(Gia_ManAndNum(pAig)-Gia_ManAndNum(p->pAig))/(Gia_ManAndNum(pAig)?Gia_ManAndNum(pAig):1), 100.0*(Gia_ManAndNum(pAig)-Gia_ManAndNum(p->pAig))/(Gia_ManAndNum(pAig)?Gia_ManAndNum(pAig):1),
Gia_ManRegNum(pAig), Gia_ManRegNum(p->pAig), Gia_ManRegNum(pAig), Gia_ManRegNum(p->pAig),
100.0*(Gia_ManRegNum(pAig)-Gia_ManRegNum(p->pAig))/(Gia_ManRegNum(pAig)?Gia_ManRegNum(pAig):1) ); 100.0*(Gia_ManRegNum(pAig)-Gia_ManRegNum(p->pAig))/(Gia_ManRegNum(pAig)?Gia_ManRegNum(pAig):1) );
ABC_PRTP( "Sim ", p->timeSim, clock() - (int)clkTotal ); Abc_PrintTimeP( 1, "Sim ", p->timeSim, clock() - (int)clkTotal );
ABC_PRTP( "Sat ", p->timeSat-pPat->timeTotalSave, clock() - (int)clkTotal ); Abc_PrintTimeP( 1, "Sat ", p->timeSat-pPat->timeTotalSave, clock() - (int)clkTotal );
ABC_PRTP( "Pat ", p->timePat+pPat->timeTotalSave, clock() - (int)clkTotal ); Abc_PrintTimeP( 1, "Pat ", p->timePat+pPat->timeTotalSave, clock() - (int)clkTotal );
ABC_PRT( "Time", clock() - clkTotal ); Abc_PrintTime( 1, "Time", (int)(clock() - clkTotal) );
} }
pTemp = p->pAig; p->pAig = NULL; pTemp = p->pAig; p->pAig = NULL;
if ( pTemp == NULL && pSim->iOut >= 0 ) if ( pTemp == NULL && pSim->iOut >= 0 )
printf( "Disproved at least one output of the miter (zero-based number %d).\n", pSim->iOut ); {
Abc_Print( 1, "Disproved at least one output of the miter (zero-based number %d).\n", pSim->iOut );
pPars->iOutFail = pSim->iOut;
}
else if ( pSim->pCexes ) else if ( pSim->pCexes )
printf( "Disproved %d outputs of the miter.\n", pSim->nOuts ); Abc_Print( 1, "Disproved %d outputs of the miter.\n", pSim->nOuts );
if ( fTimeOut ) if ( fTimeOut )
printf( "Timed out after %d seconds.\n", (int)((double)clock() - clkTotal)/CLOCKS_PER_SEC ); Abc_Print( 1, "Timed out after %d seconds.\n", (int)((double)clock() - clkTotal)/CLOCKS_PER_SEC );
pAig->pCexComb = pSim->pCexComb; pSim->pCexComb = NULL; pAig->pCexComb = pSim->pCexComb; pSim->pCexComb = NULL;
Cec_ManSimStop( pSim ); Cec_ManSimStop( pSim );
@ -516,3 +533,5 @@ finalize:
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

114
src/aig/cec/cecCorr.c
View File

@ -20,6 +20,9 @@
#include "cecInt.h" #include "cecInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -197,9 +200,9 @@ Gia_Man_t * Gia_ManCorrSpecReduce( Gia_Man_t * p, int nFrames, int fScorr, Vec_I
Vec_IntFree( vXorLits ); Vec_IntFree( vXorLits );
Gia_ManHashStop( pNew ); Gia_ManHashStop( pNew );
ABC_FREE( p->pCopies ); ABC_FREE( p->pCopies );
//printf( "Before sweeping = %d\n", Gia_ManAndNum(pNew) ); //Abc_Print( 1, "Before sweeping = %d\n", Gia_ManAndNum(pNew) );
pNew = Gia_ManCleanup( pTemp = pNew ); pNew = Gia_ManCleanup( pTemp = pNew );
//printf( "After sweeping = %d\n", Gia_ManAndNum(pNew) ); //Abc_Print( 1, "After sweeping = %d\n", Gia_ManAndNum(pNew) );
Gia_ManStop( pTemp ); Gia_ManStop( pTemp );
return pNew; return pNew;
} }
@ -266,9 +269,9 @@ Gia_Man_t * Gia_ManCorrSpecReduceInit( Gia_Man_t * p, int nFrames, int nPrefix,
Vec_IntFree( vXorLits ); Vec_IntFree( vXorLits );
Gia_ManHashStop( pNew ); Gia_ManHashStop( pNew );
ABC_FREE( p->pCopies ); ABC_FREE( p->pCopies );
//printf( "Before sweeping = %d\n", Gia_ManAndNum(pNew) ); //Abc_Print( 1, "Before sweeping = %d\n", Gia_ManAndNum(pNew) );
pNew = Gia_ManCleanup( pTemp = pNew ); pNew = Gia_ManCleanup( pTemp = pNew );
//printf( "After sweeping = %d\n", Gia_ManAndNum(pNew) ); //Abc_Print( 1, "After sweeping = %d\n", Gia_ManAndNum(pNew) );
Gia_ManStop( pTemp ); Gia_ManStop( pTemp );
return pNew; return pNew;
} }
@ -292,13 +295,13 @@ void Cec_ManStartSimInfo( Vec_Ptr_t * vInfo, int nFlops )
assert( nFlops <= Vec_PtrSize(vInfo) ); assert( nFlops <= Vec_PtrSize(vInfo) );
for ( k = 0; k < nFlops; k++ ) for ( k = 0; k < nFlops; k++ )
{ {
pInfo = Vec_PtrEntry( vInfo, k ); pInfo = (unsigned *)Vec_PtrEntry( vInfo, k );
for ( w = 0; w < nWords; w++ ) for ( w = 0; w < nWords; w++ )
pInfo[w] = 0; pInfo[w] = 0;
} }
for ( k = nFlops; k < Vec_PtrSize(vInfo); k++ ) for ( k = nFlops; k < Vec_PtrSize(vInfo); k++ )
{ {
pInfo = Vec_PtrEntry( vInfo, k ); pInfo = (unsigned *)Vec_PtrEntry( vInfo, k );
for ( w = 0; w < nWords; w++ ) for ( w = 0; w < nWords; w++ )
pInfo[w] = Gia_ManRandom( 0 ); pInfo[w] = Gia_ManRandom( 0 );
} }
@ -327,20 +330,20 @@ void Gia_ManCorrRemapSimInfo( Gia_Man_t * p, Vec_Ptr_t * vInfo )
pRepr = Gia_ObjReprObj( p, Gia_ObjId(p,pObj) ); pRepr = Gia_ObjReprObj( p, Gia_ObjId(p,pObj) );
if ( pRepr == NULL || Gia_ObjFailed(p, Gia_ObjId(p,pObj)) ) if ( pRepr == NULL || Gia_ObjFailed(p, Gia_ObjId(p,pObj)) )
continue; continue;
pInfoObj = Vec_PtrEntry( vInfo, i ); pInfoObj = (unsigned *)Vec_PtrEntry( vInfo, i );
for ( w = 0; w < nWords; w++ ) for ( w = 0; w < nWords; w++ )
assert( pInfoObj[w] == 0 ); assert( pInfoObj[w] == 0 );
// skip ROs with constant representatives // skip ROs with constant representatives
if ( Gia_ObjIsConst0(pRepr) ) if ( Gia_ObjIsConst0(pRepr) )
continue; continue;
assert( Gia_ObjIsRo(p, pRepr) ); assert( Gia_ObjIsRo(p, pRepr) );
// printf( "%d -> %d ", i, Gia_ObjId(p, pRepr) ); // Abc_Print( 1, "%d -> %d ", i, Gia_ObjId(p, pRepr) );
// transfer info from the representative // transfer info from the representative
pInfoRepr = Vec_PtrEntry( vInfo, Gia_ObjCioId(pRepr) - Gia_ManPiNum(p) ); pInfoRepr = (unsigned *)Vec_PtrEntry( vInfo, Gia_ObjCioId(pRepr) - Gia_ManPiNum(p) );
for ( w = 0; w < nWords; w++ ) for ( w = 0; w < nWords; w++ )
pInfoObj[w] = pInfoRepr[w]; pInfoObj[w] = pInfoRepr[w];
} }
// printf( "\n" ); // Abc_Print( 1, "\n" );
} }
/**Function************************************************************* /**Function*************************************************************
@ -368,7 +371,7 @@ Vec_Int_t * Gia_ManCorrCreateRemapping( Gia_Man_t * p )
// if ( pRepr == NULL || Gia_ObjIsConst0(pRepr) || Gia_ObjIsFailedPair(p, Gia_ObjId(p, pRepr), Gia_ObjId(p, pObj)) ) // if ( pRepr == NULL || Gia_ObjIsConst0(pRepr) || Gia_ObjIsFailedPair(p, Gia_ObjId(p, pRepr), Gia_ObjId(p, pObj)) )
continue; continue;
assert( Gia_ObjIsRo(p, pRepr) ); assert( Gia_ObjIsRo(p, pRepr) );
// printf( "%d -> %d ", Gia_ObjId(p,pObj), Gia_ObjId(p, pRepr) ); // Abc_Print( 1, "%d -> %d ", Gia_ObjId(p,pObj), Gia_ObjId(p, pRepr) );
// remember the pair // remember the pair
Vec_IntPush( vPairs, Gia_ObjCioId(pRepr) - Gia_ManPiNum(p) ); Vec_IntPush( vPairs, Gia_ObjCioId(pRepr) - Gia_ManPiNum(p) );
Vec_IntPush( vPairs, i ); Vec_IntPush( vPairs, i );
@ -395,8 +398,8 @@ void Gia_ManCorrPerformRemapping( Vec_Int_t * vPairs, Vec_Ptr_t * vInfo )
Vec_IntForEachEntry( vPairs, iRepr, i ) Vec_IntForEachEntry( vPairs, iRepr, i )
{ {
iObj = Vec_IntEntry( vPairs, ++i ); iObj = Vec_IntEntry( vPairs, ++i );
pInfoObj = Vec_PtrEntry( vInfo, iObj ); pInfoObj = (unsigned *)Vec_PtrEntry( vInfo, iObj );
pInfoRepr = Vec_PtrEntry( vInfo, iRepr ); pInfoRepr = (unsigned *)Vec_PtrEntry( vInfo, iRepr );
for ( w = 0; w < nWords; w++ ) for ( w = 0; w < nWords; w++ )
{ {
assert( pInfoObj[w] == 0 ); assert( pInfoObj[w] == 0 );
@ -422,16 +425,16 @@ int Cec_ManLoadCounterExamplesTry( Vec_Ptr_t * vInfo, Vec_Ptr_t * vPres, int iBi
int i; int i;
for ( i = 0; i < nLits; i++ ) for ( i = 0; i < nLits; i++ )
{ {
pInfo = Vec_PtrEntry(vInfo, Gia_Lit2Var(pLits[i])); pInfo = (unsigned *)Vec_PtrEntry(vInfo, Gia_Lit2Var(pLits[i]));
pPres = Vec_PtrEntry(vPres, Gia_Lit2Var(pLits[i])); pPres = (unsigned *)Vec_PtrEntry(vPres, Gia_Lit2Var(pLits[i]));
if ( Gia_InfoHasBit( pPres, iBit ) && if ( Gia_InfoHasBit( pPres, iBit ) &&
Gia_InfoHasBit( pInfo, iBit ) == Gia_LitIsCompl(pLits[i]) ) Gia_InfoHasBit( pInfo, iBit ) == Gia_LitIsCompl(pLits[i]) )
return 0; return 0;
} }
for ( i = 0; i < nLits; i++ ) for ( i = 0; i < nLits; i++ )
{ {
pInfo = Vec_PtrEntry(vInfo, Gia_Lit2Var(pLits[i])); pInfo = (unsigned *)Vec_PtrEntry(vInfo, Gia_Lit2Var(pLits[i]));
pPres = Vec_PtrEntry(vPres, Gia_Lit2Var(pLits[i])); pPres = (unsigned *)Vec_PtrEntry(vPres, Gia_Lit2Var(pLits[i]));
Gia_InfoSetBit( pPres, iBit ); Gia_InfoSetBit( pPres, iBit );
if ( Gia_InfoHasBit( pInfo, iBit ) == Gia_LitIsCompl(pLits[i]) ) if ( Gia_InfoHasBit( pInfo, iBit ) == Gia_LitIsCompl(pLits[i]) )
Gia_InfoXorBit( pInfo, iBit ); Gia_InfoXorBit( pInfo, iBit );
@ -506,7 +509,7 @@ int Cec_ManLoadCounterExamples2( Vec_Ptr_t * vInfo, Vec_Int_t * vCexStore, int i
// skip the output number // skip the output number
// iStart++; // iStart++;
Out = Vec_IntEntry( vCexStore, iStart++ ); Out = Vec_IntEntry( vCexStore, iStart++ );
// printf( "iBit = %d. Out = %d.\n", iBit, Out ); // Abc_Print( 1, "iBit = %d. Out = %d.\n", iBit, Out );
// get the number of items // get the number of items
nLits = Vec_IntEntry( vCexStore, iStart++ ); nLits = Vec_IntEntry( vCexStore, iStart++ );
if ( nLits <= 0 ) if ( nLits <= 0 )
@ -515,14 +518,14 @@ int Cec_ManLoadCounterExamples2( Vec_Ptr_t * vInfo, Vec_Int_t * vCexStore, int i
for ( k = 0; k < nLits; k++ ) for ( k = 0; k < nLits; k++ )
{ {
iLit = Vec_IntEntry( vCexStore, iStart++ ); iLit = Vec_IntEntry( vCexStore, iStart++ );
pInfo = Vec_PtrEntry( vInfo, Gia_Lit2Var(iLit) ); pInfo = (unsigned *)Vec_PtrEntry( vInfo, Gia_Lit2Var(iLit) );
if ( Gia_InfoHasBit( pInfo, iBit ) == Gia_LitIsCompl(iLit) ) if ( Gia_InfoHasBit( pInfo, iBit ) == Gia_LitIsCompl(iLit) )
Gia_InfoXorBit( pInfo, iBit ); Gia_InfoXorBit( pInfo, iBit );
} }
if ( ++iBit == nBits ) if ( ++iBit == nBits )
break; break;
} }
// printf( "added %d bits\n", iBit-1 ); // Abc_Print( 1, "added %d bits\n", iBit-1 );
return iStart; return iStart;
} }
@ -620,7 +623,7 @@ int Gia_ManCheckRefinements( Gia_Man_t * p, Vec_Str_t * vStatus, Vec_Int_t * vOu
if ( Gia_ObjHasSameRepr(p, iRepr, iObj) ) if ( Gia_ObjHasSameRepr(p, iRepr, iObj) )
Counter++; Counter++;
// if ( Gia_ObjHasSameRepr(p, iRepr, iObj) ) // if ( Gia_ObjHasSameRepr(p, iRepr, iObj) )
// printf( "Gia_ManCheckRefinements(): Disproved equivalence (%d,%d) is not refined!\n", iRepr, iObj ); // Abc_Print( 1, "Gia_ManCheckRefinements(): Disproved equivalence (%d,%d) is not refined!\n", iRepr, iObj );
// if ( Gia_ObjHasSameRepr(p, iRepr, iObj) ) // if ( Gia_ObjHasSameRepr(p, iRepr, iObj) )
// Cec_ManSimClassRemoveOne( pSim, iObj ); // Cec_ManSimClassRemoveOne( pSim, iObj );
continue; continue;
@ -628,7 +631,7 @@ int Gia_ManCheckRefinements( Gia_Man_t * p, Vec_Str_t * vStatus, Vec_Int_t * vOu
if ( status == -1 ) if ( status == -1 )
{ {
// if ( !Gia_ObjFailed( p, iObj ) ) // if ( !Gia_ObjFailed( p, iObj ) )
// printf( "Gia_ManCheckRefinements(): Failed equivalence is not marked as failed!\n" ); // Abc_Print( 1, "Gia_ManCheckRefinements(): Failed equivalence is not marked as failed!\n" );
// Gia_ObjSetFailed( p, iRepr ); // Gia_ObjSetFailed( p, iRepr );
// Gia_ObjSetFailed( p, iObj ); // Gia_ObjSetFailed( p, iObj );
// if ( fRings ) // if ( fRings )
@ -638,7 +641,7 @@ int Gia_ManCheckRefinements( Gia_Man_t * p, Vec_Str_t * vStatus, Vec_Int_t * vOu
} }
} }
// if ( Counter ) // if ( Counter )
// printf( "Gia_ManCheckRefinements(): Could not refine %d nodes.\n", Counter ); // Abc_Print( 1, "Gia_ManCheckRefinements(): Could not refine %d nodes.\n", Counter );
return 1; return 1;
} }
@ -732,10 +735,10 @@ void Cec_ManRefinedClassPrintStats( Gia_Man_t * p, Vec_Str_t * vStatus, int iIte
CounterX -= Gia_ManCoNum(p); CounterX -= Gia_ManCoNum(p);
nLits = Gia_ManCiNum(p) + Gia_ManAndNum(p) - Counter - CounterX; nLits = Gia_ManCiNum(p) + Gia_ManAndNum(p) - Counter - CounterX;
if ( iIter == -1 ) if ( iIter == -1 )
printf( "BMC : " ); Abc_Print( 1, "BMC : " );
else else
printf( "%3d : ", iIter ); Abc_Print( 1, "%3d : ", iIter );
printf( "c =%8d cl =%7d lit =%8d ", Counter0, Counter, nLits ); Abc_Print( 1, "c =%8d cl =%7d lit =%8d ", Counter0, Counter, nLits );
if ( vStatus ) if ( vStatus )
Vec_StrForEachEntry( vStatus, Entry, i ) Vec_StrForEachEntry( vStatus, Entry, i )
{ {
@ -746,8 +749,8 @@ void Cec_ManRefinedClassPrintStats( Gia_Man_t * p, Vec_Str_t * vStatus, int iIte
else if ( Entry == -1 ) else if ( Entry == -1 )
nFail++; nFail++;
} }
printf( "p =%6d d =%6d f =%6d ", nProve, nDispr, nFail ); Abc_Print( 1, "p =%6d d =%6d f =%6d ", nProve, nDispr, nFail );
ABC_PRT( "T", Time ); Abc_PrintTime( 1, "T", Time );
} }
/**Function************************************************************* /**Function*************************************************************
@ -833,7 +836,7 @@ int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
{ {
int nIterMax = 100000; int nIterMax = 100000;
int nAddFrames = 1; // additional timeframes to simulate int nAddFrames = 1; // additional timeframes to simulate
int fRunBmcFirst = 0; int fRunBmcFirst = 1;
Vec_Str_t * vStatus; Vec_Str_t * vStatus;
Vec_Int_t * vOutputs; Vec_Int_t * vOutputs;
Vec_Int_t * vCexStore; Vec_Int_t * vCexStore;
@ -846,7 +849,7 @@ int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
int clk2, clk = clock(); int clk2, clk = clock();
if ( Gia_ManRegNum(pAig) == 0 ) if ( Gia_ManRegNum(pAig) == 0 )
{ {
printf( "Cec_ManLatchCorrespondence(): Not a sequential AIG.\n" ); Abc_Print( 1, "Cec_ManLatchCorrespondence(): Not a sequential AIG.\n" );
return 0; return 0;
} }
Gia_ManRandom( 1 ); Gia_ManRandom( 1 );
@ -861,7 +864,7 @@ int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
pSim = Cec_ManSimStart( pAig, pParsSim ); pSim = Cec_ManSimStart( pAig, pParsSim );
if ( pAig->pReprs == NULL ) if ( pAig->pReprs == NULL )
{ {
Cec_ManSimClassesPrepare( pSim ); Cec_ManSimClassesPrepare( pSim, pPars->nLevelMax );
Cec_ManSimClassesRefine( pSim ); Cec_ManSimClassesRefine( pSim );
} }
// prepare SAT solving // prepare SAT solving
@ -870,7 +873,7 @@ int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
pParsSat->fVerbose = pPars->fVerbose; pParsSat->fVerbose = pPars->fVerbose;
if ( pPars->fVerbose ) if ( pPars->fVerbose )
{ {
printf( "Obj = %7d. And = %7d. Conf = %5d. Fr = %d. Lcorr = %d. Ring = %d. CSat = %d.\n", Abc_Print( 1, "Obj = %7d. And = %7d. Conf = %5d. Fr = %d. Lcorr = %d. Ring = %d. CSat = %d.\n",
Gia_ManObjNum(pAig), Gia_ManAndNum(pAig), Gia_ManObjNum(pAig), Gia_ManAndNum(pAig),
pPars->nBTLimit, pPars->nFrames, pPars->fLatchCorr, pPars->fUseRings, pPars->fUseCSat ); pPars->nBTLimit, pPars->nFrames, pPars->fLatchCorr, pPars->fUseRings, pPars->fUseCSat );
Cec_ManRefinedClassPrintStats( pAig, NULL, 0, clock() - clk ); Cec_ManRefinedClassPrintStats( pAig, NULL, 0, clock() - clk );
@ -878,9 +881,26 @@ int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
// check the base case // check the base case
if ( fRunBmcFirst && (!pPars->fLatchCorr || pPars->nFrames > 1) ) if ( fRunBmcFirst && (!pPars->fLatchCorr || pPars->nFrames > 1) )
Cec_ManLSCorrespondenceBmc( pAig, pPars, 0 ); Cec_ManLSCorrespondenceBmc( pAig, pPars, 0 );
if ( pPars->pFunc )
{
((int (*)(void *))pPars->pFunc)( pPars->pData );
((int (*)(void *))pPars->pFunc)( pPars->pData );
}
if ( pPars->nStepsMax == 0 )
{
Abc_Print( 1, "Stopped signal correspondence after BMC.\n" );
Cec_ManSimStop( pSim );
return 1;
}
// perform refinement of equivalence classes // perform refinement of equivalence classes
for ( r = 0; r < nIterMax; r++ ) for ( r = 0; r < nIterMax; r++ )
{ {
if ( pPars->nStepsMax == r )
{
Cec_ManSimStop( pSim );
Abc_Print( 1, "Stopped signal correspondence after %d refiment iterations.\n", r );
return 1;
}
clk = clock(); clk = clock();
// perform speculative reduction // perform speculative reduction
clk2 = clock(); clk2 = clock();
@ -920,12 +940,14 @@ int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
Vec_StrFree( vStatus ); Vec_StrFree( vStatus );
Vec_IntFree( vOutputs ); Vec_IntFree( vOutputs );
//Gia_ManEquivPrintClasses( pAig, 1, 0 ); //Gia_ManEquivPrintClasses( pAig, 1, 0 );
if ( pPars->pFunc )
((int (*)(void *))pPars->pFunc)( pPars->pData );
} }
if ( pPars->fVerbose ) if ( pPars->fVerbose )
Cec_ManRefinedClassPrintStats( pAig, NULL, r+1, clock() - clk ); Cec_ManRefinedClassPrintStats( pAig, NULL, r+1, clock() - clk );
// check the overflow // check the overflow
if ( r == nIterMax ) if ( r == nIterMax )
printf( "The refinement was not finished. The result may be incorrect.\n" ); Abc_Print( 1, "The refinement was not finished. The result may be incorrect.\n" );
Cec_ManSimStop( pSim ); Cec_ManSimStop( pSim );
// check the base case // check the base case
if ( !fRunBmcFirst && (!pPars->fLatchCorr || pPars->nFrames > 1) ) if ( !fRunBmcFirst && (!pPars->fLatchCorr || pPars->nFrames > 1) )
@ -938,9 +960,9 @@ int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
ABC_PRTP( "Sat ", clkSat, clkTotal ); ABC_PRTP( "Sat ", clkSat, clkTotal );
ABC_PRTP( "Sim ", clkSim, clkTotal ); ABC_PRTP( "Sim ", clkSim, clkTotal );
ABC_PRTP( "Other", clkTotal-clkSat-clkSrm-clkSim, clkTotal ); ABC_PRTP( "Other", clkTotal-clkSat-clkSrm-clkSim, clkTotal );
ABC_PRT( "TOTAL", clkTotal ); Abc_PrintTime( 1, "TOTAL", clkTotal );
} }
return 0; return 1;
} }
/**Function************************************************************* /**Function*************************************************************
@ -960,7 +982,7 @@ unsigned * Cec_ManComputeInitState( Gia_Man_t * pAig, int nFrames )
unsigned * pInitState; unsigned * pInitState;
int i, f; int i, f;
Gia_ManRandom( 1 ); Gia_ManRandom( 1 );
// printf( "Simulating %d timeframes.\n", nFrames ); // Abc_Print( 1, "Simulating %d timeframes.\n", nFrames );
Gia_ManForEachRo( pAig, pObj, i ) Gia_ManForEachRo( pAig, pObj, i )
pObj->fMark1 = 0; pObj->fMark1 = 0;
for ( f = 0; f < nFrames; f++ ) for ( f = 0; f < nFrames; f++ )
@ -981,9 +1003,9 @@ unsigned * Cec_ManComputeInitState( Gia_Man_t * pAig, int nFrames )
{ {
if ( pObj->fMark1 ) if ( pObj->fMark1 )
Gia_InfoSetBit( pInitState, i ); Gia_InfoSetBit( pInitState, i );
// printf( "%d", pObj->fMark1 ); // Abc_Print( 1, "%d", pObj->fMark1 );
} }
// printf( "\n" ); // Abc_Print( 1, "\n" );
Gia_ManCleanMark1( pAig ); Gia_ManCleanMark1( pAig );
return pInitState; return pInitState;
} }
@ -1007,15 +1029,15 @@ void Cec_ManPrintFlopEquivs( Gia_Man_t * p )
Gia_ManForEachRo( p, pObj, i ) Gia_ManForEachRo( p, pObj, i )
{ {
if ( Gia_ObjIsConst(p, Gia_ObjId(p, pObj)) ) if ( Gia_ObjIsConst(p, Gia_ObjId(p, pObj)) )
printf( "Original flop %s is proved equivalent to constant.\n", Vec_PtrEntry(p->vNamesIn, Gia_ObjCioId(pObj)) ); Abc_Print( 1, "Original flop %s is proved equivalent to constant.\n", Vec_PtrEntry(p->vNamesIn, Gia_ObjCioId(pObj)) );
else if ( (pRepr = Gia_ObjReprObj(p, Gia_ObjId(p, pObj))) ) else if ( (pRepr = Gia_ObjReprObj(p, Gia_ObjId(p, pObj))) )
{ {
if ( Gia_ObjIsCi(pRepr) ) if ( Gia_ObjIsCi(pRepr) )
printf( "Original flop %s is proved equivalent to flop %s.\n", Abc_Print( 1, "Original flop %s is proved equivalent to flop %s.\n",
Vec_PtrEntry( p->vNamesIn, Gia_ObjCioId(pObj) ), Vec_PtrEntry( p->vNamesIn, Gia_ObjCioId(pObj) ),
Vec_PtrEntry( p->vNamesIn, Gia_ObjCioId(pRepr) ) ); Vec_PtrEntry( p->vNamesIn, Gia_ObjCioId(pRepr) ) );
else else
printf( "Original flop %s is proved equivalent to internal node %d.\n", Abc_Print( 1, "Original flop %s is proved equivalent to internal node %d.\n",
Vec_PtrEntry( p->vNamesIn, Gia_ObjCioId(pObj) ), Gia_ObjId(p, pRepr) ); Vec_PtrEntry( p->vNamesIn, Gia_ObjCioId(pObj) ), Gia_ObjId(p, pRepr) );
} }
} }
@ -1046,7 +1068,7 @@ Gia_Man_t * Cec_ManLSCorrespondence( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
{ {
// compute the cycles AIG // compute the cycles AIG
pInitState = Cec_ManComputeInitState( pAig, pPars->nPrefix ); pInitState = Cec_ManComputeInitState( pAig, pPars->nPrefix );
pTemp = Gia_ManDupFlip( pAig, pInitState ); pTemp = Gia_ManDupFlip( pAig, (int *)pInitState );
ABC_FREE( pInitState ); ABC_FREE( pInitState );
// compute classes of this AIG // compute classes of this AIG
RetValue = Cec_ManLSCorrespondenceClasses( pTemp, pPars ); RetValue = Cec_ManLSCorrespondenceClasses( pTemp, pPars );
@ -1086,19 +1108,19 @@ Gia_Man_t * Cec_ManLSCorrespondence( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
// report the results // report the results
if ( pPars->fVerbose ) if ( pPars->fVerbose )
{ {
printf( "NBeg = %d. NEnd = %d. (Gain = %6.2f %%). RBeg = %d. REnd = %d. (Gain = %6.2f %%).\n", Abc_Print( 1, "NBeg = %d. NEnd = %d. (Gain = %6.2f %%). RBeg = %d. REnd = %d. (Gain = %6.2f %%).\n",
Gia_ManAndNum(pAig), Gia_ManAndNum(pNew), Gia_ManAndNum(pAig), Gia_ManAndNum(pNew),
100.0*(Gia_ManAndNum(pAig)-Gia_ManAndNum(pNew))/(Gia_ManAndNum(pAig)?Gia_ManAndNum(pAig):1), 100.0*(Gia_ManAndNum(pAig)-Gia_ManAndNum(pNew))/(Gia_ManAndNum(pAig)?Gia_ManAndNum(pAig):1),
Gia_ManRegNum(pAig), Gia_ManRegNum(pNew), Gia_ManRegNum(pAig), Gia_ManRegNum(pNew),
100.0*(Gia_ManRegNum(pAig)-Gia_ManRegNum(pNew))/(Gia_ManRegNum(pAig)?Gia_ManRegNum(pAig):1) ); 100.0*(Gia_ManRegNum(pAig)-Gia_ManRegNum(pNew))/(Gia_ManRegNum(pAig)?Gia_ManRegNum(pAig):1) );
} }
if ( pPars->nPrefix && (Gia_ManAndNum(pNew) < Gia_ManAndNum(pAig) || Gia_ManRegNum(pNew) < Gia_ManRegNum(pAig)) ) if ( pPars->nPrefix && (Gia_ManAndNum(pNew) < Gia_ManAndNum(pAig) || Gia_ManRegNum(pNew) < Gia_ManRegNum(pAig)) )
printf( "The reduced AIG was produced using %d-th invariants and will not verify.\n", pPars->nPrefix ); Abc_Print( 1, "The reduced AIG was produced using %d-th invariants and will not verify.\n", pPars->nPrefix );
// print verbose info about equivalences // print verbose info about equivalences
if ( pPars->fVerboseFlops ) if ( pPars->fVerboseFlops )
{ {
if ( pAig->vNamesIn == NULL ) if ( pAig->vNamesIn == NULL )
printf( "Flop output names are not available. Use command \"&get -n\".\n" ); Abc_Print( 1, "Flop output names are not available. Use command \"&get -n\".\n" );
else else
Cec_ManPrintFlopEquivs( pAig ); Cec_ManPrintFlopEquivs( pAig );
} }
@ -1110,3 +1132,5 @@ Gia_Man_t * Cec_ManLSCorrespondence( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

7
src/aig/cec/cecCorr_updated.c
View File

@ -20,6 +20,9 @@
#include "cecInt.h" #include "cecInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -970,7 +973,7 @@ int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
ABC_PRTP( "Other", clkTotal-clkSat-clkSrm-clkSim, clkTotal ); ABC_PRTP( "Other", clkTotal-clkSat-clkSrm-clkSim, clkTotal );
ABC_PRT( "TOTAL", clkTotal ); ABC_PRT( "TOTAL", clkTotal );
} }
return 0; return 1;
} }
/**Function************************************************************* /**Function*************************************************************
@ -1020,3 +1023,5 @@ Gia_Man_t * Cec_ManLSCorrespondence( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

26
src/aig/cec/cecInt.h
View File

@ -21,6 +21,7 @@
#ifndef __CEC_INT_H__ #ifndef __CEC_INT_H__
#define __CEC_INT_H__ #define __CEC_INT_H__
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// INCLUDES /// /// INCLUDES ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -34,9 +35,10 @@
/// PARAMETERS /// /// PARAMETERS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
extern "C" {
#endif ABC_NAMESPACE_HEADER_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// BASIC TYPES /// /// BASIC TYPES ///
@ -128,8 +130,8 @@ struct Cec_ManSim_t_
void ** pCexes; // counter-examples for each output void ** pCexes; // counter-examples for each output
int iOut; // first failed output int iOut; // first failed output
int nOuts; // the number of failed outputs int nOuts; // the number of failed outputs
Gia_Cex_t * pCexComb; // counter-example for the first failed output Abc_Cex_t * pCexComb; // counter-example for the first failed output
Gia_Cex_t * pBestState; // the state that led to most of the refinements Abc_Cex_t * pBestState; // the state that led to most of the refinements
// scoring simulation patterns // scoring simulation patterns
int * pScores; // counters of refinement for each pattern int * pScores; // counters of refinement for each pattern
// temporaries // temporaries
@ -170,7 +172,7 @@ struct Cec_ManFra_t_
extern void Cec_ManRefinedClassPrintStats( Gia_Man_t * p, Vec_Str_t * vStatus, int iIter, int Time ); extern void Cec_ManRefinedClassPrintStats( Gia_Man_t * p, Vec_Str_t * vStatus, int iIter, int Time );
/*=== cecClass.c ============================================================*/ /*=== cecClass.c ============================================================*/
extern int Cec_ManSimClassRemoveOne( Cec_ManSim_t * p, int i ); extern int Cec_ManSimClassRemoveOne( Cec_ManSim_t * p, int i );
extern int Cec_ManSimClassesPrepare( Cec_ManSim_t * p ); extern int Cec_ManSimClassesPrepare( Cec_ManSim_t * p, int LevelMax );
extern int Cec_ManSimClassesRefine( Cec_ManSim_t * p ); extern int Cec_ManSimClassesRefine( Cec_ManSim_t * p );
extern int Cec_ManSimSimulateRound( Cec_ManSim_t * p, Vec_Ptr_t * vInfoCis, Vec_Ptr_t * vInfoCos ); extern int Cec_ManSimSimulateRound( Cec_ManSim_t * p, Vec_Ptr_t * vInfoCis, Vec_Ptr_t * vInfoCos );
/*=== cecIso.c ============================================================*/ /*=== cecIso.c ============================================================*/
@ -192,8 +194,8 @@ extern Vec_Ptr_t * Cec_ManPatCollectPatterns( Cec_ManPat_t * pMan, int
extern Vec_Ptr_t * Cec_ManPatPackPatterns( Vec_Int_t * vCexStore, int nInputs, int nRegs, int nWordsInit ); extern Vec_Ptr_t * Cec_ManPatPackPatterns( Vec_Int_t * vCexStore, int nInputs, int nRegs, int nWordsInit );
/*=== cecSeq.c ============================================================*/ /*=== cecSeq.c ============================================================*/
extern int Cec_ManSeqResimulate( Cec_ManSim_t * p, Vec_Ptr_t * vInfo ); extern int Cec_ManSeqResimulate( Cec_ManSim_t * p, Vec_Ptr_t * vInfo );
extern int Cec_ManSeqResimulateInfo( Gia_Man_t * pAig, Vec_Ptr_t * vSimInfo, Gia_Cex_t * pBestState, int fCheckMiter ); extern int Cec_ManSeqResimulateInfo( Gia_Man_t * pAig, Vec_Ptr_t * vSimInfo, Abc_Cex_t * pBestState, int fCheckMiter );
extern void Cec_ManSeqDeriveInfoInitRandom( Vec_Ptr_t * vInfo, Gia_Man_t * pAig, Gia_Cex_t * pCex ); extern void Cec_ManSeqDeriveInfoInitRandom( Vec_Ptr_t * vInfo, Gia_Man_t * pAig, Abc_Cex_t * pCex );
extern int Cec_ManCountNonConstOutputs( Gia_Man_t * pAig ); extern int Cec_ManCountNonConstOutputs( Gia_Man_t * pAig );
extern int Cec_ManCheckNonTrivialCands( Gia_Man_t * pAig ); extern int Cec_ManCheckNonTrivialCands( Gia_Man_t * pAig );
/*=== cecSolve.c ============================================================*/ /*=== cecSolve.c ============================================================*/
@ -209,9 +211,11 @@ extern Vec_Int_t * Cec_ManSatReadCex( Cec_ManSat_t * p );
extern Gia_Man_t * Cec_ManFraSpecReduction( Cec_ManFra_t * p ); extern Gia_Man_t * Cec_ManFraSpecReduction( Cec_ManFra_t * p );
extern int Cec_ManFraClassesUpdate( Cec_ManFra_t * p, Cec_ManSim_t * pSim, Cec_ManPat_t * pPat, Gia_Man_t * pNew ); extern int Cec_ManFraClassesUpdate( Cec_ManFra_t * p, Cec_ManSim_t * pSim, Cec_ManPat_t * pPat, Gia_Man_t * pNew );
#ifdef __cplusplus
}
#endif ABC_NAMESPACE_HEADER_END
#endif #endif

11
src/aig/cec/cecIso.c
View File

@ -20,6 +20,9 @@
#include "cecInt.h" #include "cecInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -348,13 +351,13 @@ int * Cec_ManDetectIsomorphism( Gia_Man_t * p )
{ {
if ( (Gia_ObjIsHead(p,pIso[i]) && Gia_ObjRepr(p,i)==pIso[i]) || if ( (Gia_ObjIsHead(p,pIso[i]) && Gia_ObjRepr(p,i)==pIso[i]) ||
(Gia_ObjIsClass(p,pIso[i]) && Gia_ObjRepr(p,i)==Gia_ObjRepr(p,pIso[i])) ) (Gia_ObjIsClass(p,pIso[i]) && Gia_ObjRepr(p,i)==Gia_ObjRepr(p,pIso[i])) )
printf( "1" ); Abc_Print( 1, "1" );
else else
printf( "0" ); Abc_Print( 1, "0" );
} }
*/ */
} }
printf( "Computed %d pairs of structurally equivalent nodes.\n", Counter ); Abc_Print( 1, "Computed %d pairs of structurally equivalent nodes.\n", Counter );
// p->pIso = pIso; // p->pIso = pIso;
// Cec_ManTransformClasses( p ); // Cec_ManTransformClasses( p );
@ -368,3 +371,5 @@ int * Cec_ManDetectIsomorphism( Gia_Man_t * p )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

45
src/aig/cec/cecMan.c
View File

@ -20,6 +20,9 @@
#include "cecInt.h" #include "cecInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -70,21 +73,21 @@ Cec_ManSat_t * Cec_ManSatCreate( Gia_Man_t * pAig, Cec_ParSat_t * pPars )
***********************************************************************/ ***********************************************************************/
void Cec_ManSatPrintStats( Cec_ManSat_t * p ) void Cec_ManSatPrintStats( Cec_ManSat_t * p )
{ {
printf( "CO = %8d ", Gia_ManCoNum(p->pAig) ); Abc_Print( 1, "CO = %8d ", Gia_ManCoNum(p->pAig) );
printf( "AND = %8d ", Gia_ManAndNum(p->pAig) ); Abc_Print( 1, "AND = %8d ", Gia_ManAndNum(p->pAig) );
printf( "Conf = %5d ", p->pPars->nBTLimit ); Abc_Print( 1, "Conf = %5d ", p->pPars->nBTLimit );
printf( "MinVar = %5d ", p->pPars->nSatVarMax ); Abc_Print( 1, "MinVar = %5d ", p->pPars->nSatVarMax );
printf( "MinCalls = %5d\n", p->pPars->nCallsRecycle ); Abc_Print( 1, "MinCalls = %5d\n", p->pPars->nCallsRecycle );
printf( "Unsat calls %6d (%6.2f %%) Ave conf = %8.1f ", Abc_Print( 1, "Unsat calls %6d (%6.2f %%) Ave conf = %8.1f ",
p->nSatUnsat, p->nSatTotal? 100.0*p->nSatUnsat/p->nSatTotal : 0.0, p->nSatUnsat? 1.0*p->nConfUnsat/p->nSatUnsat :0.0 ); p->nSatUnsat, p->nSatTotal? 100.0*p->nSatUnsat/p->nSatTotal : 0.0, p->nSatUnsat? 1.0*p->nConfUnsat/p->nSatUnsat :0.0 );
ABC_PRTP( "Time", p->timeSatUnsat, p->timeTotal ); Abc_PrintTimeP( 1, "Time", p->timeSatUnsat, p->timeTotal );
printf( "Sat calls %6d (%6.2f %%) Ave conf = %8.1f ", Abc_Print( 1, "Sat calls %6d (%6.2f %%) Ave conf = %8.1f ",
p->nSatSat, p->nSatTotal? 100.0*p->nSatSat/p->nSatTotal : 0.0, p->nSatSat? 1.0*p->nConfSat/p->nSatSat : 0.0 ); p->nSatSat, p->nSatTotal? 100.0*p->nSatSat/p->nSatTotal : 0.0, p->nSatSat? 1.0*p->nConfSat/p->nSatSat : 0.0 );
ABC_PRTP( "Time", p->timeSatSat, p->timeTotal ); Abc_PrintTimeP( 1, "Time", p->timeSatSat, p->timeTotal );
printf( "Undef calls %6d (%6.2f %%) Ave conf = %8.1f ", Abc_Print( 1, "Undef calls %6d (%6.2f %%) Ave conf = %8.1f ",
p->nSatUndec, p->nSatTotal? 100.0*p->nSatUndec/p->nSatTotal : 0.0, p->nSatUndec? 1.0*p->nConfUndec/p->nSatUndec : 0.0 ); p->nSatUndec, p->nSatTotal? 100.0*p->nSatUndec/p->nSatTotal : 0.0, p->nSatUndec? 1.0*p->nConfUndec/p->nSatUndec : 0.0 );
ABC_PRTP( "Time", p->timeSatUndec, p->timeTotal ); Abc_PrintTimeP( 1, "Time", p->timeSatUndec, p->timeTotal );
ABC_PRT( "Total time", p->timeTotal ); Abc_PrintTime( 1, "Total time", p->timeTotal );
} }
/**Function************************************************************* /**Function*************************************************************
@ -146,18 +149,18 @@ Cec_ManPat_t * Cec_ManPatStart()
***********************************************************************/ ***********************************************************************/
void Cec_ManPatPrintStats( Cec_ManPat_t * p ) void Cec_ManPatPrintStats( Cec_ManPat_t * p )
{ {
printf( "Latest: P = %8d. L = %10d. Lm = %10d. Ave = %6.1f. MEM =%6.2f Mb\n", Abc_Print( 1, "Latest: P = %8d. L = %10d. Lm = %10d. Ave = %6.1f. MEM =%6.2f Mb\n",
p->nPats, p->nPatLits, p->nPatLitsMin, 1.0 * p->nPatLitsMin/p->nPats, p->nPats, p->nPatLits, p->nPatLitsMin, 1.0 * p->nPatLitsMin/p->nPats,
1.0*(Vec_StrSize(p->vStorage)-p->iStart)/(1<<20) ); 1.0*(Vec_StrSize(p->vStorage)-p->iStart)/(1<<20) );
printf( "Total: P = %8d. L = %10d. Lm = %10d. Ave = %6.1f. MEM =%6.2f Mb\n", Abc_Print( 1, "Total: P = %8d. L = %10d. Lm = %10d. Ave = %6.1f. MEM =%6.2f Mb\n",
p->nPatsAll, p->nPatLitsAll, p->nPatLitsMinAll, 1.0 * p->nPatLitsMinAll/p->nPatsAll, p->nPatsAll, p->nPatLitsAll, p->nPatLitsMinAll, 1.0 * p->nPatLitsMinAll/p->nPatsAll,
1.0*Vec_StrSize(p->vStorage)/(1<<20) ); 1.0*Vec_StrSize(p->vStorage)/(1<<20) );
ABC_PRTP( "Finding ", p->timeFind, p->timeTotal ); Abc_PrintTimeP( 1, "Finding ", p->timeFind, p->timeTotal );
ABC_PRTP( "Shrinking", p->timeShrink, p->timeTotal ); Abc_PrintTimeP( 1, "Shrinking", p->timeShrink, p->timeTotal );
ABC_PRTP( "Verifying", p->timeVerify, p->timeTotal ); Abc_PrintTimeP( 1, "Verifying", p->timeVerify, p->timeTotal );
ABC_PRTP( "Sorting ", p->timeSort, p->timeTotal ); Abc_PrintTimeP( 1, "Sorting ", p->timeSort, p->timeTotal );
ABC_PRTP( "Packing ", p->timePack, p->timeTotal ); Abc_PrintTimeP( 1, "Packing ", p->timePack, p->timeTotal );
ABC_PRT( "TOTAL ", p->timeTotal ); Abc_PrintTime( 1, "TOTAL ", p->timeTotal );
} }
/**Function************************************************************* /**Function*************************************************************
@ -290,3 +293,5 @@ void Cec_ManFraStop( Cec_ManFra_t * p )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

19
src/aig/cec/cecPat.c
View File

@ -20,6 +20,9 @@
#include "cecInt.h" #include "cecInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -296,7 +299,7 @@ void Cec_ManPatVerifyPattern( Gia_Man_t * p, Gia_Obj_t * pObj, Vec_Int_t * vPat
Value = Cec_ManPatComputePattern3_rec( p, Gia_ObjFanin0(pObj) ); Value = Cec_ManPatComputePattern3_rec( p, Gia_ObjFanin0(pObj) );
Value = Gia_XsimNotCond( Value, Gia_ObjFaninC0(pObj) ); Value = Gia_XsimNotCond( Value, Gia_ObjFaninC0(pObj) );
if ( Value != GIA_ONE ) if ( Value != GIA_ONE )
printf( "Cec_ManPatVerifyPattern(): Verification failed.\n" ); Abc_Print( 1, "Cec_ManPatVerifyPattern(): Verification failed.\n" );
assert( Value == GIA_ONE ); assert( Value == GIA_ONE );
} }
@ -412,16 +415,16 @@ int Cec_ManPatCollectTry( Vec_Ptr_t * vInfo, Vec_Ptr_t * vPres, int iBit, int *
int i; int i;
for ( i = 0; i < nLits; i++ ) for ( i = 0; i < nLits; i++ )
{ {
pInfo = Vec_PtrEntry(vInfo, Gia_Lit2Var(pLits[i])); pInfo = (unsigned *)Vec_PtrEntry(vInfo, Gia_Lit2Var(pLits[i]));
pPres = Vec_PtrEntry(vPres, Gia_Lit2Var(pLits[i])); pPres = (unsigned *)Vec_PtrEntry(vPres, Gia_Lit2Var(pLits[i]));
if ( Gia_InfoHasBit( pPres, iBit ) && if ( Gia_InfoHasBit( pPres, iBit ) &&
Gia_InfoHasBit( pInfo, iBit ) == Gia_LitIsCompl(pLits[i]) ) Gia_InfoHasBit( pInfo, iBit ) == Gia_LitIsCompl(pLits[i]) )
return 0; return 0;
} }
for ( i = 0; i < nLits; i++ ) for ( i = 0; i < nLits; i++ )
{ {
pInfo = Vec_PtrEntry(vInfo, Gia_Lit2Var(pLits[i])); pInfo = (unsigned *)Vec_PtrEntry(vInfo, Gia_Lit2Var(pLits[i]));
pPres = Vec_PtrEntry(vPres, Gia_Lit2Var(pLits[i])); pPres = (unsigned *)Vec_PtrEntry(vPres, Gia_Lit2Var(pLits[i]));
Gia_InfoSetBit( pPres, iBit ); Gia_InfoSetBit( pPres, iBit );
if ( Gia_InfoHasBit( pInfo, iBit ) == Gia_LitIsCompl(pLits[i]) ) if ( Gia_InfoHasBit( pInfo, iBit ) == Gia_LitIsCompl(pLits[i]) )
Gia_InfoXorBit( pInfo, iBit ); Gia_InfoXorBit( pInfo, iBit );
@ -478,7 +481,7 @@ Vec_Ptr_t * Cec_ManPatCollectPatterns( Cec_ManPat_t * pMan, int nInputs, int nW
pMan->iStart = iStartOld; pMan->iStart = iStartOld;
if ( pMan->fVerbose ) if ( pMan->fVerbose )
{ {
printf( "Total = %5d. Max used = %5d. Full = %5d. Series = %d. ", Abc_Print( 1, "Total = %5d. Max used = %5d. Full = %5d. Series = %d. ",
nPatterns, kMax, nWordsInit*32, pMan->nSeries ); nPatterns, kMax, nWordsInit*32, pMan->nSeries );
ABC_PRT( "Time", clock() - clk ); ABC_PRT( "Time", clock() - clk );
Cec_ManPatPrintStats( pMan ); Cec_ManPatPrintStats( pMan );
@ -551,7 +554,7 @@ Vec_Ptr_t * Cec_ManPatPackPatterns( Vec_Int_t * vCexStore, int nInputs, int nReg
nBits *= 2; nBits *= 2;
} }
} }
// printf( "packed %d patterns into %d vectors (out of %d)\n", nPatterns, kMax, nBits ); // Abc_Print( 1, "packed %d patterns into %d vectors (out of %d)\n", nPatterns, kMax, nBits );
Vec_PtrFree( vPres ); Vec_PtrFree( vPres );
Vec_IntFree( vPat ); Vec_IntFree( vPat );
return vInfo; return vInfo;
@ -562,3 +565,5 @@ Vec_Ptr_t * Cec_ManPatPackPatterns( Vec_Int_t * vCexStore, int nInputs, int nReg
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

71
src/aig/cec/cecSeq.c
View File

@ -20,6 +20,9 @@
#include "cecInt.h" #include "cecInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -39,7 +42,7 @@
SeeAlso [] SeeAlso []
***********************************************************************/ ***********************************************************************/
void Cec_ManSeqDeriveInfoFromCex( Vec_Ptr_t * vInfo, Gia_Man_t * pAig, Gia_Cex_t * pCex ) void Cec_ManSeqDeriveInfoFromCex( Vec_Ptr_t * vInfo, Gia_Man_t * pAig, Abc_Cex_t * pCex )
{ {
unsigned * pInfo; unsigned * pInfo;
int k, i, w, nWords; int k, i, w, nWords;
@ -56,14 +59,14 @@ void Cec_ManSeqDeriveInfoFromCex( Vec_Ptr_t * vInfo, Gia_Man_t * pAig, Gia_Cex_t
*/ */
for ( k = 0; k < Gia_ManRegNum(pAig); k++ ) for ( k = 0; k < Gia_ManRegNum(pAig); k++ )
{ {
pInfo = Vec_PtrEntry( vInfo, k ); pInfo = (unsigned *)Vec_PtrEntry( vInfo, k );
for ( w = 0; w < nWords; w++ ) for ( w = 0; w < nWords; w++ )
pInfo[w] = 0; pInfo[w] = 0;
} }
for ( i = pCex->nRegs; i < pCex->nBits; i++ ) for ( i = pCex->nRegs; i < pCex->nBits; i++ )
{ {
pInfo = Vec_PtrEntry( vInfo, k++ ); pInfo = (unsigned *)Vec_PtrEntry( vInfo, k++ );
for ( w = 0; w < nWords; w++ ) for ( w = 0; w < nWords; w++ )
pInfo[w] = Gia_ManRandom(0); pInfo[w] = Gia_ManRandom(0);
// set simulation pattern and make sure it is second (first will be erased during simulation) // set simulation pattern and make sure it is second (first will be erased during simulation)
@ -72,7 +75,7 @@ void Cec_ManSeqDeriveInfoFromCex( Vec_Ptr_t * vInfo, Gia_Man_t * pAig, Gia_Cex_t
} }
for ( ; k < Vec_PtrSize(vInfo); k++ ) for ( ; k < Vec_PtrSize(vInfo); k++ )
{ {
pInfo = Vec_PtrEntry( vInfo, k ); pInfo = (unsigned *)Vec_PtrEntry( vInfo, k );
for ( w = 0; w < nWords; w++ ) for ( w = 0; w < nWords; w++ )
pInfo[w] = Gia_ManRandom(0); pInfo[w] = Gia_ManRandom(0);
} }
@ -89,7 +92,7 @@ void Cec_ManSeqDeriveInfoFromCex( Vec_Ptr_t * vInfo, Gia_Man_t * pAig, Gia_Cex_t
SeeAlso [] SeeAlso []
***********************************************************************/ ***********************************************************************/
void Cec_ManSeqDeriveInfoInitRandom( Vec_Ptr_t * vInfo, Gia_Man_t * pAig, Gia_Cex_t * pCex ) void Cec_ManSeqDeriveInfoInitRandom( Vec_Ptr_t * vInfo, Gia_Man_t * pAig, Abc_Cex_t * pCex )
{ {
unsigned * pInfo; unsigned * pInfo;
int k, w, nWords; int k, w, nWords;
@ -98,14 +101,14 @@ void Cec_ManSeqDeriveInfoInitRandom( Vec_Ptr_t * vInfo, Gia_Man_t * pAig, Gia_Ce
assert( Gia_ManRegNum(pAig) <= Vec_PtrSize(vInfo) ); assert( Gia_ManRegNum(pAig) <= Vec_PtrSize(vInfo) );
for ( k = 0; k < Gia_ManRegNum(pAig); k++ ) for ( k = 0; k < Gia_ManRegNum(pAig); k++ )
{ {
pInfo = Vec_PtrEntry( vInfo, k ); pInfo = (unsigned *)Vec_PtrEntry( vInfo, k );
for ( w = 0; w < nWords; w++ ) for ( w = 0; w < nWords; w++ )
pInfo[w] = (pCex && Gia_InfoHasBit(pCex->pData, k))? ~0 : 0; pInfo[w] = (pCex && Gia_InfoHasBit(pCex->pData, k))? ~0 : 0;
} }
for ( ; k < Vec_PtrSize(vInfo); k++ ) for ( ; k < Vec_PtrSize(vInfo); k++ )
{ {
pInfo = Vec_PtrEntry( vInfo, k ); pInfo = (unsigned *)Vec_PtrEntry( vInfo, k );
for ( w = 0; w < nWords; w++ ) for ( w = 0; w < nWords; w++ )
pInfo[w] = Gia_ManRandom( 0 ); pInfo[w] = Gia_ManRandom( 0 );
} }
@ -130,8 +133,8 @@ int Cec_ManSeqResimulate( Cec_ManSim_t * p, Vec_Ptr_t * vInfo )
assert( Vec_PtrSize(vInfo) == Gia_ManRegNum(p->pAig) + Gia_ManPiNum(p->pAig) * p->pPars->nFrames ); assert( Vec_PtrSize(vInfo) == Gia_ManRegNum(p->pAig) + Gia_ManPiNum(p->pAig) * p->pPars->nFrames );
for ( k = 0; k < Gia_ManRegNum(p->pAig); k++ ) for ( k = 0; k < Gia_ManRegNum(p->pAig); k++ )
{ {
pInfo0 = Vec_PtrEntry( vInfo, k ); pInfo0 = (unsigned *)Vec_PtrEntry( vInfo, k );
pInfo1 = Vec_PtrEntry( p->vCoSimInfo, Gia_ManPoNum(p->pAig) + k ); pInfo1 = (unsigned *)Vec_PtrEntry( p->vCoSimInfo, Gia_ManPoNum(p->pAig) + k );
for ( w = 0; w < p->nWords; w++ ) for ( w = 0; w < p->nWords; w++ )
pInfo1[w] = pInfo0[w]; pInfo1[w] = pInfo0[w];
} }
@ -139,15 +142,15 @@ int Cec_ManSeqResimulate( Cec_ManSim_t * p, Vec_Ptr_t * vInfo )
{ {
for ( i = 0; i < Gia_ManPiNum(p->pAig); i++ ) for ( i = 0; i < Gia_ManPiNum(p->pAig); i++ )
{ {
pInfo0 = Vec_PtrEntry( vInfo, k++ ); pInfo0 = (unsigned *)Vec_PtrEntry( vInfo, k++ );
pInfo1 = Vec_PtrEntry( p->vCiSimInfo, i ); pInfo1 = (unsigned *)Vec_PtrEntry( p->vCiSimInfo, i );
for ( w = 0; w < p->nWords; w++ ) for ( w = 0; w < p->nWords; w++ )
pInfo1[w] = pInfo0[w]; pInfo1[w] = pInfo0[w];
} }
for ( i = 0; i < Gia_ManRegNum(p->pAig); i++ ) for ( i = 0; i < Gia_ManRegNum(p->pAig); i++ )
{ {
pInfo0 = Vec_PtrEntry( p->vCoSimInfo, Gia_ManPoNum(p->pAig) + i ); pInfo0 = (unsigned *)Vec_PtrEntry( p->vCoSimInfo, Gia_ManPoNum(p->pAig) + i );
pInfo1 = Vec_PtrEntry( p->vCiSimInfo, Gia_ManPiNum(p->pAig) + i ); pInfo1 = (unsigned *)Vec_PtrEntry( p->vCiSimInfo, Gia_ManPiNum(p->pAig) + i );
for ( w = 0; w < p->nWords; w++ ) for ( w = 0; w < p->nWords; w++ )
pInfo1[w] = pInfo0[w]; pInfo1[w] = pInfo0[w];
} }
@ -169,7 +172,7 @@ int Cec_ManSeqResimulate( Cec_ManSim_t * p, Vec_Ptr_t * vInfo )
SeeAlso [] SeeAlso []
***********************************************************************/ ***********************************************************************/
int Cec_ManSeqResimulateInfo( Gia_Man_t * pAig, Vec_Ptr_t * vSimInfo, Gia_Cex_t * pBestState, int fCheckMiter ) int Cec_ManSeqResimulateInfo( Gia_Man_t * pAig, Vec_Ptr_t * vSimInfo, Abc_Cex_t * pBestState, int fCheckMiter )
{ {
Cec_ParSim_t ParsSim, * pParsSim = &ParsSim; Cec_ParSim_t ParsSim, * pParsSim = &ParsSim;
Cec_ManSim_t * pSim; Cec_ManSim_t * pSim;
@ -200,33 +203,33 @@ int Cec_ManSeqResimulateInfo( Gia_Man_t * pAig, Vec_Ptr_t * vSimInfo, Gia_Cex_t
SeeAlso [] SeeAlso []
***********************************************************************/ ***********************************************************************/
int Cec_ManSeqResimulateCounter( Gia_Man_t * pAig, Cec_ParSim_t * pPars, Gia_Cex_t * pCex ) int Cec_ManSeqResimulateCounter( Gia_Man_t * pAig, Cec_ParSim_t * pPars, Abc_Cex_t * pCex )
{ {
Vec_Ptr_t * vSimInfo; Vec_Ptr_t * vSimInfo;
int RetValue, clkTotal = clock(); int RetValue, clkTotal = clock();
if ( pCex == NULL ) if ( pCex == NULL )
{ {
printf( "Cec_ManSeqResimulateCounter(): Counter-example is not available.\n" ); Abc_Print( 1, "Cec_ManSeqResimulateCounter(): Counter-example is not available.\n" );
return -1; return -1;
} }
if ( pAig->pReprs == NULL ) if ( pAig->pReprs == NULL )
{ {
printf( "Cec_ManSeqResimulateCounter(): Equivalence classes are not available.\n" ); Abc_Print( 1, "Cec_ManSeqResimulateCounter(): Equivalence classes are not available.\n" );
return -1; return -1;
} }
if ( Gia_ManRegNum(pAig) == 0 ) if ( Gia_ManRegNum(pAig) == 0 )
{ {
printf( "Cec_ManSeqResimulateCounter(): Not a sequential AIG.\n" ); Abc_Print( 1, "Cec_ManSeqResimulateCounter(): Not a sequential AIG.\n" );
return -1; return -1;
} }
// if ( Gia_ManRegNum(pAig) != pCex->nRegs || Gia_ManPiNum(pAig) != pCex->nPis ) // if ( Gia_ManRegNum(pAig) != pCex->nRegs || Gia_ManPiNum(pAig) != pCex->nPis )
if ( Gia_ManPiNum(pAig) != pCex->nPis ) if ( Gia_ManPiNum(pAig) != pCex->nPis )
{ {
printf( "Cec_ManSeqResimulateCounter(): The number of PIs in the AIG and the counter-example differ.\n" ); Abc_Print( 1, "Cec_ManSeqResimulateCounter(): The number of PIs in the AIG and the counter-example differ.\n" );
return -1; return -1;
} }
if ( pPars->fVerbose ) if ( pPars->fVerbose )
printf( "Resimulating %d timeframes.\n", pPars->nFrames + pCex->iFrame + 1 ); Abc_Print( 1, "Resimulating %d timeframes.\n", pPars->nFrames + pCex->iFrame + 1 );
Gia_ManRandom( 1 ); Gia_ManRandom( 1 );
vSimInfo = Vec_PtrAllocSimInfo( Gia_ManRegNum(pAig) + vSimInfo = Vec_PtrAllocSimInfo( Gia_ManRegNum(pAig) +
Gia_ManPiNum(pAig) * (pPars->nFrames + pCex->iFrame + 1), 1 ); Gia_ManPiNum(pAig) * (pPars->nFrames + pCex->iFrame + 1), 1 );
@ -240,7 +243,7 @@ int Cec_ManSeqResimulateCounter( Gia_Man_t * pAig, Cec_ParSim_t * pPars, Gia_Cex
if ( pPars->fVerbose ) if ( pPars->fVerbose )
ABC_PRT( "Time", clock() - clkTotal ); ABC_PRT( "Time", clock() - clkTotal );
if ( RetValue ) if ( RetValue )
printf( "Cec_ManSeqResimulateCounter(): An output of the miter is asserted!\n" ); Abc_Print( 1, "Cec_ManSeqResimulateCounter(): An output of the miter is asserted!\n" );
return RetValue; return RetValue;
} }
@ -320,17 +323,17 @@ int Cec_ManSeqSemiformal( Gia_Man_t * pAig, Cec_ParSmf_t * pPars )
Cec_ParSat_t ParsSat, * pParsSat = &ParsSat; Cec_ParSat_t ParsSat, * pParsSat = &ParsSat;
Vec_Ptr_t * vSimInfo; Vec_Ptr_t * vSimInfo;
Vec_Str_t * vStatus; Vec_Str_t * vStatus;
Gia_Cex_t * pState; Abc_Cex_t * pState;
Gia_Man_t * pSrm, * pReduce, * pAux; Gia_Man_t * pSrm, * pReduce, * pAux;
int r, nPats, RetValue = 0; int r, nPats, RetValue = 0;
if ( pAig->pReprs == NULL ) if ( pAig->pReprs == NULL )
{ {
printf( "Cec_ManSeqSemiformal(): Equivalence classes are not available.\n" ); Abc_Print( 1, "Cec_ManSeqSemiformal(): Equivalence classes are not available.\n" );
return -1; return -1;
} }
if ( Gia_ManRegNum(pAig) == 0 ) if ( Gia_ManRegNum(pAig) == 0 )
{ {
printf( "Cec_ManSeqSemiformal(): Not a sequential AIG.\n" ); Abc_Print( 1, "Cec_ManSeqSemiformal(): Not a sequential AIG.\n" );
return -1; return -1;
} }
Gia_ManRandom( 1 ); Gia_ManRandom( 1 );
@ -344,7 +347,7 @@ int Cec_ManSeqSemiformal( Gia_Man_t * pAig, Cec_ParSmf_t * pPars )
pParsSat->fVerbose = pPars->fVerbose; pParsSat->fVerbose = pPars->fVerbose;
if ( pParsSat->fVerbose ) if ( pParsSat->fVerbose )
{ {
printf( "Starting: " ); Abc_Print( 1, "Starting: " );
Gia_ManEquivPrintClasses( pAig, 0, 0 ); Gia_ManEquivPrintClasses( pAig, 0, 0 );
} }
// perform the given number of BMC rounds // perform the given number of BMC rounds
@ -353,7 +356,7 @@ int Cec_ManSeqSemiformal( Gia_Man_t * pAig, Cec_ParSmf_t * pPars )
{ {
if ( !Cec_ManCheckNonTrivialCands(pAig) ) if ( !Cec_ManCheckNonTrivialCands(pAig) )
{ {
printf( "Cec_ManSeqSemiformal: There are only trivial equiv candidates left (PO drivers). Quitting.\n" ); Abc_Print( 1, "Cec_ManSeqSemiformal: There are only trivial equiv candidates left (PO drivers). Quitting.\n" );
break; break;
} }
// Gia_ManPrintCounterExample( pState ); // Gia_ManPrintCounterExample( pState );
@ -362,12 +365,12 @@ int Cec_ManSeqSemiformal( Gia_Man_t * pAig, Cec_ParSmf_t * pPars )
pSrm = Gia_ManSpecReduceInitFrames( pAig, pState, pPars->nFrames, &nFramesReal, pPars->fDualOut, pPars->nMinOutputs ); pSrm = Gia_ManSpecReduceInitFrames( pAig, pState, pPars->nFrames, &nFramesReal, pPars->fDualOut, pPars->nMinOutputs );
if ( pSrm == NULL ) if ( pSrm == NULL )
{ {
printf( "Quitting refinement because miter could not be unrolled.\n" ); Abc_Print( 1, "Quitting refinement because miter could not be unrolled.\n" );
break; break;
} }
assert( Gia_ManRegNum(pSrm) == 0 && Gia_ManPiNum(pSrm) == (Gia_ManPiNum(pAig) * nFramesReal) ); assert( Gia_ManRegNum(pSrm) == 0 && Gia_ManPiNum(pSrm) == (Gia_ManPiNum(pAig) * nFramesReal) );
if ( pPars->fVerbose ) if ( pPars->fVerbose )
printf( "Unrolled for %d frames.\n", nFramesReal ); Abc_Print( 1, "Unrolled for %d frames.\n", nFramesReal );
// allocate room for simulation info // allocate room for simulation info
vSimInfo = Vec_PtrAllocSimInfo( Gia_ManRegNum(pAig) + vSimInfo = Vec_PtrAllocSimInfo( Gia_ManRegNum(pAig) +
Gia_ManPiNum(pAig) * (nFramesReal + nAddFrames), pPars->nWords ); Gia_ManPiNum(pAig) * (nFramesReal + nAddFrames), pPars->nWords );
@ -383,27 +386,27 @@ int Cec_ManSeqSemiformal( Gia_Man_t * pAig, Cec_ParSmf_t * pPars )
pState->iPo = -1; pState->iPo = -1;
if ( pPars->fVerbose ) if ( pPars->fVerbose )
{ {
printf( "BMC = %3d ", nPats ); Abc_Print( 1, "BMC = %3d ", nPats );
Gia_ManEquivPrintClasses( pAig, 0, 0 ); Gia_ManEquivPrintClasses( pAig, 0, 0 );
} }
// write equivalence classes // write equivalence classes
Gia_WriteAiger( pAig, "gore.aig", 0, 0 ); Gia_WriteAiger( pAig, "gore.aig", 0, 0 );
// reduce the model // reduce the model
pReduce = Gia_ManSpecReduce( pAig, 0, 0 ); pReduce = Gia_ManSpecReduce( pAig, 0, 0, 0 );
if ( pReduce ) if ( pReduce )
{ {
pReduce = Gia_ManSeqStructSweep( pAux = pReduce, 1, 1, 0 ); pReduce = Gia_ManSeqStructSweep( pAux = pReduce, 1, 1, 0 );
Gia_ManStop( pAux ); Gia_ManStop( pAux );
Gia_WriteAiger( pReduce, "gsrm.aig", 0, 0 ); Gia_WriteAiger( pReduce, "gsrm.aig", 0, 0 );
// printf( "Speculatively reduced model was written into file \"%s\".\n", "gsrm.aig" ); // Abc_Print( 1, "Speculatively reduced model was written into file \"%s\".\n", "gsrm.aig" );
// Gia_ManPrintStatsShort( pReduce ); // Gia_ManPrintStatsShort( pReduce );
Gia_ManStop( pReduce ); Gia_ManStop( pReduce );
} }
if ( RetValue ) if ( RetValue )
{ {
printf( "Cec_ManSeqSemiformal(): An output of the miter is asserted. Refinement stopped.\n" ); Abc_Print( 1, "Cec_ManSeqSemiformal(): An output of the miter is asserted. Refinement stopped.\n" );
break; break;
} }
// decide when to stop // decide when to stop
@ -417,7 +420,7 @@ int Cec_ManSeqSemiformal( Gia_Man_t * pAig, Cec_ParSmf_t * pPars )
{ {
int nNonConsts = Cec_ManCountNonConstOutputs( pAig ); int nNonConsts = Cec_ManCountNonConstOutputs( pAig );
if ( nNonConsts ) if ( nNonConsts )
printf( "The number of POs that are not const-0 candidates = %d.\n", nNonConsts ); Abc_Print( 1, "The number of POs that are not const-0 candidates = %d.\n", nNonConsts );
} }
return RetValue; return RetValue;
} }
@ -432,3 +435,5 @@ int Cec_ManSeqSemiformal( Gia_Man_t * pAig, Cec_ParSmf_t * pPars )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

5
src/aig/cec/cecSim.c
View File

@ -20,6 +20,9 @@
#include "cecInt.h" #include "cecInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -46,3 +49,5 @@
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

75
src/aig/cec/cecSolve.c
View File

@ -20,6 +20,9 @@
#include "cecInt.h" #include "cecInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -188,7 +191,7 @@ void Cec_AddClausesSuper( Cec_ManSat_t * p, Gia_Obj_t * pNode, Vec_Ptr_t * vSupe
pLits = ABC_ALLOC( int, nLits ); pLits = ABC_ALLOC( int, nLits );
// suppose AND-gate is A & B = C // suppose AND-gate is A & B = C
// add !A => !C or A + !C // add !A => !C or A + !C
Vec_PtrForEachEntry( vSuper, pFanin, i ) Vec_PtrForEachEntry( Gia_Obj_t *, vSuper, pFanin, i )
{ {
pLits[0] = toLitCond(Cec_ObjSatNum(p,Gia_Regular(pFanin)), Gia_IsComplement(pFanin)); pLits[0] = toLitCond(Cec_ObjSatNum(p,Gia_Regular(pFanin)), Gia_IsComplement(pFanin));
pLits[1] = toLitCond(Cec_ObjSatNum(p,pNode), 1); pLits[1] = toLitCond(Cec_ObjSatNum(p,pNode), 1);
@ -201,7 +204,7 @@ void Cec_AddClausesSuper( Cec_ManSat_t * p, Gia_Obj_t * pNode, Vec_Ptr_t * vSupe
assert( RetValue ); assert( RetValue );
} }
// add A & B => C or !A + !B + C // add A & B => C or !A + !B + C
Vec_PtrForEachEntry( vSuper, pFanin, i ) Vec_PtrForEachEntry( Gia_Obj_t *, vSuper, pFanin, i )
{ {
pLits[i] = toLitCond(Cec_ObjSatNum(p,Gia_Regular(pFanin)), !Gia_IsComplement(pFanin)); pLits[i] = toLitCond(Cec_ObjSatNum(p,Gia_Regular(pFanin)), !Gia_IsComplement(pFanin));
if ( p->pPars->fPolarFlip ) if ( p->pPars->fPolarFlip )
@ -320,7 +323,7 @@ void Cec_CnfNodeAddToSolver( Cec_ManSat_t * p, Gia_Obj_t * pObj )
vFrontier = Vec_PtrAlloc( 100 ); vFrontier = Vec_PtrAlloc( 100 );
Cec_ObjAddToFrontier( p, pObj, vFrontier ); Cec_ObjAddToFrontier( p, pObj, vFrontier );
// explore nodes in the frontier // explore nodes in the frontier
Vec_PtrForEachEntry( vFrontier, pNode, i ) Vec_PtrForEachEntry( Gia_Obj_t *, vFrontier, pNode, i )
{ {
// create the supergate // create the supergate
assert( Cec_ObjSatNum(p,pNode) ); assert( Cec_ObjSatNum(p,pNode) );
@ -331,14 +334,14 @@ void Cec_CnfNodeAddToSolver( Cec_ManSat_t * p, Gia_Obj_t * pObj )
Vec_PtrPushUnique( p->vFanins, Gia_ObjFanin0( Gia_ObjFanin1(pNode) ) ); Vec_PtrPushUnique( p->vFanins, Gia_ObjFanin0( Gia_ObjFanin1(pNode) ) );
Vec_PtrPushUnique( p->vFanins, Gia_ObjFanin1( Gia_ObjFanin0(pNode) ) ); Vec_PtrPushUnique( p->vFanins, Gia_ObjFanin1( Gia_ObjFanin0(pNode) ) );
Vec_PtrPushUnique( p->vFanins, Gia_ObjFanin1( Gia_ObjFanin1(pNode) ) ); Vec_PtrPushUnique( p->vFanins, Gia_ObjFanin1( Gia_ObjFanin1(pNode) ) );
Vec_PtrForEachEntry( p->vFanins, pFanin, k ) Vec_PtrForEachEntry( Gia_Obj_t *, p->vFanins, pFanin, k )
Cec_ObjAddToFrontier( p, Gia_Regular(pFanin), vFrontier ); Cec_ObjAddToFrontier( p, Gia_Regular(pFanin), vFrontier );
Cec_AddClausesMux( p, pNode ); Cec_AddClausesMux( p, pNode );
} }
else else
{ {
Cec_CollectSuper( pNode, fUseMuxes, p->vFanins ); Cec_CollectSuper( pNode, fUseMuxes, p->vFanins );
Vec_PtrForEachEntry( p->vFanins, pFanin, k ) Vec_PtrForEachEntry( Gia_Obj_t *, p->vFanins, pFanin, k )
Cec_ObjAddToFrontier( p, Gia_Regular(pFanin), vFrontier ); Cec_ObjAddToFrontier( p, Gia_Regular(pFanin), vFrontier );
Cec_AddClausesSuper( p, pNode, p->vFanins ); Cec_AddClausesSuper( p, pNode, p->vFanins );
} }
@ -366,7 +369,7 @@ void Cec_ManSatSolverRecycle( Cec_ManSat_t * p )
{ {
Gia_Obj_t * pObj; Gia_Obj_t * pObj;
int i; int i;
Vec_PtrForEachEntry( p->vUsedNodes, pObj, i ) Vec_PtrForEachEntry( Gia_Obj_t *, p->vUsedNodes, pObj, i )
Cec_ObjSetSatNum( p, pObj, 0 ); Cec_ObjSetSatNum( p, pObj, 0 );
Vec_PtrClear( p->vUsedNodes ); Vec_PtrClear( p->vUsedNodes );
// memset( p->pSatVars, 0, sizeof(int) * Gia_ManObjNumMax(p->pAigTotal) ); // memset( p->pSatVars, 0, sizeof(int) * Gia_ManObjNumMax(p->pAigTotal) );
@ -404,9 +407,9 @@ void Cec_SetActivityFactors_rec( Cec_ManSat_t * p, Gia_Obj_t * pObj, int LevelMi
float dActConeBumpMax = 20.0; float dActConeBumpMax = 20.0;
int iVar; int iVar;
// skip visited variables // skip visited variables
if ( Gia_ObjIsTravIdCurrentArray(p->pAig, pObj) ) if ( Gia_ObjIsTravIdCurrent(p->pAig, pObj) )
return; return;
Gia_ObjSetTravIdCurrentArray(p->pAig, pObj); Gia_ObjSetTravIdCurrent(p->pAig, pObj);
// add the PI to the list // add the PI to the list
if ( Gia_ObjLevel(p->pAig, pObj) <= LevelMin || Gia_ObjIsCi(pObj) ) if ( Gia_ObjLevel(p->pAig, pObj) <= LevelMin || Gia_ObjIsCi(pObj) )
return; return;
@ -440,7 +443,7 @@ int Cec_SetActivityFactors( Cec_ManSat_t * p, Gia_Obj_t * pObj )
// reset the active variables // reset the active variables
veci_resize(&p->pSat->act_vars, 0); veci_resize(&p->pSat->act_vars, 0);
// prepare for traversal // prepare for traversal
Gia_ManIncrementTravIdArray( p->pAig ); Gia_ManIncrementTravId( p->pAig );
// determine the min and max level to visit // determine the min and max level to visit
assert( dActConeRatio > 0 && dActConeRatio < 1 ); assert( dActConeRatio > 0 && dActConeRatio < 1 );
LevelMax = Gia_ObjLevel(p->pAig,pObj); LevelMax = Gia_ObjLevel(p->pAig,pObj);
@ -491,7 +494,7 @@ int Cec_ManSatCheckNode( Cec_ManSat_t * p, Gia_Obj_t * pObj )
clk2 = clock(); clk2 = clock();
Cec_CnfNodeAddToSolver( p, pObjR ); Cec_CnfNodeAddToSolver( p, pObjR );
//ABC_PRT( "cnf", clock() - clk2 ); //ABC_PRT( "cnf", clock() - clk2 );
//printf( "%d \n", p->pSat->size ); //Abc_Print( 1, "%d \n", p->pSat->size );
clk2 = clock(); clk2 = clock();
// Cec_SetActivityFactors( p, pObjR ); // Cec_SetActivityFactors( p, pObjR );
@ -529,7 +532,7 @@ p->timeSatUnsat += clock() - clk;
assert( RetValue ); assert( RetValue );
p->nSatUnsat++; p->nSatUnsat++;
p->nConfUnsat += p->pSat->stats.conflicts - nConflicts; p->nConfUnsat += p->pSat->stats.conflicts - nConflicts;
//printf( "UNSAT after %d conflicts\n", p->pSat->stats.conflicts - nConflicts ); //Abc_Print( 1, "UNSAT after %d conflicts\n", p->pSat->stats.conflicts - nConflicts );
return 1; return 1;
} }
else if ( RetValue == l_True ) else if ( RetValue == l_True )
@ -537,7 +540,7 @@ p->timeSatUnsat += clock() - clk;
p->timeSatSat += clock() - clk; p->timeSatSat += clock() - clk;
p->nSatSat++; p->nSatSat++;
p->nConfSat += p->pSat->stats.conflicts - nConflicts; p->nConfSat += p->pSat->stats.conflicts - nConflicts;
//printf( "SAT after %d conflicts\n", p->pSat->stats.conflicts - nConflicts ); //Abc_Print( 1, "SAT after %d conflicts\n", p->pSat->stats.conflicts - nConflicts );
return 0; return 0;
} }
else // if ( RetValue == l_Undef ) else // if ( RetValue == l_Undef )
@ -545,7 +548,7 @@ p->timeSatSat += clock() - clk;
p->timeSatUndec += clock() - clk; p->timeSatUndec += clock() - clk;
p->nSatUndec++; p->nSatUndec++;
p->nConfUndec += p->pSat->stats.conflicts - nConflicts; p->nConfUndec += p->pSat->stats.conflicts - nConflicts;
//printf( "UNDEC after %d conflicts\n", p->pSat->stats.conflicts - nConflicts ); //Abc_Print( 1, "UNDEC after %d conflicts\n", p->pSat->stats.conflicts - nConflicts );
return -1; return -1;
} }
} }
@ -591,7 +594,7 @@ clk2 = clock();
Cec_CnfNodeAddToSolver( p, pObjR1 ); Cec_CnfNodeAddToSolver( p, pObjR1 );
Cec_CnfNodeAddToSolver( p, pObjR2 ); Cec_CnfNodeAddToSolver( p, pObjR2 );
//ABC_PRT( "cnf", clock() - clk2 ); //ABC_PRT( "cnf", clock() - clk2 );
//printf( "%d \n", p->pSat->size ); //Abc_Print( 1, "%d \n", p->pSat->size );
clk2 = clock(); clk2 = clock();
// Cec_SetActivityFactors( p, pObjR1 ); // Cec_SetActivityFactors( p, pObjR1 );
@ -633,7 +636,7 @@ p->timeSatUnsat += clock() - clk;
assert( RetValue ); assert( RetValue );
p->nSatUnsat++; p->nSatUnsat++;
p->nConfUnsat += p->pSat->stats.conflicts - nConflicts; p->nConfUnsat += p->pSat->stats.conflicts - nConflicts;
//printf( "UNSAT after %d conflicts\n", p->pSat->stats.conflicts - nConflicts ); //Abc_Print( 1, "UNSAT after %d conflicts\n", p->pSat->stats.conflicts - nConflicts );
return 1; return 1;
} }
else if ( RetValue == l_True ) else if ( RetValue == l_True )
@ -641,7 +644,7 @@ p->timeSatUnsat += clock() - clk;
p->timeSatSat += clock() - clk; p->timeSatSat += clock() - clk;
p->nSatSat++; p->nSatSat++;
p->nConfSat += p->pSat->stats.conflicts - nConflicts; p->nConfSat += p->pSat->stats.conflicts - nConflicts;
//printf( "SAT after %d conflicts\n", p->pSat->stats.conflicts - nConflicts ); //Abc_Print( 1, "SAT after %d conflicts\n", p->pSat->stats.conflicts - nConflicts );
return 0; return 0;
} }
else // if ( RetValue == l_Undef ) else // if ( RetValue == l_Undef )
@ -649,7 +652,7 @@ p->timeSatSat += clock() - clk;
p->timeSatUndec += clock() - clk; p->timeSatUndec += clock() - clk;
p->nSatUndec++; p->nSatUndec++;
p->nConfUndec += p->pSat->stats.conflicts - nConflicts; p->nConfUndec += p->pSat->stats.conflicts - nConflicts;
//printf( "UNDEC after %d conflicts\n", p->pSat->stats.conflicts - nConflicts ); //Abc_Print( 1, "UNDEC after %d conflicts\n", p->pSat->stats.conflicts - nConflicts );
return -1; return -1;
} }
} }
@ -683,7 +686,7 @@ void Cec_ManSatSolve( Cec_ManPat_t * pPat, Gia_Man_t * pAig, Cec_ParSat_t * pPar
} }
Gia_ManSetPhase( pAig ); Gia_ManSetPhase( pAig );
Gia_ManLevelNum( pAig ); Gia_ManLevelNum( pAig );
Gia_ManResetTravIdArray( pAig ); Gia_ManIncrementTravId( pAig );
p = Cec_ManSatCreate( pAig, pPars ); p = Cec_ManSatCreate( pAig, pPars );
pProgress = Bar_ProgressStart( stdout, Gia_ManPoNum(pAig) ); pProgress = Bar_ProgressStart( stdout, Gia_ManPoNum(pAig) );
Gia_ManForEachCo( pAig, pObj, i ) Gia_ManForEachCo( pAig, pObj, i )
@ -705,7 +708,7 @@ clk2 = clock();
Gia_Man_t * pTemp = Gia_ManDupDfsCone( pAig, pObj ); Gia_Man_t * pTemp = Gia_ManDupDfsCone( pAig, pObj );
Gia_WriteAiger( pTemp, "gia_hard.aig", 0, 0 ); Gia_WriteAiger( pTemp, "gia_hard.aig", 0, 0 );
Gia_ManStop( pTemp ); Gia_ManStop( pTemp );
printf( "Dumping hard cone into file \"%s\".\n", "gia_hard.aig" ); Abc_Print( 1, "Dumping hard cone into file \"%s\".\n", "gia_hard.aig" );
} }
*/ */
if ( status != 0 ) if ( status != 0 )
@ -759,12 +762,12 @@ Vec_Int_t * Cec_ManSatReadCex( Cec_ManSat_t * pSat )
***********************************************************************/ ***********************************************************************/
void Cec_ManSatSolveSeq_rec( Cec_ManSat_t * pSat, Gia_Man_t * p, Gia_Obj_t * pObj, Vec_Ptr_t * vInfo, int iPat, int nRegs ) void Cec_ManSatSolveSeq_rec( Cec_ManSat_t * pSat, Gia_Man_t * p, Gia_Obj_t * pObj, Vec_Ptr_t * vInfo, int iPat, int nRegs )
{ {
if ( Gia_ObjIsTravIdCurrentArray(p, pObj) ) if ( Gia_ObjIsTravIdCurrent(p, pObj) )
return; return;
Gia_ObjSetTravIdCurrentArray(p, pObj); Gia_ObjSetTravIdCurrent(p, pObj);
if ( Gia_ObjIsCi(pObj) ) if ( Gia_ObjIsCi(pObj) )
{ {
unsigned * pInfo = Vec_PtrEntry( vInfo, nRegs + Gia_ObjCioId(pObj) ); unsigned * pInfo = (unsigned *)Vec_PtrEntry( vInfo, nRegs + Gia_ObjCioId(pObj) );
if ( Cec_ObjSatVarValue( pSat, pObj ) != Gia_InfoHasBit( pInfo, iPat ) ) if ( Cec_ObjSatVarValue( pSat, pObj ) != Gia_InfoHasBit( pInfo, iPat ) )
Gia_InfoXorBit( pInfo, iPat ); Gia_InfoXorBit( pInfo, iPat );
pSat->nCexLits++; pSat->nCexLits++;
@ -799,7 +802,7 @@ Vec_Str_t * Cec_ManSatSolveSeq( Vec_Ptr_t * vPatts, Gia_Man_t * pAig, Cec_ParSat
nPatsInit = nPats = 32 * Vec_PtrReadWordsSimInfo(vPatts); nPatsInit = nPats = 32 * Vec_PtrReadWordsSimInfo(vPatts);
Gia_ManSetPhase( pAig ); Gia_ManSetPhase( pAig );
Gia_ManLevelNum( pAig ); Gia_ManLevelNum( pAig );
Gia_ManResetTravIdArray( pAig ); Gia_ManIncrementTravId( pAig );
p = Cec_ManSatCreate( pAig, pPars ); p = Cec_ManSatCreate( pAig, pPars );
vStatus = Vec_StrAlloc( Gia_ManPoNum(pAig) ); vStatus = Vec_StrAlloc( Gia_ManPoNum(pAig) );
pProgress = Bar_ProgressStart( stdout, Gia_ManPoNum(pAig) ); pProgress = Bar_ProgressStart( stdout, Gia_ManPoNum(pAig) );
@ -810,18 +813,18 @@ Vec_Str_t * Cec_ManSatSolveSeq( Vec_Ptr_t * vPatts, Gia_Man_t * pAig, Cec_ParSat
{ {
if ( Gia_ObjFaninC0(pObj) ) if ( Gia_ObjFaninC0(pObj) )
{ {
// printf( "Constant 1 output of SRM!!!\n" ); // Abc_Print( 1, "Constant 1 output of SRM!!!\n" );
Vec_StrPush( vStatus, 0 ); Vec_StrPush( vStatus, 0 );
} }
else else
{ {
// printf( "Constant 0 output of SRM!!!\n" ); // Abc_Print( 1, "Constant 0 output of SRM!!!\n" );
Vec_StrPush( vStatus, 1 ); Vec_StrPush( vStatus, 1 );
} }
continue; continue;
} }
status = Cec_ManSatCheckNode( p, Gia_ObjChild0(pObj) ); status = Cec_ManSatCheckNode( p, Gia_ObjChild0(pObj) );
//printf( "output %d status = %d\n", i, status ); //Abc_Print( 1, "output %d status = %d\n", i, status );
Vec_StrPush( vStatus, (char)status ); Vec_StrPush( vStatus, (char)status );
if ( status != 0 ) if ( status != 0 )
continue; continue;
@ -836,7 +839,7 @@ Vec_Str_t * Cec_ManSatSolveSeq( Vec_Ptr_t * vPatts, Gia_Man_t * pAig, Cec_ParSat
if ( iPat % nPatsInit == 0 ) if ( iPat % nPatsInit == 0 )
iPat++; iPat++;
// save the pattern // save the pattern
Gia_ManIncrementTravIdArray( pAig ); Gia_ManIncrementTravId( pAig );
// Vec_IntClear( p->vCex ); // Vec_IntClear( p->vCex );
Cec_ManSatSolveSeq_rec( p, pAig, Gia_ObjFanin0(pObj), vPatts, iPat++, nRegs ); Cec_ManSatSolveSeq_rec( p, pAig, Gia_ObjFanin0(pObj), vPatts, iPat++, nRegs );
// Gia_SatVerifyPattern( pAig, pObj, p->vCex, p->vVisits ); // Gia_SatVerifyPattern( pAig, pObj, p->vCex, p->vVisits );
@ -853,7 +856,7 @@ Vec_Str_t * Cec_ManSatSolveSeq( Vec_Ptr_t * vPatts, Gia_Man_t * pAig, Cec_ParSat
Bar_ProgressStop( pProgress ); Bar_ProgressStop( pProgress );
if ( pPars->fVerbose ) if ( pPars->fVerbose )
Cec_ManSatPrintStats( p ); Cec_ManSatPrintStats( p );
// printf( "Total number of cex literals = %d. (Ave = %d)\n", p->nCexLits, p->nCexLits/p->nSatSat ); // Abc_Print( 1, "Total number of cex literals = %d. (Ave = %d)\n", p->nCexLits, p->nCexLits/p->nSatSat );
Cec_ManSatStop( p ); Cec_ManSatStop( p );
if ( pnPats ) if ( pnPats )
*pnPats = iPat-1; *pnPats = iPat-1;
@ -900,9 +903,9 @@ void Cec_ManSatAddToStore( Vec_Int_t * vCexStore, Vec_Int_t * vCex, int Out )
***********************************************************************/ ***********************************************************************/
void Cec_ManSatSolveMiter_rec( Cec_ManSat_t * pSat, Gia_Man_t * p, Gia_Obj_t * pObj ) void Cec_ManSatSolveMiter_rec( Cec_ManSat_t * pSat, Gia_Man_t * p, Gia_Obj_t * pObj )
{ {
if ( Gia_ObjIsTravIdCurrentArray(p, pObj) ) if ( Gia_ObjIsTravIdCurrent(p, pObj) )
return; return;
Gia_ObjSetTravIdCurrentArray(p, pObj); Gia_ObjSetTravIdCurrent(p, pObj);
if ( Gia_ObjIsCi(pObj) ) if ( Gia_ObjIsCi(pObj) )
{ {
pSat->nCexLits++; pSat->nCexLits++;
@ -928,7 +931,7 @@ void Cec_ManSatSolveMiter_rec( Cec_ManSat_t * pSat, Gia_Man_t * p, Gia_Obj_t * p
void Cec_ManSavePattern( Cec_ManSat_t * p, Gia_Obj_t * pObj1, Gia_Obj_t * pObj2 ) void Cec_ManSavePattern( Cec_ManSat_t * p, Gia_Obj_t * pObj1, Gia_Obj_t * pObj2 )
{ {
Vec_IntClear( p->vCex ); Vec_IntClear( p->vCex );
Gia_ManIncrementTravIdArray( p->pAig ); Gia_ManIncrementTravId( p->pAig );
Cec_ManSatSolveMiter_rec( p, p->pAig, Gia_Regular(pObj1) ); Cec_ManSatSolveMiter_rec( p, p->pAig, Gia_Regular(pObj1) );
if ( pObj2 ) if ( pObj2 )
Cec_ManSatSolveMiter_rec( p, p->pAig, Gia_Regular(pObj2) ); Cec_ManSatSolveMiter_rec( p, p->pAig, Gia_Regular(pObj2) );
@ -957,7 +960,7 @@ Vec_Int_t * Cec_ManSatSolveMiter( Gia_Man_t * pAig, Cec_ParSat_t * pPars, Vec_St
// prepare AIG // prepare AIG
Gia_ManSetPhase( pAig ); Gia_ManSetPhase( pAig );
Gia_ManLevelNum( pAig ); Gia_ManLevelNum( pAig );
Gia_ManResetTravIdArray( pAig ); Gia_ManIncrementTravId( pAig );
// create resulting data-structures // create resulting data-structures
vStatus = Vec_StrAlloc( Gia_ManPoNum(pAig) ); vStatus = Vec_StrAlloc( Gia_ManPoNum(pAig) );
vCexStore = Vec_IntAlloc( 10000 ); vCexStore = Vec_IntAlloc( 10000 );
@ -972,13 +975,13 @@ Vec_Int_t * Cec_ManSatSolveMiter( Gia_Man_t * pAig, Cec_ParSat_t * pPars, Vec_St
{ {
if ( Gia_ObjFaninC0(pObj) ) if ( Gia_ObjFaninC0(pObj) )
{ {
// printf( "Constant 1 output of SRM!!!\n" ); // Abc_Print( 1, "Constant 1 output of SRM!!!\n" );
Cec_ManSatAddToStore( vCexStore, p->vCex, i ); // trivial counter-example Cec_ManSatAddToStore( vCexStore, p->vCex, i ); // trivial counter-example
Vec_StrPush( vStatus, 0 ); Vec_StrPush( vStatus, 0 );
} }
else else
{ {
// printf( "Constant 0 output of SRM!!!\n" ); // Abc_Print( 1, "Constant 0 output of SRM!!!\n" );
Vec_StrPush( vStatus, 1 ); Vec_StrPush( vStatus, 1 );
} }
continue; continue;
@ -994,7 +997,7 @@ Vec_Int_t * Cec_ManSatSolveMiter( Gia_Man_t * pAig, Cec_ParSat_t * pPars, Vec_St
continue; continue;
assert( status == 0 ); assert( status == 0 );
// save the pattern // save the pattern
// Gia_ManIncrementTravIdArray( pAig ); // Gia_ManIncrementTravId( pAig );
// Cec_ManSatSolveMiter_rec( p, pAig, Gia_ObjFanin0(pObj) ); // Cec_ManSatSolveMiter_rec( p, pAig, Gia_ObjFanin0(pObj) );
Cec_ManSavePattern( p, Gia_ObjFanin0(pObj), NULL ); Cec_ManSavePattern( p, Gia_ObjFanin0(pObj), NULL );
// Gia_SatVerifyPattern( pAig, pObj, p->vCex, p->vVisits ); // Gia_SatVerifyPattern( pAig, pObj, p->vCex, p->vVisits );
@ -1015,3 +1018,5 @@ Vec_Int_t * Cec_ManSatSolveMiter( Gia_Man_t * pAig, Cec_ParSat_t * pPars, Vec_St
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

11
src/aig/cec/cecSweep.c
View File

@ -20,6 +20,9 @@
#include "cecInt.h" #include "cecInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -162,8 +165,8 @@ void Cec_ManFraCreateInfo( Cec_ManSim_t * p, Vec_Ptr_t * vCiInfo, Vec_Ptr_t * vI
int i, w; int i, w;
for ( i = 0; i < Gia_ManCiNum(p->pAig); i++ ) for ( i = 0; i < Gia_ManCiNum(p->pAig); i++ )
{ {
pRes0 = Vec_PtrEntry( vCiInfo, i ); pRes0 = (unsigned *)Vec_PtrEntry( vCiInfo, i );
pRes1 = Vec_PtrEntry( vInfo, i ); pRes1 = (unsigned *)Vec_PtrEntry( vInfo, i );
pRes1 += p->nWords * nSeries; pRes1 += p->nWords * nSeries;
for ( w = 0; w < p->nWords; w++ ) for ( w = 0; w < p->nWords; w++ )
pRes0[w] = pRes1[w]; pRes0[w] = pRes1[w];
@ -270,7 +273,7 @@ p->timeSim += clock() - clk;
// if ( pObjOld->fMark0 == 0 ) // if ( pObjOld->fMark0 == 0 )
{ {
if ( iRepr == Gia_ObjRepr(p->pAig, iNode) ) if ( iRepr == Gia_ObjRepr(p->pAig, iNode) )
printf( "Cec_ManFraClassesUpdate(): Error! Node is not refined!\n" ); Abc_Print( 1, "Cec_ManFraClassesUpdate(): Error! Node is not refined!\n" );
p->nAllDisproved++; p->nAllDisproved++;
} }
} }
@ -292,3 +295,5 @@ p->timeSim += clock() - clk;
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

380
src/aig/cec/cecSynth.c Normal file
View File

@ -0,0 +1,380 @@
/**CFile****************************************************************
FileName [cecSynth.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Combinational equivalence checking.]
Synopsis [Partitioned sequential synthesis.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: cecSynth.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "cecInt.h"
#include "giaAig.h"
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Populate sequential synthesis parameters.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Cec_SeqSynthesisSetDefaultParams( Cec_ParSeq_t * p )
{
memset( p, 0, sizeof(Cec_ParSeq_t) );
p->fUseLcorr = 0; // enables latch correspondence
p->fUseScorr = 0; // enables signal correspondence
p->nBTLimit = 1000; // (scorr/lcorr) conflict limit at a node
p->nFrames = 1; // (scorr only) the number of timeframes
p->nLevelMax = -1; // (scorr only) the max number of levels
p->fConsts = 1; // (scl only) merging constants
p->fEquivs = 1; // (scl only) merging equivalences
p->fUseMiniSat = 0; // enables MiniSat in lcorr/scorr
p->nMinDomSize = 100; // the size of minimum clock domain
p->fVeryVerbose = 0; // verbose stats
p->fVerbose = 0; // verbose stats
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Cec_SeqReadMinDomSize( Cec_ParSeq_t * p )
{
return p->nMinDomSize;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Cec_SeqReadVerbose( Cec_ParSeq_t * p )
{
return p->fVerbose;
}
/**Function*************************************************************
Synopsis [Computes partitioning of registers.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Gia_ManRegCreatePart( Gia_Man_t * p, Vec_Int_t * vPart, int * pnCountPis, int * pnCountRegs, int ** ppMapBack )
{
Gia_Man_t * pNew;
Gia_Obj_t * pObj;
Vec_Int_t * vNodes, * vRoots;
int i, iOut, nCountPis, nCountRegs;
int * pMapBack;
// collect/mark nodes/PIs in the DFS order from the roots
Gia_ManIncrementTravId( p );
vRoots = Vec_IntAlloc( Vec_IntSize(vPart) );
Vec_IntForEachEntry( vPart, iOut, i )
Vec_IntPush( vRoots, Gia_ObjId(p, Gia_ManCo(p, Gia_ManPoNum(p)+iOut)) );
vNodes = Gia_ManCollectNodesCis( p, Vec_IntArray(vRoots), Vec_IntSize(vRoots) );
Vec_IntFree( vRoots );
// unmark register outputs
Vec_IntForEachEntry( vPart, iOut, i )
Gia_ObjSetTravIdPrevious( p, Gia_ManCi(p, Gia_ManPiNum(p)+iOut) );
// count pure PIs
nCountPis = nCountRegs = 0;
Gia_ManForEachPi( p, pObj, i )
nCountPis += Gia_ObjIsTravIdCurrent(p, pObj);
// count outputs of other registers
Gia_ManForEachRo( p, pObj, i )
nCountRegs += Gia_ObjIsTravIdCurrent(p, pObj); // should be !Gia_... ???
if ( pnCountPis )
*pnCountPis = nCountPis;
if ( pnCountRegs )
*pnCountRegs = nCountRegs;
// clean old manager
Gia_ManFillValue(p);
Gia_ManConst0(p)->Value = 0;
// create the new manager
pNew = Gia_ManStart( Vec_IntSize(vNodes) );
// create the PIs
Gia_ManForEachCi( p, pObj, i )
if ( Gia_ObjIsTravIdCurrent(p, pObj) )
pObj->Value = Gia_ManAppendCi(pNew);
// add variables for the register outputs
// create fake POs to hold the register outputs
Vec_IntForEachEntry( vPart, iOut, i )
{
pObj = Gia_ManCi(p, Gia_ManPiNum(p)+iOut);
pObj->Value = Gia_ManAppendCi(pNew);
Gia_ManAppendCo( pNew, pObj->Value );
Gia_ObjSetTravIdCurrent( p, pObj ); // added
}
// create the nodes
Gia_ManForEachObjVec( vNodes, p, pObj, i )
if ( Gia_ObjIsAnd(pObj) )
pObj->Value = Gia_ManAppendAnd( pNew, Gia_ObjFanin0Copy(pObj), Gia_ObjFanin1Copy(pObj) );
// add real POs for the registers
Vec_IntForEachEntry( vPart, iOut, i )
{
pObj = Gia_ManCo( p, Gia_ManPoNum(p)+iOut );
Gia_ManAppendCo( pNew, Gia_ObjFanin0Copy(pObj) );
}
Gia_ManSetRegNum( pNew, Vec_IntSize(vPart) );
// create map
if ( ppMapBack )
{
pMapBack = ABC_FALLOC( int, Gia_ManObjNum(pNew) );
// map constant nodes
pMapBack[0] = 0;
// logic cones of register outputs
Gia_ManForEachObjVec( vNodes, p, pObj, i )
{
// pObjNew = Aig_Regular(pObj->pData);
// pMapBack[pObjNew->Id] = pObj->Id;
assert( Gia_Lit2Var(Gia_ObjValue(pObj)) >= 0 );
assert( Gia_Lit2Var(Gia_ObjValue(pObj)) < Gia_ManObjNum(pNew) );
pMapBack[ Gia_Lit2Var(Gia_ObjValue(pObj)) ] = Gia_ObjId(p, pObj);
}
// map register outputs
Vec_IntForEachEntry( vPart, iOut, i )
{
pObj = Gia_ManCi(p, Gia_ManPiNum(p)+iOut);
// pObjNew = pObj->pData;
// pMapBack[pObjNew->Id] = pObj->Id;
assert( Gia_Lit2Var(Gia_ObjValue(pObj)) >= 0 );
assert( Gia_Lit2Var(Gia_ObjValue(pObj)) < Gia_ManObjNum(pNew) );
pMapBack[ Gia_Lit2Var(Gia_ObjValue(pObj)) ] = Gia_ObjId(p, pObj);
}
*ppMapBack = pMapBack;
}
Vec_IntFree( vNodes );
return pNew;
}
/**Function*************************************************************
Synopsis [Transfers the classes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_TransferMappedClasses( Gia_Man_t * pPart, int * pMapBack, int * pReprs )
{
Gia_Obj_t * pObj;
int i, Id1, Id2, nClasses;
if ( pPart->pReprs == NULL )
return 0;
nClasses = 0;
Gia_ManForEachObj( pPart, pObj, i )
{
if ( Gia_ObjRepr(pPart, i) == GIA_VOID )
continue;
assert( i < Gia_ManObjNum(pPart) );
assert( Gia_ObjRepr(pPart, i) < Gia_ManObjNum(pPart) );
Id1 = pMapBack[ i ];
Id2 = pMapBack[ Gia_ObjRepr(pPart, i) ];
if ( Id1 == Id2 )
continue;
if ( Id1 < Id2 )
pReprs[Id2] = Id1;
else
pReprs[Id1] = Id2;
nClasses++;
}
return nClasses;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_ManFindRepr_rec( int * pReprs, int Id )
{
if ( pReprs[Id] == 0 )
return 0;
if ( pReprs[Id] == ~0 )
return Id;
return Gia_ManFindRepr_rec( pReprs, pReprs[Id] );
}
/**Function*************************************************************
Synopsis [Normalizes equivalences.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ManNormalizeEquivalences( Gia_Man_t * p, int * pReprs )
{
int i, iRepr;
assert( p->pReprs == NULL );
assert( p->pNexts == NULL );
p->pReprs = ABC_CALLOC( Gia_Rpr_t, Gia_ManObjNum(p) );
for ( i = 0; i < Gia_ManObjNum(p); i++ )
Gia_ObjSetRepr( p, i, GIA_VOID );
for ( i = 0; i < Gia_ManObjNum(p); i++ )
{
if ( pReprs[i] == ~0 )
continue;
iRepr = Gia_ManFindRepr_rec( pReprs, i );
Gia_ObjSetRepr( p, i, iRepr );
}
p->pNexts = Gia_ManDeriveNexts( p );
}
/**Function*************************************************************
Synopsis [Partitioned sequential synthesis.]
Description [Returns AIG annotated with equivalence classes.]
SideEffects []
SeeAlso []
***********************************************************************/
int Cec_SequentialSynthesisPart( Gia_Man_t * p, Cec_ParSeq_t * pPars )
{
int fPrintParts = 0;
char Buffer[100];
Gia_Man_t * pTemp;
Vec_Ptr_t * vParts = (Vec_Ptr_t *)p->vClockDoms;
Vec_Int_t * vPart;
int * pMapBack, * pReprs;
int i, nCountPis, nCountRegs;
int nClasses, clk = clock();
// save parameters
if ( fPrintParts )
{
// print partitions
Abc_Print( 1, "The following clock domains are used:\n" );
Vec_PtrForEachEntry( Vec_Int_t *, vParts, vPart, i )
{
pTemp = Gia_ManRegCreatePart( p, vPart, &nCountPis, &nCountRegs, NULL );
sprintf( Buffer, "part%03d.aig", i );
Gia_WriteAiger( pTemp, Buffer, 0, 0 );
Abc_Print( 1, "part%03d.aig : Reg = %4d. PI = %4d. (True = %4d. Regs = %4d.) And = %5d.\n",
i, Vec_IntSize(vPart), Gia_ManCiNum(pTemp)-Vec_IntSize(vPart), nCountPis, nCountRegs, Gia_ManAndNum(pTemp) );
Gia_ManStop( pTemp );
}
}
// perform sequential synthesis for clock domains
pReprs = ABC_FALLOC( int, Gia_ManObjNum(p) );
Vec_PtrForEachEntry( Vec_Int_t *, vParts, vPart, i )
{
pTemp = Gia_ManRegCreatePart( p, vPart, &nCountPis, &nCountRegs, &pMapBack );
if ( nCountPis > 0 )
{
if ( pPars->fUseScorr )
{
Cec_ParCor_t CorPars, * pCorPars = &CorPars;
Cec_ManCorSetDefaultParams( pCorPars );
pCorPars->nBTLimit = pPars->nBTLimit;
pCorPars->nLevelMax = pPars->nLevelMax;
pCorPars->fVerbose = pPars->fVeryVerbose;
pCorPars->fUseCSat = 1;
Cec_ManLSCorrespondenceClasses( pTemp, pCorPars );
}
else if ( pPars->fUseLcorr )
{
Cec_ParCor_t CorPars, * pCorPars = &CorPars;
Cec_ManCorSetDefaultParams( pCorPars );
pCorPars->fLatchCorr = 1;
pCorPars->nBTLimit = pPars->nBTLimit;
pCorPars->fVerbose = pPars->fVeryVerbose;
pCorPars->fUseCSat = 1;
Cec_ManLSCorrespondenceClasses( pTemp, pCorPars );
}
else
{
// pNew = Gia_ManSeqStructSweep( pTemp, pPars->fConsts, pPars->fEquivs, pPars->fVerbose );
// Gia_ManStop( pNew );
Gia_ManSeqCleanupClasses( pTemp, pPars->fConsts, pPars->fEquivs, pPars->fVerbose );
}
//Abc_Print( 1, "Part equivalences = %d.\n", Gia_ManEquivCountLitsAll(pTemp) );
nClasses = Gia_TransferMappedClasses( pTemp, pMapBack, pReprs );
if ( pPars->fVerbose )
{
Abc_Print( 1, "%3d : Reg = %4d. PI = %4d. (True = %4d. Regs = %4d.) And = %5d. Cl = %5d.\n",
i, Vec_IntSize(vPart), Gia_ManCiNum(pTemp)-Vec_IntSize(vPart), nCountPis, nCountRegs, Gia_ManAndNum(pTemp), nClasses );
}
}
Gia_ManStop( pTemp );
ABC_FREE( pMapBack );
}
// generate resulting equivalences
Gia_ManNormalizeEquivalences( p, pReprs );
//Abc_Print( 1, "Total equivalences = %d.\n", Gia_ManEquivCountLitsAll(p) );
ABC_FREE( pReprs );
if ( pPars->fVerbose )
{
Abc_PrintTime( 1, "Total time", clock() - clk );
}
return 1;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

1
src/aig/cec/module.make
View File

@ -9,4 +9,5 @@ SRC += src/aig/cec/cecCec.c \
src/aig/cec/cecSeq.c \ src/aig/cec/cecSeq.c \
src/aig/cec/cecSim.c \ src/aig/cec/cecSim.c \
src/aig/cec/cecSolve.c \ src/aig/cec/cecSolve.c \
src/aig/cec/cecSynth.c \
src/aig/cec/cecSweep.c src/aig/cec/cecSweep.c

16
src/aig/cgt/cgt.h
View File

@ -21,6 +21,7 @@
#ifndef __CGT_H__ #ifndef __CGT_H__
#define __CGT_H__ #define __CGT_H__
/* /*
The algorithm implemented in this package is based on the paper: The algorithm implemented in this package is based on the paper:
A. Hurst. "Automatic synthesis of clock gating logic with controlled A. Hurst. "Automatic synthesis of clock gating logic with controlled
@ -35,9 +36,10 @@
/// PARAMETERS /// /// PARAMETERS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
extern "C" {
#endif ABC_NAMESPACE_HEADER_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// BASIC TYPES /// /// BASIC TYPES ///
@ -70,9 +72,11 @@ extern void Cgt_SetDefaultParams( Cgt_Par_t * p );
extern Vec_Vec_t * Cgt_ClockGatingCandidates( Aig_Man_t * pAig, Aig_Man_t * pCare, Cgt_Par_t * pPars ); extern Vec_Vec_t * Cgt_ClockGatingCandidates( Aig_Man_t * pAig, Aig_Man_t * pCare, Cgt_Par_t * pPars );
extern Aig_Man_t * Cgt_ClockGating( Aig_Man_t * pAig, Aig_Man_t * pCare, Cgt_Par_t * pPars ); extern Aig_Man_t * Cgt_ClockGating( Aig_Man_t * pAig, Aig_Man_t * pCare, Cgt_Par_t * pPars );
#ifdef __cplusplus
}
#endif ABC_NAMESPACE_HEADER_END
#endif #endif

63
src/aig/cgt/cgtAig.c
View File

@ -20,6 +20,9 @@
#include "cgtInt.h" #include "cgtInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -119,7 +122,7 @@ void Cgt_ManDetectFanout( Aig_Man_t * pAig, Aig_Obj_t * pObj, int nOdcMax, Vec_P
Cgt_ManDetectFanout_rec( pAig, pObj, nOdcMax, vFanout ); Cgt_ManDetectFanout_rec( pAig, pObj, nOdcMax, vFanout );
// remove those nodes whose fanout is included // remove those nodes whose fanout is included
k = 0; k = 0;
Vec_PtrForEachEntry( vFanout, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vFanout, pObj, i )
{ {
// go through the fanouts of this node // go through the fanouts of this node
Aig_ObjForEachFanout( pAig, pObj, pFanout, iFanout, f ) Aig_ObjForEachFanout( pAig, pObj, pFanout, iFanout, f )
@ -130,7 +133,7 @@ void Cgt_ManDetectFanout( Aig_Man_t * pAig, Aig_Obj_t * pObj, int nOdcMax, Vec_P
Vec_PtrWriteEntry( vFanout, k++, pObj ); Vec_PtrWriteEntry( vFanout, k++, pObj );
} }
Vec_PtrShrink( vFanout, k ); Vec_PtrShrink( vFanout, k );
Vec_PtrSort( vFanout, Aig_ObjCompareIdIncrease ); Vec_PtrSort( vFanout, (int (*)(void))Aig_ObjCompareIdIncrease );
assert( Vec_PtrSize(vFanout) > 0 ); assert( Vec_PtrSize(vFanout) > 0 );
} }
@ -175,7 +178,7 @@ void Cgt_ManCollectVisited( Aig_Man_t * pAig, Vec_Ptr_t * vFanout, Vec_Ptr_t * v
int i; int i;
Vec_PtrClear( vVisited ); Vec_PtrClear( vVisited );
Aig_ManIncrementTravId( pAig ); Aig_ManIncrementTravId( pAig );
Vec_PtrForEachEntry( vFanout, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vFanout, pObj, i )
Cgt_ManCollectVisited_rec( pAig, pObj, vVisited ); Cgt_ManCollectVisited_rec( pAig, pObj, vVisited );
} }
@ -215,7 +218,7 @@ Aig_Obj_t * Cgt_ManConstructCareCondition( Cgt_Man_t * p, Aig_Man_t * pNew, Aig_
Cgt_ManDetectFanout( p->pAig, pObjLo, p->pPars->nOdcMax, p->vFanout ); Cgt_ManDetectFanout( p->pAig, pObjLo, p->pPars->nOdcMax, p->vFanout );
Cgt_ManCollectVisited( p->pAig, p->vFanout, p->vVisited ); Cgt_ManCollectVisited( p->pAig, p->vFanout, p->vVisited );
// add new variables if the observability condition depends on PI variables // add new variables if the observability condition depends on PI variables
Vec_PtrForEachEntry( p->vVisited, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, p->vVisited, pObj, i )
{ {
assert( Aig_ObjIsNode(pObj) ); assert( Aig_ObjIsNode(pObj) );
if ( Saig_ObjIsPi(p->pAig, Aig_ObjFanin0(pObj)) && Vec_PtrEntry(vCopy0, Aig_ObjFaninId0(pObj)) == NULL ) if ( Saig_ObjIsPi(p->pAig, Aig_ObjFanin0(pObj)) && Vec_PtrEntry(vCopy0, Aig_ObjFaninId0(pObj)) == NULL )
@ -232,7 +235,7 @@ Aig_Obj_t * Cgt_ManConstructCareCondition( Cgt_Man_t * p, Aig_Man_t * pNew, Aig_
} }
} }
// construct AIGs for the nodes // construct AIGs for the nodes
Vec_PtrForEachEntry( p->vVisited, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, p->vVisited, pObj, i )
{ {
pTemp = Aig_And( pNew, Aig_ObjChild0CopyVec(vCopy0, pObj), Aig_ObjChild1CopyVec(vCopy0, pObj) ); pTemp = Aig_And( pNew, Aig_ObjChild0CopyVec(vCopy0, pObj), Aig_ObjChild1CopyVec(vCopy0, pObj) );
Vec_PtrWriteEntry( vCopy0, Aig_ObjId(pObj), pTemp ); Vec_PtrWriteEntry( vCopy0, Aig_ObjId(pObj), pTemp );
@ -241,9 +244,9 @@ Aig_Obj_t * Cgt_ManConstructCareCondition( Cgt_Man_t * p, Aig_Man_t * pNew, Aig_
} }
// construct the care miter // construct the care miter
pMiter = Aig_ManConst0( pNew ); pMiter = Aig_ManConst0( pNew );
Vec_PtrForEachEntry( p->vFanout, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, p->vFanout, pObj, i )
{ {
pTemp = Aig_Exor( pNew, Vec_PtrEntry(vCopy0, Aig_ObjId(pObj)), Vec_PtrEntry(vCopy1, Aig_ObjId(pObj)) ); pTemp = Aig_Exor( pNew, (Aig_Obj_t *)Vec_PtrEntry(vCopy0, Aig_ObjId(pObj)), (Aig_Obj_t *)Vec_PtrEntry(vCopy1, Aig_ObjId(pObj)) );
pMiter = Aig_Or( pNew, pMiter, pTemp ); pMiter = Aig_Or( pNew, pMiter, pTemp );
} }
return pMiter; return pMiter;
@ -300,7 +303,7 @@ Aig_Man_t * Cgt_ManDeriveAigForGating( Cgt_Man_t * p )
Vec_PtrWriteEntry( vCopy0, Aig_ObjId(pObjLo), Aig_ObjChild0Copy(pObjLi) ); Vec_PtrWriteEntry( vCopy0, Aig_ObjId(pObjLo), Aig_ObjChild0Copy(pObjLi) );
Vec_PtrWriteEntry( vCopy1, Aig_ObjId(pObjLo), Aig_ObjChild0Copy(pObjLi) ); Vec_PtrWriteEntry( vCopy1, Aig_ObjId(pObjLo), Aig_ObjChild0Copy(pObjLi) );
// compute the miter // compute the miter
pMiter = Aig_Exor( pNew, pObjLo->pData, Aig_ObjChild0Copy(pObjLi) ); pMiter = Aig_Exor( pNew, (Aig_Obj_t *)pObjLo->pData, Aig_ObjChild0Copy(pObjLi) );
pMiter = Aig_And( pNew, pMiter, pCare ); pMiter = Aig_And( pNew, pMiter, pCare );
pObjLi->pData = Aig_ObjCreatePo( pNew, pMiter ); pObjLi->pData = Aig_ObjCreatePo( pNew, pMiter );
} }
@ -312,7 +315,7 @@ Aig_Man_t * Cgt_ManDeriveAigForGating( Cgt_Man_t * p )
// construct clock-gating miters for each register input // construct clock-gating miters for each register input
Saig_ManForEachLiLo( p->pAig, pObjLi, pObjLo, i ) Saig_ManForEachLiLo( p->pAig, pObjLi, pObjLo, i )
{ {
pMiter = Aig_Exor( pNew, pObjLo->pData, Aig_ObjChild0Copy(pObjLi) ); pMiter = Aig_Exor( pNew, (Aig_Obj_t *)pObjLo->pData, Aig_ObjChild0Copy(pObjLi) );
pObjLi->pData = Aig_ObjCreatePo( pNew, pMiter ); pObjLi->pData = Aig_ObjCreatePo( pNew, pMiter );
} }
} }
@ -336,19 +339,19 @@ Aig_Obj_t * Cgt_ManConstructCare_rec( Aig_Man_t * pCare, Aig_Obj_t * pObj, Aig_M
{ {
Aig_Obj_t * pObj0, * pObj1; Aig_Obj_t * pObj0, * pObj1;
if ( Aig_ObjIsTravIdCurrent( pCare, pObj ) ) if ( Aig_ObjIsTravIdCurrent( pCare, pObj ) )
return pObj->pData; return (Aig_Obj_t *)pObj->pData;
Aig_ObjSetTravIdCurrent( pCare, pObj ); Aig_ObjSetTravIdCurrent( pCare, pObj );
if ( Aig_ObjIsPi(pObj) ) if ( Aig_ObjIsPi(pObj) )
return pObj->pData = NULL; return (Aig_Obj_t *)(pObj->pData = NULL);
pObj0 = Cgt_ManConstructCare_rec( pCare, Aig_ObjFanin0(pObj), pNew ); pObj0 = Cgt_ManConstructCare_rec( pCare, Aig_ObjFanin0(pObj), pNew );
if ( pObj0 == NULL ) if ( pObj0 == NULL )
return pObj->pData = NULL; return (Aig_Obj_t *)(pObj->pData = NULL);
pObj1 = Cgt_ManConstructCare_rec( pCare, Aig_ObjFanin1(pObj), pNew ); pObj1 = Cgt_ManConstructCare_rec( pCare, Aig_ObjFanin1(pObj), pNew );
if ( pObj1 == NULL ) if ( pObj1 == NULL )
return pObj->pData = NULL; return (Aig_Obj_t *)(pObj->pData = NULL);
pObj0 = Aig_NotCond( pObj0, Aig_ObjFaninC0(pObj) ); pObj0 = Aig_NotCond( pObj0, Aig_ObjFaninC0(pObj) );
pObj1 = Aig_NotCond( pObj1, Aig_ObjFaninC1(pObj) ); pObj1 = Aig_NotCond( pObj1, Aig_ObjFaninC1(pObj) );
return pObj->pData = Aig_And( pNew, pObj0, pObj1 ); return (Aig_Obj_t *)(pObj->pData = Aig_And( pNew, pObj0, pObj1 ));
} }
/**Function************************************************************* /**Function*************************************************************
@ -370,16 +373,16 @@ void Cgt_ManConstructCare( Aig_Man_t * pNew, Aig_Man_t * pCare, Vec_Vec_t * vSup
// go through the PIs of the partition // go through the PIs of the partition
// label the corresponding PIs of the care set // label the corresponding PIs of the care set
Aig_ManIncrementTravId( pCare ); Aig_ManIncrementTravId( pCare );
Vec_PtrForEachEntry( vLeaves, pLeaf, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vLeaves, pLeaf, i )
{ {
pPi = Aig_ManPi( pCare, Aig_ObjPioNum(pLeaf) ); pPi = Aig_ManPi( pCare, Aig_ObjPioNum(pLeaf) );
Aig_ObjSetTravIdCurrent( pCare, pPi ); Aig_ObjSetTravIdCurrent( pCare, pPi );
pPi->pData = pLeaf->pData; pPi->pData = pLeaf->pData;
} }
// construct the constraints // construct the constraints
Vec_PtrForEachEntry( vLeaves, pLeaf, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vLeaves, pLeaf, i )
{ {
vOuts = Vec_VecEntry( vSuppsInv, Aig_ObjPioNum(pLeaf) ); vOuts = (Vec_Int_t *)Vec_VecEntry( vSuppsInv, Aig_ObjPioNum(pLeaf) );
Vec_IntForEachEntry( vOuts, iOut, k ) Vec_IntForEachEntry( vOuts, iOut, k )
{ {
pPo = Aig_ManPo( pCare, iOut ); pPo = Aig_ManPo( pCare, iOut );
@ -411,17 +414,17 @@ void Cgt_ManConstructCare( Aig_Man_t * pNew, Aig_Man_t * pCare, Vec_Vec_t * vSup
Aig_Obj_t * Cgt_ManDupPartition_rec( Aig_Man_t * pNew, Aig_Man_t * pAig, Aig_Obj_t * pObj, Vec_Ptr_t * vLeaves ) Aig_Obj_t * Cgt_ManDupPartition_rec( Aig_Man_t * pNew, Aig_Man_t * pAig, Aig_Obj_t * pObj, Vec_Ptr_t * vLeaves )
{ {
if ( Aig_ObjIsTravIdCurrent(pAig, pObj) ) if ( Aig_ObjIsTravIdCurrent(pAig, pObj) )
return pObj->pData; return (Aig_Obj_t *)pObj->pData;
Aig_ObjSetTravIdCurrent(pAig, pObj); Aig_ObjSetTravIdCurrent(pAig, pObj);
if ( Aig_ObjIsPi(pObj) ) if ( Aig_ObjIsPi(pObj) )
{ {
pObj->pData = Aig_ObjCreatePi( pNew ); pObj->pData = Aig_ObjCreatePi( pNew );
Vec_PtrPush( vLeaves, pObj ); Vec_PtrPush( vLeaves, pObj );
return pObj->pData; return (Aig_Obj_t *)pObj->pData;
} }
Cgt_ManDupPartition_rec( pNew, pAig, Aig_ObjFanin0(pObj), vLeaves ); Cgt_ManDupPartition_rec( pNew, pAig, Aig_ObjFanin0(pObj), vLeaves );
Cgt_ManDupPartition_rec( pNew, pAig, Aig_ObjFanin1(pObj), vLeaves ); Cgt_ManDupPartition_rec( pNew, pAig, Aig_ObjFanin1(pObj), vLeaves );
return pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) ); return (Aig_Obj_t *)(pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) ));
} }
/**Function************************************************************* /**Function*************************************************************
@ -469,8 +472,8 @@ Aig_Man_t * Cgt_ManDupPartition( Aig_Man_t * pFrame, int nVarsMin, int nFlopsMin
if ( pCare ) if ( pCare )
Cgt_ManConstructCare( pNew, pCare, vSuppsInv, vLeaves ); Cgt_ManConstructCare( pNew, pCare, vSuppsInv, vLeaves );
// create POs // create POs
Vec_PtrForEachEntry( vPos, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vPos, pObj, i )
pObj->pData = Aig_ObjCreatePo( pNew, Vec_PtrEntry(vRoots, i) ); pObj->pData = (Aig_Obj_t *)Aig_ObjCreatePo( pNew, (Aig_Obj_t *)Vec_PtrEntry(vRoots, i) );
if ( pnOutputs != NULL ) if ( pnOutputs != NULL )
*pnOutputs = Vec_PtrSize( vPos ); *pnOutputs = Vec_PtrSize( vPos );
Vec_PtrFree( vRoots ); Vec_PtrFree( vRoots );
@ -496,12 +499,12 @@ Aig_Obj_t * Cgt_ManBuildClockGate( Aig_Man_t * pNew, Vec_Ptr_t * vGates )
int i; int i;
assert( Vec_PtrSize(vGates) > 0 ); assert( Vec_PtrSize(vGates) > 0 );
pTotal = Aig_ManConst0(pNew); pTotal = Aig_ManConst0(pNew);
Vec_PtrForEachEntry( vGates, pGate, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vGates, pGate, i )
{ {
if ( Aig_Regular(pGate)->pNext ) if ( Aig_Regular(pGate)->pNext )
pGate = Aig_NotCond( Aig_Regular(pGate)->pNext, Aig_IsComplement(pGate) ); pGate = Aig_NotCond( Aig_Regular(pGate)->pNext, Aig_IsComplement(pGate) );
else else
pGate = Aig_NotCond( Aig_Regular(pGate)->pData, Aig_IsComplement(pGate) ); pGate = Aig_NotCond( (Aig_Obj_t *)Aig_Regular(pGate)->pData, Aig_IsComplement(pGate) );
pTotal = Aig_Or( pNew, pTotal, pGate ); pTotal = Aig_Or( pNew, pTotal, pGate );
} }
return pTotal; return pTotal;
@ -526,7 +529,7 @@ Aig_Man_t * Cgt_ManDeriveGatedAig( Aig_Man_t * pAig, Vec_Vec_t * vGates, int fRe
int i, k; int i, k;
Aig_ManCleanNext( pAig ); Aig_ManCleanNext( pAig );
// label nodes // label nodes
Vec_VecForEachEntry( vGates, pObj, i, k ) Vec_VecForEachEntry( Aig_Obj_t *, vGates, pObj, i, k )
{ {
if ( Aig_IsComplement(pObj) ) if ( Aig_IsComplement(pObj) )
Aig_Regular(pObj)->fMarkB = 1; Aig_Regular(pObj)->fMarkB = 1;
@ -549,12 +552,12 @@ Aig_Man_t * Cgt_ManDeriveGatedAig( Aig_Man_t * pAig, Vec_Vec_t * vGates, int fRe
pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) ); pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
if ( pObj->fMarkA ) if ( pObj->fMarkA )
{ {
pObj->pNext = pObj->pData; pObj->pNext = (Aig_Obj_t *)pObj->pData;
pObj->pData = Aig_ManConst0(pNew); pObj->pData = Aig_ManConst0(pNew);
} }
else if ( pObj->fMarkB ) else if ( pObj->fMarkB )
{ {
pObj->pNext = pObj->pData; pObj->pNext = (Aig_Obj_t *)pObj->pData;
pObj->pData = Aig_ManConst1(pNew); pObj->pData = Aig_ManConst1(pNew);
} }
} }
@ -570,14 +573,14 @@ Aig_Man_t * Cgt_ManDeriveGatedAig( Aig_Man_t * pAig, Vec_Vec_t * vGates, int fRe
pObj->pData = Aig_ObjCreatePo( pNew, Aig_ObjChild0Copy(pObj) ); pObj->pData = Aig_ObjCreatePo( pNew, Aig_ObjChild0Copy(pObj) );
Saig_ManForEachLiLo( pAig, pObjLi, pObjLo, i ) Saig_ManForEachLiLo( pAig, pObjLi, pObjLo, i )
{ {
vOne = Vec_VecEntry( vGates, i ); vOne = (Vec_Ptr_t *)Vec_VecEntry( vGates, i );
if ( Vec_PtrSize(vOne) == 0 ) if ( Vec_PtrSize(vOne) == 0 )
pObjNew = Aig_ObjChild0Copy(pObjLi); pObjNew = Aig_ObjChild0Copy(pObjLi);
else else
{ {
// pGateNew = Aig_NotCond( Aig_Regular(pGate)->pData, Aig_IsComplement(pGate) ); // pGateNew = Aig_NotCond( Aig_Regular(pGate)->pData, Aig_IsComplement(pGate) );
pGateNew = Cgt_ManBuildClockGate( pNew, vOne ); pGateNew = Cgt_ManBuildClockGate( pNew, vOne );
pObjNew = Aig_Mux( pNew, pGateNew, pObjLo->pData, Aig_ObjChild0Copy(pObjLi) ); pObjNew = Aig_Mux( pNew, pGateNew, (Aig_Obj_t *)pObjLo->pData, Aig_ObjChild0Copy(pObjLi) );
} }
pObjLi->pData = Aig_ObjCreatePo( pNew, pObjNew ); pObjLi->pData = Aig_ObjCreatePo( pNew, pObjNew );
} }
@ -594,3 +597,5 @@ Aig_Man_t * Cgt_ManDeriveGatedAig( Aig_Man_t * pAig, Vec_Vec_t * vGates, int fRe
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

23
src/aig/cgt/cgtCore.c
View File

@ -21,6 +21,9 @@
#include "cgtInt.h" #include "cgtInt.h"
#include "bar.h" #include "bar.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -68,8 +71,8 @@ int Cgt_SimulationFilter( Cgt_Man_t * p, Aig_Obj_t * pCandPart, Aig_Obj_t * pMit
{ {
unsigned * pInfoCand, * pInfoMiter; unsigned * pInfoCand, * pInfoMiter;
int w, nWords = Aig_BitWordNum( p->nPatts ); int w, nWords = Aig_BitWordNum( p->nPatts );
pInfoCand = Vec_PtrEntry( p->vPatts, Aig_ObjId(Aig_Regular(pCandPart)) ); pInfoCand = (unsigned *)Vec_PtrEntry( p->vPatts, Aig_ObjId(Aig_Regular(pCandPart)) );
pInfoMiter = Vec_PtrEntry( p->vPatts, Aig_ObjId(pMiterPart) ); pInfoMiter = (unsigned *)Vec_PtrEntry( p->vPatts, Aig_ObjId(pMiterPart) );
// C => !M -- true is the same as C & M -- false // C => !M -- true is the same as C & M -- false
if ( !Aig_IsComplement(pCandPart) ) if ( !Aig_IsComplement(pCandPart) )
{ {
@ -103,7 +106,7 @@ void Cgt_SimulationRecord( Cgt_Man_t * p )
int i; int i;
Aig_ManForEachObj( p->pPart, pObj, i ) Aig_ManForEachObj( p->pPart, pObj, i )
if ( sat_solver_var_value( p->pSat, p->pCnf->pVarNums[i] ) ) if ( sat_solver_var_value( p->pSat, p->pCnf->pVarNums[i] ) )
Aig_InfoSetBit( Vec_PtrEntry(p->vPatts, i), p->nPatts ); Aig_InfoSetBit( (unsigned *)Vec_PtrEntry(p->vPatts, i), p->nPatts );
p->nPatts++; p->nPatts++;
if ( p->nPatts == 32 * p->nPattWords ) if ( p->nPatts == 32 * p->nPattWords )
{ {
@ -137,14 +140,14 @@ void Cgt_ClockGatingRangeCheck( Cgt_Man_t * p, int iStart, int nOutputs )
pMiter = Saig_ManLi( p->pAig, i ); pMiter = Saig_ManLi( p->pAig, i );
Cgt_ManDetectCandidates( p->pAig, Aig_ObjFanin0(pMiter), p->pPars->nLevelMax, vNodes ); Cgt_ManDetectCandidates( p->pAig, Aig_ObjFanin0(pMiter), p->pPars->nLevelMax, vNodes );
// go through the candidates of this PO // go through the candidates of this PO
Vec_PtrForEachEntry( vNodes, pCand, k ) Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pCand, k )
{ {
// get the corresponding nodes from the frames // get the corresponding nodes from the frames
pCandFrame = pCand->pData; pCandFrame = (Aig_Obj_t *)pCand->pData;
pMiterFrame = pMiter->pData; pMiterFrame = (Aig_Obj_t *)pMiter->pData;
// get the corresponding nodes from the part // get the corresponding nodes from the part
pCandPart = pCandFrame->pData; pCandPart = (Aig_Obj_t *)pCandFrame->pData;
pMiterPart = pMiterFrame->pData; pMiterPart = (Aig_Obj_t *)pMiterFrame->pData;
// try direct polarity // try direct polarity
if ( Cgt_SimulationFilter( p, pCandPart, pMiterPart ) ) if ( Cgt_SimulationFilter( p, pCandPart, pMiterPart ) )
{ {
@ -205,7 +208,7 @@ int Cgt_ClockGatingRange( Cgt_Man_t * p, int iStart )
clk = clock(); clk = clock();
p->pPart = Cgt_ManDupPartition( p->pFrame, p->pPars->nVarsMin, p->pPars->nFlopsMin, iStart, p->pCare, p->vSuppsInv, &nOutputs ); p->pPart = Cgt_ManDupPartition( p->pFrame, p->pPars->nVarsMin, p->pPars->nFlopsMin, iStart, p->pCare, p->vSuppsInv, &nOutputs );
p->pCnf = Cnf_DeriveSimple( p->pPart, nOutputs ); p->pCnf = Cnf_DeriveSimple( p->pPart, nOutputs );
p->pSat = Cnf_DataWriteIntoSolver( p->pCnf, 1, 0 ); p->pSat = (sat_solver *)Cnf_DataWriteIntoSolver( p->pCnf, 1, 0 );
sat_solver_compress( p->pSat ); sat_solver_compress( p->pSat );
p->vPatts = Vec_PtrAllocSimInfo( Aig_ManObjNumMax(p->pPart), p->nPattWords ); p->vPatts = Vec_PtrAllocSimInfo( Aig_ManObjNumMax(p->pPart), p->nPattWords );
Vec_PtrCleanSimInfo( p->vPatts, 0, p->nPattWords ); Vec_PtrCleanSimInfo( p->vPatts, 0, p->nPattWords );
@ -314,3 +317,5 @@ Aig_Man_t * Cgt_ClockGating( Aig_Man_t * pAig, Aig_Man_t * pCare, Cgt_Par_t * pP
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

23
src/aig/cgt/cgtDecide.c
View File

@ -21,6 +21,9 @@
#include "cgtInt.h" #include "cgtInt.h"
#include "sswInt.h" #include "sswInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -96,11 +99,11 @@ int Cgt_ManCheckGateComplete( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, Aig_Obj_t
Vec_Ptr_t * vGates; Vec_Ptr_t * vGates;
Aig_Obj_t * pObj; Aig_Obj_t * pObj;
int i; int i;
Vec_PtrForEachEntry( vFanout, pObj, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vFanout, pObj, i )
{ {
if ( Saig_ObjIsPo(pAig, pObj) ) if ( Saig_ObjIsPo(pAig, pObj) )
return 0; return 0;
vGates = Vec_VecEntry( vGatesAll, Aig_ObjPioNum(pObj) - Saig_ManPoNum(pAig) ); vGates = (Vec_Ptr_t *)Vec_VecEntry( vGatesAll, Aig_ObjPioNum(pObj) - Saig_ManPoNum(pAig) );
if ( Vec_PtrFind( vGates, pGate ) == -1 ) if ( Vec_PtrFind( vGates, pGate ) == -1 )
return 0; return 0;
} }
@ -125,7 +128,7 @@ Vec_Ptr_t * Cgt_ManCompleteGates( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, int n
int i, k; int i, k;
vFanout = Vec_PtrAlloc( 100 ); vFanout = Vec_PtrAlloc( 100 );
vGatesFull = Vec_PtrAlloc( 100 ); vGatesFull = Vec_PtrAlloc( 100 );
Vec_VecForEachEntry( vGatesAll, pGate, i, k ) Vec_VecForEachEntry( Aig_Obj_t *, vGatesAll, pGate, i, k )
{ {
pGateR = Aig_Regular(pGate); pGateR = Aig_Regular(pGate);
if ( pGateR->fMarkA ) if ( pGateR->fMarkA )
@ -136,7 +139,7 @@ Vec_Ptr_t * Cgt_ManCompleteGates( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, int n
Vec_PtrPush( vGatesFull, pGate ); Vec_PtrPush( vGatesFull, pGate );
} }
Vec_PtrFree( vFanout ); Vec_PtrFree( vFanout );
Vec_VecForEachEntry( vGatesAll, pGate, i, k ) Vec_VecForEachEntry( Aig_Obj_t *, vGatesAll, pGate, i, k )
Aig_Regular(pGate)->fMarkA = 0; Aig_Regular(pGate)->fMarkA = 0;
return vGatesFull; return vGatesFull;
} }
@ -197,8 +200,8 @@ Vec_Vec_t * Cgt_ManDecideSimple( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, int nO
{ {
nHitsMax = 0; nHitsMax = 0;
pCandBest = NULL; pCandBest = NULL;
vCands = Vec_VecEntry( vGatesAll, i ); vCands = (Vec_Ptr_t *)Vec_VecEntry( vGatesAll, i );
Vec_PtrForEachEntry( vCands, pCand, k ) Vec_PtrForEachEntry( Aig_Obj_t *, vCands, pCand, k )
{ {
// check if this is indeed a clock-gate // check if this is indeed a clock-gate
if ( nOdcMax == 0 && !Ssw_SmlCheckXorImplication( pSml, pObjLi, pObjLo, pCand ) ) if ( nOdcMax == 0 && !Ssw_SmlCheckXorImplication( pSml, pObjLi, pObjLo, pCand ) )
@ -260,15 +263,15 @@ Vec_Vec_t * Cgt_ManDecideArea( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, int nOdc
// derive and label complete gates // derive and label complete gates
vCompletes = Cgt_ManCompleteGates( pAig, vGatesAll, nOdcMax, fVerbose ); vCompletes = Cgt_ManCompleteGates( pAig, vGatesAll, nOdcMax, fVerbose );
// label complete gates // label complete gates
Vec_PtrForEachEntry( vCompletes, pGate, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vCompletes, pGate, i )
Aig_Regular(pGate)->fMarkA = 1; Aig_Regular(pGate)->fMarkA = 1;
// select only complete gates // select only complete gates
vGates = Vec_VecStart( Saig_ManRegNum(pAig) ); vGates = Vec_VecStart( Saig_ManRegNum(pAig) );
Vec_VecForEachEntry( vGatesAll, pGate, i, k ) Vec_VecForEachEntry( Aig_Obj_t *, vGatesAll, pGate, i, k )
if ( Aig_Regular(pGate)->fMarkA ) if ( Aig_Regular(pGate)->fMarkA )
Vec_VecPush( vGates, i, pGate ); Vec_VecPush( vGates, i, pGate );
// unlabel complete gates // unlabel complete gates
Vec_PtrForEachEntry( vCompletes, pGate, i ) Vec_PtrForEachEntry( Aig_Obj_t *, vCompletes, pGate, i )
Aig_Regular(pGate)->fMarkA = 0; Aig_Regular(pGate)->fMarkA = 0;
// count the number of gated flops // count the number of gated flops
Vec_VecForEachLevel( vGates, vOne, i ) Vec_VecForEachLevel( vGates, vOne, i )
@ -294,3 +297,5 @@ Vec_Vec_t * Cgt_ManDecideArea( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, int nOdc
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

16
src/aig/cgt/cgtInt.h
View File

@ -21,6 +21,7 @@
#ifndef __CGT_INT_H__ #ifndef __CGT_INT_H__
#define __CGT_INT_H__ #define __CGT_INT_H__
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// INCLUDES /// /// INCLUDES ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -34,9 +35,10 @@
/// PARAMETERS /// /// PARAMETERS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
extern "C" {
#endif ABC_NAMESPACE_HEADER_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// BASIC TYPES /// /// BASIC TYPES ///
@ -106,9 +108,11 @@ extern void Cgt_ManStop( Cgt_Man_t * p );
/*=== cgtSat.c ==========================================================*/ /*=== cgtSat.c ==========================================================*/
extern int Cgt_CheckImplication( Cgt_Man_t * p, Aig_Obj_t * pGate, Aig_Obj_t * pFlop ); extern int Cgt_CheckImplication( Cgt_Man_t * p, Aig_Obj_t * pGate, Aig_Obj_t * pFlop );
#ifdef __cplusplus
}
#endif ABC_NAMESPACE_HEADER_END
#endif #endif

5
src/aig/cgt/cgtMan.c
View File

@ -20,6 +20,9 @@
#include "cgtInt.h" #include "cgtInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -172,3 +175,5 @@ void Cgt_ManStop( Cgt_Man_t * p )
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

5
src/aig/cgt/cgtSat.c
View File

@ -20,6 +20,9 @@
#include "cgtInt.h" #include "cgtInt.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -90,3 +93,5 @@ p->timeSatUndec += clock() - clk;
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

21
src/aig/cnf/cnf.h
View File

@ -21,6 +21,7 @@
#ifndef __CNF_H__ #ifndef __CNF_H__
#define __CNF_H__ #define __CNF_H__
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// INCLUDES /// /// INCLUDES ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -39,9 +40,10 @@
/// PARAMETERS /// /// PARAMETERS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
extern "C" {
#endif ABC_NAMESPACE_HEADER_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// BASIC TYPES /// /// BASIC TYPES ///
@ -97,7 +99,7 @@ static inline int Cnf_CutLeaveNum( Cnf_Cut_t * pCut ) { return pCut-
static inline int * Cnf_CutLeaves( Cnf_Cut_t * pCut ) { return pCut->pFanins; } static inline int * Cnf_CutLeaves( Cnf_Cut_t * pCut ) { return pCut->pFanins; }
static inline unsigned * Cnf_CutTruth( Cnf_Cut_t * pCut ) { return (unsigned *)(pCut->pFanins + pCut->nFanins); } static inline unsigned * Cnf_CutTruth( Cnf_Cut_t * pCut ) { return (unsigned *)(pCut->pFanins + pCut->nFanins); }
static inline Cnf_Cut_t * Cnf_ObjBestCut( Aig_Obj_t * pObj ) { return pObj->pData; } static inline Cnf_Cut_t * Cnf_ObjBestCut( Aig_Obj_t * pObj ) { return (Cnf_Cut_t *)pObj->pData; }
static inline void Cnf_ObjSetBestCut( Aig_Obj_t * pObj, Cnf_Cut_t * pCut ) { pObj->pData = pCut; } static inline void Cnf_ObjSetBestCut( Aig_Obj_t * pObj, Cnf_Cut_t * pCut ) { pObj->pData = pCut; }
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -121,6 +123,7 @@ static inline void Cnf_ObjSetBestCut( Aig_Obj_t * pObj, Cnf_Cut_t * pCut
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/*=== cnfCore.c ========================================================*/ /*=== cnfCore.c ========================================================*/
extern Vec_Int_t * Cnf_DeriveMappingArray( Aig_Man_t * pAig );
extern Cnf_Dat_t * Cnf_Derive( Aig_Man_t * pAig, int nOutputs ); extern Cnf_Dat_t * Cnf_Derive( Aig_Man_t * pAig, int nOutputs );
extern Cnf_Man_t * Cnf_ManRead(); extern Cnf_Man_t * Cnf_ManRead();
extern void Cnf_ClearMemory(); extern void Cnf_ClearMemory();
@ -147,6 +150,7 @@ extern void * Cnf_DataWriteIntoSolver( Cnf_Dat_t * p, int nFrames, int
extern int Cnf_DataWriteOrClause( void * pSat, Cnf_Dat_t * pCnf ); extern int Cnf_DataWriteOrClause( void * pSat, Cnf_Dat_t * pCnf );
extern int Cnf_DataWriteAndClauses( void * p, Cnf_Dat_t * pCnf ); extern int Cnf_DataWriteAndClauses( void * p, Cnf_Dat_t * pCnf );
extern void Cnf_DataTranformPolarity( Cnf_Dat_t * pCnf, int fTransformPos ); extern void Cnf_DataTranformPolarity( Cnf_Dat_t * pCnf, int fTransformPos );
extern int Cnf_DataAddXorClause( void * pSat, int iVarA, int iVarB, int iVarC );
/*=== cnfMap.c ========================================================*/ /*=== cnfMap.c ========================================================*/
extern void Cnf_DeriveMapping( Cnf_Man_t * p ); extern void Cnf_DeriveMapping( Cnf_Man_t * p );
extern int Cnf_ManMapForCnf( Cnf_Man_t * p ); extern int Cnf_ManMapForCnf( Cnf_Man_t * p );
@ -160,14 +164,17 @@ extern Vec_Ptr_t * Cnf_ManScanMapping( Cnf_Man_t * p, int fCollect, int fPre
extern Vec_Int_t * Cnf_DataCollectCiSatNums( Cnf_Dat_t * pCnf, Aig_Man_t * p ); extern Vec_Int_t * Cnf_DataCollectCiSatNums( Cnf_Dat_t * pCnf, Aig_Man_t * p );
extern Vec_Int_t * Cnf_DataCollectCoSatNums( Cnf_Dat_t * pCnf, Aig_Man_t * p ); extern Vec_Int_t * Cnf_DataCollectCoSatNums( Cnf_Dat_t * pCnf, Aig_Man_t * p );
/*=== cnfWrite.c ========================================================*/ /*=== cnfWrite.c ========================================================*/
extern Vec_Int_t * Cnf_ManWriteCnfMapping( Cnf_Man_t * p, Vec_Ptr_t * vMapped );
extern void Cnf_SopConvertToVector( char * pSop, int nCubes, Vec_Int_t * vCover ); extern void Cnf_SopConvertToVector( char * pSop, int nCubes, Vec_Int_t * vCover );
extern Cnf_Dat_t * Cnf_ManWriteCnf( Cnf_Man_t * p, Vec_Ptr_t * vMapped, int nOutputs ); extern Cnf_Dat_t * Cnf_ManWriteCnf( Cnf_Man_t * p, Vec_Ptr_t * vMapped, int nOutputs );
extern Cnf_Dat_t * Cnf_DeriveSimple( Aig_Man_t * p, int nOutputs ); extern Cnf_Dat_t * Cnf_DeriveSimple( Aig_Man_t * p, int nOutputs );
extern Cnf_Dat_t * Cnf_DeriveSimpleForRetiming( Aig_Man_t * p ); extern Cnf_Dat_t * Cnf_DeriveSimpleForRetiming( Aig_Man_t * p );
#ifdef __cplusplus
}
#endif ABC_NAMESPACE_HEADER_END
#endif #endif

58
src/aig/cnf/cnfCore.c
View File

@ -20,6 +20,9 @@
#include "cnf.h" #include "cnf.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -30,6 +33,59 @@ static Cnf_Man_t * s_pManCnf = NULL;
/// FUNCTION DEFINITIONS /// /// FUNCTION DEFINITIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Converts AIG into the SAT solver.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Cnf_DeriveMappingArray( Aig_Man_t * pAig )
{
Vec_Int_t * vResult;
Cnf_Man_t * p;
Vec_Ptr_t * vMapped;
Aig_MmFixed_t * pMemCuts;
int clk;
// allocate the CNF manager
if ( s_pManCnf == NULL )
s_pManCnf = Cnf_ManStart();
// connect the managers
p = s_pManCnf;
p->pManAig = pAig;
// generate cuts for all nodes, assign cost, and find best cuts
clk = clock();
pMemCuts = Dar_ManComputeCuts( pAig, 10, 0 );
p->timeCuts = clock() - clk;
// find the mapping
clk = clock();
Cnf_DeriveMapping( p );
p->timeMap = clock() - clk;
// Aig_ManScanMapping( p, 1 );
// convert it into CNF
clk = clock();
Cnf_ManTransferCuts( p );
vMapped = Cnf_ManScanMapping( p, 1, 0 );
vResult = Cnf_ManWriteCnfMapping( p, vMapped );
Vec_PtrFree( vMapped );
Aig_MmFixedStop( pMemCuts, 0 );
p->timeSave = clock() - clk;
// reset reference counters
Aig_ManResetRefs( pAig );
//ABC_PRT( "Cuts ", p->timeCuts );
//ABC_PRT( "Map ", p->timeMap );
//ABC_PRT( "Saving ", p->timeSave );
return vResult;
}
/**Function************************************************************* /**Function*************************************************************
Synopsis [Converts AIG into the SAT solver.] Synopsis [Converts AIG into the SAT solver.]
@ -183,3 +239,5 @@ ABC_PRT( "Ext ", clock() - clk );
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

5
src/aig/cnf/cnfCut.c
View File

@ -21,6 +21,9 @@
#include "cnf.h" #include "cnf.h"
#include "kit.h" #include "kit.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -369,3 +372,5 @@ Cnf_Cut_t * Cnf_CutCompose( Cnf_Man_t * p, Cnf_Cut_t * pCut, Cnf_Cut_t * pCutFan
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

9
src/aig/cnf/cnfData.c
View File

@ -20,13 +20,16 @@
#include "cnf.h" #include "cnf.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
static char s_Data3[81] = "!#&()*+,-.0123456789:;<=>?ABCDEFGHIJKLMNOPQRSTUVWXYZ[]abcdefghijklmnopqrstuvwxyz|"; static const char s_Data3[82] = "!#&()*+,-.0123456789:;<=>?ABCDEFGHIJKLMNOPQRSTUVWXYZ[]abcdefghijklmnopqrstuvwxyz|";
static char * s_Data4[] = { static const char * s_Data4[] = {
"! B a . 8 .B 8a K !K T Ta j 8j Tj s ( + (B +a (. +8 .B( +8a (K +K T( +T j( ", "! B a . 8 .B 8a K !K T Ta j 8j Tj s ( + (B +a (. +8 .B( +8a (K +K T( +T j( ",
"+j Tj( s+ E !E H Ha E. 8E H. H8 EK EK! HT HTa jE 8jE Hj sH d +d Hd g d. 8d ", "+j Tj( s+ E !E H Ha E. 8E H. H8 EK EK! HT HTa jE 8jE Hj sH d +d Hd g d. 8d ",
"Hd. g8 dK +dK Td gT dj +jd Hjd gs 2 !2 2B a2 5 58 5B 5a 2K 2K! T2 Ta2 5j 58", "Hd. g8 dK +dK Td gT dj +jd Hjd gs 2 !2 2B a2 5 58 5B 5a 2K 2K! T2 Ta2 5j 58",
@ -4782,3 +4785,5 @@ int Aig_ManDeriveCnfTest2()
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

52
src/aig/cnf/cnfMan.c
View File

@ -22,6 +22,9 @@
#include "satSolver.h" #include "satSolver.h"
#include "zlib.h" #include "zlib.h"
ABC_NAMESPACE_IMPL_START
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// DECLARATIONS /// /// DECLARATIONS ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -422,7 +425,7 @@ void * Cnf_DataWriteIntoSolver( Cnf_Dat_t * p, int nFrames, int fInit )
***********************************************************************/ ***********************************************************************/
int Cnf_DataWriteOrClause( void * p, Cnf_Dat_t * pCnf ) int Cnf_DataWriteOrClause( void * p, Cnf_Dat_t * pCnf )
{ {
sat_solver * pSat = p; sat_solver * pSat = (sat_solver *)p;
Aig_Obj_t * pObj; Aig_Obj_t * pObj;
int i, * pLits; int i, * pLits;
pLits = ABC_ALLOC( int, Aig_ManPoNum(pCnf->pMan) ); pLits = ABC_ALLOC( int, Aig_ManPoNum(pCnf->pMan) );
@ -450,7 +453,7 @@ int Cnf_DataWriteOrClause( void * p, Cnf_Dat_t * pCnf )
***********************************************************************/ ***********************************************************************/
int Cnf_DataWriteAndClauses( void * p, Cnf_Dat_t * pCnf ) int Cnf_DataWriteAndClauses( void * p, Cnf_Dat_t * pCnf )
{ {
sat_solver * pSat = p; sat_solver * pSat = (sat_solver *)p;
Aig_Obj_t * pObj; Aig_Obj_t * pObj;
int i, Lit; int i, Lit;
Aig_ManForEachPo( pCnf->pMan, pObj, i ) Aig_ManForEachPo( pCnf->pMan, pObj, i )
@ -498,8 +501,53 @@ void Cnf_DataTranformPolarity( Cnf_Dat_t * pCnf, int fTransformPos )
ABC_FREE( pVarToPol ); ABC_FREE( pVarToPol );
} }
/**Function*************************************************************
Synopsis [Adds constraints for the two-input AND-gate.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Cnf_DataAddXorClause( void * pSat, int iVarA, int iVarB, int iVarC )
{
lit Lits[3];
assert( iVarA > 0 && iVarB > 0 && iVarC > 0 );
Lits[0] = toLitCond( iVarA, 1 );
Lits[1] = toLitCond( iVarB, 1 );
Lits[2] = toLitCond( iVarC, 1 );
if ( !sat_solver_addclause( (sat_solver *)pSat, Lits, Lits + 3 ) )
return 0;
Lits[0] = toLitCond( iVarA, 1 );
Lits[1] = toLitCond( iVarB, 0 );
Lits[2] = toLitCond( iVarC, 0 );
if ( !sat_solver_addclause( (sat_solver *)pSat, Lits, Lits + 3 ) )
return 0;
Lits[0] = toLitCond( iVarA, 0 );
Lits[1] = toLitCond( iVarB, 1 );
Lits[2] = toLitCond( iVarC, 0 );
if ( !sat_solver_addclause( (sat_solver *)pSat, Lits, Lits + 3 ) )
return 0;
Lits[0] = toLitCond( iVarA, 0 );
Lits[1] = toLitCond( iVarB, 0 );
Lits[2] = toLitCond( iVarC, 1 );
if ( !sat_solver_addclause( (sat_solver *)pSat, Lits, Lits + 3 ) )
return 0;
return 1;
}
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
/// END OF FILE /// /// END OF FILE ///
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
ABC_NAMESPACE_IMPL_END

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