mirror of https://github.com/YosysHQ/abc.git
Generation of dual-rail miter.
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Alan Mishchenko
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99b408fcb1
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/**CFile****************************************************************
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FileName [saigDual.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Sequential AIG package.]
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Synopsis [Various duplication procedures.]
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Author [Alan Mishchenko]
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Affiliation [UC Berkeley]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: saigDual.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "saig.h"
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ABC_NAMESPACE_IMPL_START
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////////////////////////////////////////////////////////////////////////
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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static inline void Saig_ObjSetDual( Vec_Ptr_t * vCopies, int Id, int fPos, Aig_Obj_t * pItem ) { Vec_PtrWriteEntry( vCopies, 2*Id+fPos, pItem ); }
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static inline Aig_Obj_t * Saig_ObjDual( Vec_Ptr_t * vCopies, int Id, int fPos ) { return (Aig_Obj_t *)Vec_PtrEntry( vCopies, 2*Id+fPos ); }
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static inline void Saig_ObjDualFanin( Aig_Man_t * pAigNew, Vec_Ptr_t * vCopies, Aig_Obj_t * pObj, int iFanin, Aig_Obj_t ** ppRes0, Aig_Obj_t ** ppRes1 ) {
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Aig_Obj_t * pTemp0, * pTemp1, * pCare;
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int fCompl;
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assert( iFanin == 0 || iFanin == 1 );
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if ( iFanin == 0 )
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{
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pTemp0 = Saig_ObjDual( vCopies, Aig_ObjFaninId0(pObj), 0 );
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pTemp1 = Saig_ObjDual( vCopies, Aig_ObjFaninId0(pObj), 1 );
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fCompl = Aig_ObjFaninC0( pObj );
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}
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else
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{
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pTemp0 = Saig_ObjDual( vCopies, Aig_ObjFaninId1(pObj), 0 );
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pTemp1 = Saig_ObjDual( vCopies, Aig_ObjFaninId1(pObj), 1 );
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fCompl = Aig_ObjFaninC1( pObj );
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}
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if ( fCompl )
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{
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pCare = Aig_Or( pAigNew, pTemp0, pTemp1 );
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*ppRes0 = Aig_And( pAigNew, pTemp1, pCare );
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*ppRes1 = Aig_And( pAigNew, pTemp0, pCare );
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}
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else
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{
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*ppRes0 = pTemp0;
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*ppRes1 = pTemp1;
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}
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}
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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/**Function*************************************************************
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Synopsis [Transforms sequential AIG into dual-rail miter.]
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Description [Transforms sequential AIG into a miter encoding ternary
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problem formulated as follows "none of the POs has a ternary value".
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Interprets the first nDualPis as having ternary value. Sets flops
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to have ternary intial value when fDualFfs is set to 1.]
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Aig_Man_t * Saig_ManDupDual( Aig_Man_t * pAig, int nDualPis, int fDualFfs, int fMiterFfs, int fComplPo )
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{
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Vec_Ptr_t * vCopies;
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Aig_Man_t * pAigNew;
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Aig_Obj_t * pObj, * pTemp0, * pTemp1, * pTemp2, * pTemp3, * pCare, * pMiter;
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int i;
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assert( Saig_ManPoNum(pAig) > 0 );
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assert( nDualPis >= 0 && nDualPis <= Saig_ManPiNum(pAig) );
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vCopies = Vec_PtrStart( 2*Aig_ManObjNum(pAig) );
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// start the new manager
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pAigNew = Aig_ManStart( Aig_ManNodeNum(pAig) );
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pAigNew->pName = Abc_UtilStrsav( pAig->pName );
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// map the constant node
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Saig_ObjSetDual( vCopies, 0, 0, Aig_ManConst0(pAigNew) );
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Saig_ObjSetDual( vCopies, 0, 1, Aig_ManConst1(pAigNew) );
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// create variables for PIs
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Aig_ManForEachPi( pAig, pObj, i )
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{
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if ( i < nDualPis )
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{
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pTemp0 = Aig_ObjCreatePi( pAigNew );
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pTemp1 = Aig_ObjCreatePi( pAigNew );
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}
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else if ( i < Saig_ManPiNum(pAig) )
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{
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pTemp1 = Aig_ObjCreatePi( pAigNew );
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pTemp0 = Aig_Not( pTemp1 );
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}
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else
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{
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pTemp0 = Aig_ObjCreatePi( pAigNew );
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pTemp1 = Aig_ObjCreatePi( pAigNew );
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pTemp0 = Aig_NotCond( pTemp0, !fDualFfs );
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}
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Saig_ObjSetDual( vCopies, Aig_ObjId(pObj), 0, Aig_And(pAigNew, pTemp0, Aig_Not(pTemp1)) );
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Saig_ObjSetDual( vCopies, Aig_ObjId(pObj), 1, Aig_And(pAigNew, pTemp1, Aig_Not(pTemp0)) );
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}
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// create internal nodes
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Aig_ManForEachNode( pAig, pObj, i )
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{
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Saig_ObjDualFanin( pAigNew, vCopies, pObj, 0, &pTemp0, &pTemp1 );
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Saig_ObjDualFanin( pAigNew, vCopies, pObj, 1, &pTemp2, &pTemp3 );
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Saig_ObjSetDual( vCopies, Aig_ObjId(pObj), 0, Aig_Or (pAigNew, pTemp0, pTemp2) );
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Saig_ObjSetDual( vCopies, Aig_ObjId(pObj), 1, Aig_And(pAigNew, pTemp1, pTemp3) );
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}
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// create miter and flops
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pMiter = Aig_ManConst0(pAigNew);
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if ( fMiterFfs )
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{
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Saig_ManForEachLi( pAig, pObj, i )
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{
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Saig_ObjDualFanin( pAigNew, vCopies, pObj, 0, &pTemp0, &pTemp1 );
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pCare = Aig_Or( pAigNew, pTemp0, pTemp1 );
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pMiter = Aig_Or( pAigNew, pMiter, Aig_Not(pCare) );
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}
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}
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else
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{
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Saig_ManForEachPo( pAig, pObj, i )
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{
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Saig_ObjDualFanin( pAigNew, vCopies, pObj, 0, &pTemp0, &pTemp1 );
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pCare = Aig_Or( pAigNew, pTemp0, pTemp1 );
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pMiter = Aig_Or( pAigNew, pMiter, Aig_Not(pCare) );
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}
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}
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// create PO
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pMiter = Aig_NotCond( pMiter, fComplPo );
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Aig_ObjCreatePo( pAigNew, pMiter );
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// create flops
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Saig_ManForEachLi( pAig, pObj, i )
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{
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Saig_ObjDualFanin( pAigNew, vCopies, pObj, 0, &pTemp0, &pTemp1 );
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pTemp0 = Aig_NotCond( pTemp0, !fDualFfs );
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Aig_ObjCreatePo( pAigNew, pTemp0 );
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Aig_ObjCreatePo( pAigNew, pTemp1 );
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}
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// set the flops
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Aig_ManSetRegNum( pAigNew, 2 * Aig_ManRegNum(pAig) );
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Aig_ManCleanup( pAigNew );
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Vec_PtrFree( vCopies );
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return pAigNew;
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}
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/**Function*************************************************************
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Synopsis [Transforms sequential AIG to block the PO for N cycles.]
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Description [This procedure should be applied to a safety property
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miter to make the propetry 'true' (const 0) during the first N cycles.]
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Saig_ManBlockPo( Aig_Man_t * pAig, int nCycles )
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{
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Aig_Obj_t * pObj, * pCond, * pPrev;
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int i;
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assert( nCycles > 0 );
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// add N flops (assuming 1-hot encoding of cycles)
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pPrev = Aig_ManConst1(pAig);
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pCond = Aig_ManConst1(pAig);
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for ( i = 0; i < nCycles; i++ )
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{
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Aig_ObjCreatePo( pAig, pPrev );
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pPrev = Aig_ObjCreatePi( pAig );
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pCond = Aig_And( pAig, pCond, pPrev );
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}
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// update the POs
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Saig_ManForEachPo( pAig, pObj, i )
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{
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pCond = Aig_And( pAig, Aig_ObjChild0(pObj), pCond );
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Aig_ObjPatchFanin0( pAig, pObj, pCond );
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}
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// set the flops
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Aig_ManSetRegNum( pAig, Aig_ManRegNum(pAig) + nCycles );
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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ABC_NAMESPACE_IMPL_END
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