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Preparing new implementation of SOP/DSD balancing in 'if' mapper.

This commit is contained in:
Alan Mishchenko 2014-04-05 11:06:35 -07:00
parent 424b86a556
commit 5608d947ed
6 changed files with 125 additions and 47 deletions
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10
src/aig/gia/giaIf.c
View File

@ -691,7 +691,7 @@ Gia_Man_t * Gia_ManFromIfAig( If_Man_t * pIfMan )
Vec_Int_t * vCover;
int i, k;
assert( pIfMan->pPars->pLutStruct == NULL );
assert( pIfMan->pPars->fDelayOpt || pIfMan->pPars->fUserRecLib );
assert( pIfMan->pPars->fDelayOpt || pIfMan->pPars->fDsdBalance || pIfMan->pPars->fUserRecLib );
// create new manager
pNew = Gia_ManStart( If_ManObjNum(pIfMan) );
Gia_ManHashAlloc( pNew );
@ -713,6 +713,8 @@ Gia_Man_t * Gia_ManFromIfAig( If_Man_t * pIfMan )
// get the functionality
if ( pIfMan->pPars->fDelayOpt )
pIfObj->iCopy = Gia_ManNodeIfSopToGia( pNew, pIfMan, pCutBest, vLeaves, fHash );
else if ( pIfMan->pPars->fDsdBalance )
pIfObj->iCopy = If_DsdCutBalance( pNew, pIfMan, pCutBest, vLeaves, fHash );
else if ( pIfMan->pPars->fUserRecLib )
pIfObj->iCopy = Abc_RecToGia3( pNew, pIfMan, pCutBest, vLeaves, fHash );
else assert( 0 );
@ -1292,7 +1294,7 @@ Gia_Man_t * Gia_ManFromIfLogic( If_Man_t * pIfMan )
{
pCutBest = If_ObjCutBest( pIfObj );
// perform sorting of cut leaves by delay, so that the slowest pin drives the fastest input of the LUT
if ( !pIfMan->pPars->fUseTtPerm && !pIfMan->pPars->fDelayOpt && !pIfMan->pPars->pLutStruct && !pIfMan->pPars->fUserRecLib && !pIfMan->pPars->nGateSize && !pIfMan->pPars->fEnableCheck75 && !pIfMan->pPars->fEnableCheck75u && !pIfMan->pPars->fEnableCheck07 )
if ( !pIfMan->pPars->fUseTtPerm && !pIfMan->pPars->fDelayOpt && !pIfMan->pPars->fDsdBalance && !pIfMan->pPars->pLutStruct && !pIfMan->pPars->fUserRecLib && !pIfMan->pPars->nGateSize && !pIfMan->pPars->fEnableCheck75 && !pIfMan->pPars->fEnableCheck75u && !pIfMan->pPars->fEnableCheck07 )
If_CutRotatePins( pIfMan, pCutBest );
// collect leaves of the best cut
Vec_IntClear( vLeaves );
@ -1534,7 +1536,7 @@ Gia_Man_t * Gia_ManPerformMapping( Gia_Man_t * p, void * pp, int fNormalized )
If_Man_t * pIfMan;
If_Par_t * pPars = (If_Par_t *)pp;
// disable cut minimization when GIA strucure is needed
if ( !pPars->fDelayOpt && !pPars->fUserRecLib && !pPars->fDeriveLuts && !pPars->fUseDsd && !pPars->fUseTtPerm )
if ( !pPars->fDelayOpt && !pPars->fDsdBalance && !pPars->fUserRecLib && !pPars->fDeriveLuts && !pPars->fUseDsd && !pPars->fUseTtPerm )
pPars->fCutMin = 0;
// reconstruct GIA according to the hierarchy manager
@ -1593,7 +1595,7 @@ Gia_Man_t * Gia_ManPerformMapping( Gia_Man_t * p, void * pp, int fNormalized )
return NULL;
}
// transform the result of mapping into the new network
if ( pIfMan->pPars->fDelayOpt || pIfMan->pPars->fUserRecLib )
if ( pIfMan->pPars->fDelayOpt || pIfMan->pPars->fDsdBalance || pIfMan->pPars->fUserRecLib )
pNew = Gia_ManFromIfAig( pIfMan );
else
pNew = Gia_ManFromIfLogic( pIfMan );

28
src/base/abci/abc.c
View File

@ -14762,7 +14762,7 @@ int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
fLutMux = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "KCFAGNDEWSTqaflepmrsdbugyojikncvh" ) ) != EOF )
while ( ( c = Extra_UtilGetopt( argc, argv, "KCFAGNDEWSTqaflepmrsdbugxyojikncvh" ) ) != EOF )
{
switch ( c )
{
@ -14931,6 +14931,9 @@ int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
case 'g':
pPars->fDelayOpt ^= 1;
break;
case 'x':
pPars->fDsdBalance ^= 1;
break;
case 'y':
pPars->fUserRecLib ^= 1;
break;
@ -15093,8 +15096,8 @@ int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
pPars->fUsePerm = 1;
pPars->pLutLib = NULL;
}
// modify for global delay optimization
if ( pPars->fDelayOpt )
// modify for delay optimization
if ( pPars->fDelayOpt || pPars->fDsdBalance )
{
pPars->fTruth = 1;
pPars->fCutMin = 1;
@ -15102,7 +15105,7 @@ int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
pPars->fUsePerm = 1;
pPars->pLutLib = NULL;
}
// modify for global delay optimization
// modify for delay optimization
if ( pPars->nGateSize > 0 )
{
pPars->fTruth = 1;
@ -15216,7 +15219,7 @@ usage:
sprintf(LutSize, "library" );
else
sprintf(LutSize, "%d", pPars->nLutSize );
Abc_Print( -2, "usage: if [-KCFANGT num] [-DEW float] [-S str] [-qarlepmsdbugyojikncvh]\n" );
Abc_Print( -2, "usage: if [-KCFANGT num] [-DEW float] [-S str] [-qarlepmsdbugxyojikncvh]\n" );
Abc_Print( -2, "\t performs FPGA technology mapping of the network\n" );
Abc_Print( -2, "\t-K num : the number of LUT inputs (2 < num < %d) [default = %s]\n", IF_MAX_LUTSIZE+1, LutSize );
Abc_Print( -2, "\t-C num : the max number of priority cuts (0 < num < 2^12) [default = %d]\n", pPars->nCutsMax );
@ -15242,6 +15245,7 @@ usage:
Abc_Print( -2, "\t-b : toggles the use of one special feature [default = %s]\n", pPars->fUseBat? "yes": "no" );
Abc_Print( -2, "\t-u : toggles the use of MUXes along with LUTs [default = %s]\n", fLutMux? "yes": "no" );
Abc_Print( -2, "\t-g : toggles delay optimization by SOP balancing [default = %s]\n", pPars->fDelayOpt? "yes": "no" );
Abc_Print( -2, "\t-x : toggles delay optimization by DSD balancing [default = %s]\n", pPars->fDsdBalance? "yes": "no" );
Abc_Print( -2, "\t-y : toggles delay optimization with recorded library [default = %s]\n", pPars->fUserRecLib? "yes": "no" );
Abc_Print( -2, "\t-o : toggles using buffers to decouple combinational outputs [default = %s]\n", pPars->fUseBuffs? "yes": "no" );
Abc_Print( -2, "\t-j : toggles enabling additional check [default = %s]\n", pPars->fEnableCheck07? "yes": "no" );
@ -29503,7 +29507,7 @@ int Abc_CommandAbc9If( Abc_Frame_t * pAbc, int argc, char ** argv )
}
pPars->pLutLib = (If_LibLut_t *)pAbc->pLibLut;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "KCFAGRDEWSTqalepmrsdbgyojikfuztncvh" ) ) != EOF )
while ( ( c = Extra_UtilGetopt( argc, argv, "KCFAGRDEWSTqalepmrsdbgxyojikfuztncvh" ) ) != EOF )
{
switch ( c )
{
@ -29666,6 +29670,9 @@ int Abc_CommandAbc9If( Abc_Frame_t * pAbc, int argc, char ** argv )
case 'g':
pPars->fDelayOpt ^= 1;
break;
case 'x':
pPars->fDsdBalance ^= 1;
break;
case 'y':
pPars->fUserRecLib ^= 1;
break;
@ -29842,8 +29849,8 @@ int Abc_CommandAbc9If( Abc_Frame_t * pAbc, int argc, char ** argv )
pPars->fUsePerm = 1;
pPars->pLutLib = NULL;
}
// modify for global delay optimization
if ( pPars->fDelayOpt )
// modify for delay optimization
if ( pPars->fDelayOpt || pPars->fDsdBalance )
{
pPars->fTruth = 1;
pPars->fCutMin = 1;
@ -29851,7 +29858,7 @@ int Abc_CommandAbc9If( Abc_Frame_t * pAbc, int argc, char ** argv )
pPars->fUsePerm = 1;
pPars->pLutLib = NULL;
}
// modify for global delay optimization
// modify for delay optimization
if ( pPars->nGateSize > 0 )
{
pPars->fTruth = 1;
@ -29924,7 +29931,7 @@ usage:
sprintf(LutSize, "library" );
else
sprintf(LutSize, "%d", pPars->nLutSize );
Abc_Print( -2, "usage: &if [-KCFAGRT num] [-DEW float] [-S str] [-qarlepmsdbgyojikfuztncvh]\n" );
Abc_Print( -2, "usage: &if [-KCFAGRT num] [-DEW float] [-S str] [-qarlepmsdbgxyojikfuztncvh]\n" );
Abc_Print( -2, "\t performs FPGA technology mapping of the network\n" );
Abc_Print( -2, "\t-K num : the number of LUT inputs (2 < num < %d) [default = %s]\n", IF_MAX_LUTSIZE+1, LutSize );
Abc_Print( -2, "\t-C num : the max number of priority cuts (0 < num < 2^12) [default = %d]\n", pPars->nCutsMax );
@ -29948,6 +29955,7 @@ usage:
Abc_Print( -2, "\t-d : toggles deriving local AIGs using bi-decomposition [default = %s]\n", pPars->fBidec? "yes": "no" );
Abc_Print( -2, "\t-b : toggles the use of one special feature [default = %s]\n", pPars->fUseBat? "yes": "no" );
Abc_Print( -2, "\t-g : toggles delay optimization by SOP balancing [default = %s]\n", pPars->fDelayOpt? "yes": "no" );
Abc_Print( -2, "\t-x : toggles delay optimization by DSD balancing [default = %s]\n", pPars->fDsdBalance? "yes": "no" );
Abc_Print( -2, "\t-y : toggles delay optimization with recorded library [default = %s]\n", pPars->fUserRecLib? "yes": "no" );
Abc_Print( -2, "\t-o : toggles using buffers to decouple combinational outputs [default = %s]\n", pPars->fUseBuffs? "yes": "no" );
Abc_Print( -2, "\t-j : toggles enabling additional check [default = %s]\n", pPars->fEnableCheck07? "yes": "no" );

61
src/base/abci/abcIf.c
View File

@ -356,7 +356,7 @@ Abc_Ntk_t * Abc_NtkFromIf( If_Man_t * pIfMan, Abc_Ntk_t * pNtk )
SeeAlso []
***********************************************************************/
Hop_Obj_t * Abc_NodeTruthToHopInt( Hop_Man_t * pMan, Vec_Wrd_t * vAnds, int nVars )
Hop_Obj_t * Abc_NodeFromSopBalanceInt( Hop_Man_t * pMan, Vec_Wrd_t * vAnds, int nVars )
{
Vec_Ptr_t * vResults;
Hop_Obj_t * pRes0, * pRes1, * pRes = NULL;
@ -387,24 +387,64 @@ Hop_Obj_t * Abc_NodeTruthToHopInt( Hop_Man_t * pMan, Vec_Wrd_t * vAnds, int nVar
Vec_PtrFree( vResults );
return Hop_NotCond( pRes, This.fCompl );
}
Hop_Obj_t * Abc_NodeFromSopBalance( Hop_Man_t * pMan, If_Man_t * p, If_Cut_t * pCut )
{
Hop_Obj_t * pResult;
Vec_Wrd_t * vArray;
vArray = If_CutDelaySopArray( p, pCut );
pResult = Abc_NodeFromSopBalanceInt( pMan, vArray, If_CutLeaveNum(pCut) );
// Vec_WrdFree( vArray );
return pResult;
}
/**Function*************************************************************
Synopsis [Creates the mapped network.]
Synopsis [Inserts the entry while sorting them by delay.]
Description [Assuming the copy field of the mapped nodes are NULL.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Hop_Obj_t * Abc_NodeTruthToHop( Hop_Man_t * pMan, If_Man_t * p, If_Cut_t * pCut )
Hop_Obj_t * Abc_NodeFromDsdBalanceInt( Hop_Man_t * pMan, Vec_Wrd_t * vAnds, int nVars )
{
Vec_Ptr_t * vResults;
Hop_Obj_t * pRes0, * pRes1, * pRes = NULL;
If_And_t This;
word Entry;
int i;
if ( Vec_WrdSize(vAnds) == 0 )
return Hop_ManConst0(pMan);
if ( Vec_WrdSize(vAnds) == 1 && Vec_WrdEntry(vAnds,0) == 0 )
return Hop_ManConst1(pMan);
vResults = Vec_PtrAlloc( Vec_WrdSize(vAnds) );
for ( i = 0; i < nVars; i++ )
Vec_PtrPush( vResults, Hop_IthVar(pMan, i) );
Vec_WrdForEachEntryStart( vAnds, Entry, i, nVars )
{
This = If_WrdToAnd( Entry );
pRes0 = Hop_NotCond( (Hop_Obj_t *)Vec_PtrEntry(vResults, This.iFan0), This.fCompl0 );
pRes1 = Hop_NotCond( (Hop_Obj_t *)Vec_PtrEntry(vResults, This.iFan1), This.fCompl1 );
pRes = Hop_And( pMan, pRes0, pRes1 );
Vec_PtrPush( vResults, pRes );
/*
printf( "fan0 = %c%d fan1 = %c%d Del = %d\n",
This.fCompl0? '-':'+', This.iFan0,
This.fCompl1? '-':'+', This.iFan1,
This.Delay );
*/
}
Vec_PtrFree( vResults );
return Hop_NotCond( pRes, This.fCompl );
}
Hop_Obj_t * Abc_NodeFromDsdBalance( Hop_Man_t * pMan, If_Man_t * p, If_Cut_t * pCut )
{
Hop_Obj_t * pResult;
Vec_Wrd_t * vArray;
vArray = If_CutDelaySopArray( p, pCut );
pResult = Abc_NodeTruthToHopInt( pMan, vArray, If_CutLeaveNum(pCut) );
pResult = Abc_NodeFromDsdBalanceInt( pMan, vArray, If_CutLeaveNum(pCut) );
// Vec_WrdFree( vArray );
return pResult;
}
@ -437,7 +477,7 @@ Abc_Obj_t * Abc_NodeFromIf_rec( Abc_Ntk_t * pNtkNew, If_Man_t * pIfMan, If_Obj_t
pCutBest = If_ObjCutBest( pIfObj );
// printf( "%d 0x%02X %d\n", pCutBest->nLeaves, 0xff & *If_CutTruth(pCutBest), pIfMan->pPars->pFuncCost(pCutBest) );
// if ( pIfMan->pPars->pLutLib && pIfMan->pPars->pLutLib->fVarPinDelays )
if ( !pIfMan->pPars->fUseTtPerm && !pIfMan->pPars->fDelayOpt && !pIfMan->pPars->pLutStruct && !pIfMan->pPars->fUserRecLib && !pIfMan->pPars->nGateSize )
if ( !pIfMan->pPars->fUseTtPerm && !pIfMan->pPars->fDelayOpt && !pIfMan->pPars->fDsdBalance && !pIfMan->pPars->pLutStruct && !pIfMan->pPars->fUserRecLib && !pIfMan->pPars->nGateSize )
If_CutRotatePins( pIfMan, pCutBest );
if ( pIfMan->pPars->fUseCnfs || pIfMan->pPars->fUseMv )
{
@ -486,8 +526,13 @@ Abc_Obj_t * Abc_NodeFromIf_rec( Abc_Ntk_t * pNtkNew, If_Man_t * pIfMan, If_Obj_t
}
else if ( pIfMan->pPars->fDelayOpt )
{
extern Hop_Obj_t * Abc_NodeTruthToHop( Hop_Man_t * pMan, If_Man_t * pIfMan, If_Cut_t * pCut );
pNodeNew->pData = Abc_NodeTruthToHop( (Hop_Man_t *)pNtkNew->pManFunc, pIfMan, pCutBest );
extern Hop_Obj_t * Abc_NodeFromSopBalance( Hop_Man_t * pMan, If_Man_t * pIfMan, If_Cut_t * pCut );
pNodeNew->pData = Abc_NodeFromSopBalance( (Hop_Man_t *)pNtkNew->pManFunc, pIfMan, pCutBest );
}
else if ( pIfMan->pPars->fDsdBalance )
{
extern Hop_Obj_t * Abc_NodeFromDsdBalance( Hop_Man_t * pMan, If_Man_t * pIfMan, If_Cut_t * pCut );
pNodeNew->pData = Abc_NodeFromDsdBalance( (Hop_Man_t *)pNtkNew->pManFunc, pIfMan, pCutBest );
}
else if ( pIfMan->pPars->fUserRecLib )
{

3
src/map/if/if.h
View File

@ -134,6 +134,7 @@ struct If_Par_t_
float WireDelay; // wire delay
// internal parameters
int fDelayOpt; // special delay optimization
int fDsdBalance; // special delay optimization
int fUserRecLib; // use recorded library
int fSkipCutFilter;// skip cut filter
int fAreaOnly; // area only mode
@ -546,6 +547,8 @@ extern int If_DsdManLutSize( If_DsdMan_t * p );
extern int If_DsdManSuppSize( If_DsdMan_t * p, int iDsd );
extern int If_DsdManCheckDec( If_DsdMan_t * p, int iDsd );
extern unsigned If_DsdManCheckXY( If_DsdMan_t * p, int iDsd, int LutSize, int fDerive, int fHighEffort, int fVerbose );
extern int If_DsdCutBalanceCost( If_Man_t * pIfMan, If_Cut_t * pCut );
extern int If_DsdCutBalance( void * pGia, If_Man_t * pIfMan, If_Cut_t * pCut, Vec_Int_t * vLeaves, int fHash );
/*=== ifLib.c =============================================================*/
extern If_LibLut_t * If_LibLutRead( char * FileName );
extern If_LibLut_t * If_LibLutDup( If_LibLut_t * p );

22
src/map/if/ifDsd.c
View File

@ -1838,6 +1838,28 @@ void If_DsdManTest()
Vec_IntFree( vSets );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int If_DsdCutBalanceCost( If_Man_t * pIfMan, If_Cut_t * pCut )
{
return 0;
}
int If_DsdCutBalance( void * pGia, If_Man_t * pIfMan, If_Cut_t * pCut, Vec_Int_t * vLeaves, int fHash )
{
Gia_Man_t * p = (Gia_Man_t *)pGia;
return 0;
}
/**Function*************************************************************
Synopsis []

48
src/map/if/ifMap.c
View File

@ -99,6 +99,7 @@ void If_ObjPerformMappingAnd( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPrep
If_Cut_t * pCut0R, * pCut1R;
int fFunc0R, fFunc1R;
int i, k, v, fChange;
int fSave0 = p->pPars->fDelayOpt || p->pPars->fDsdBalance || p->pPars->fUserRecLib;
assert( p->pPars->fSeqMap || !If_ObjIsAnd(pObj->pFanin0) || pObj->pFanin0->pCutSet->nCuts > 0 );
assert( p->pPars->fSeqMap || !If_ObjIsAnd(pObj->pFanin1) || pObj->pFanin1->pCutSet->nCuts > 0 );
@ -122,12 +123,14 @@ void If_ObjPerformMappingAnd( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPrep
if ( !fFirst )
{
// recompute the parameters of the best cut
if ( p->pPars->fUserRecLib )
pCut->Delay = If_CutDelayRecCost3(p, pCut, pObj);
else if(p->pPars->fDelayOpt)
pCut->Delay = If_CutDelaySopCost(p,pCut);
else if(p->pPars->nGateSize > 0)
pCut->Delay = If_CutDelaySop(p,pCut);
if ( p->pPars->fDelayOpt )
pCut->Delay = If_CutDelaySopCost( p, pCut );
else if ( p->pPars->fDsdBalance )
pCut->Delay = If_DsdCutBalanceCost( p, pCut );
else if ( p->pPars->fUserRecLib )
pCut->Delay = If_CutDelayRecCost3( p, pCut, pObj );
else if( p->pPars->nGateSize > 0 )
pCut->Delay = If_CutDelaySop( p, pCut );
else
pCut->Delay = If_CutDelay( p, pObj, pCut );
// assert( pCut->Delay <= pObj->Required + p->fEpsilon );
@ -184,7 +187,7 @@ void If_ObjPerformMappingAnd( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPrep
p->nCutsMerged++;
p->nCutsTotal++;
// check if this cut is contained in any of the available cuts
if ( !p->pPars->fSkipCutFilter && If_CutFilter( pCutSet, pCut, p->pPars->fUserRecLib || p->pPars->fDelayOpt ) )
if ( !p->pPars->fSkipCutFilter && If_CutFilter( pCutSet, pCut, fSave0 ) )
continue;
// compute the truth table
pCut->iCutFunc = -1;
@ -202,7 +205,7 @@ void If_ObjPerformMappingAnd( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPrep
fChange = If_CutComputeTruth( p, pCut, pCut0, pCut1, pObj->fCompl0, pObj->fCompl1 );
if ( p->pPars->fVerbose )
p->timeCache[4] += Abc_Clock() - clk;
if ( !p->pPars->fSkipCutFilter && fChange && If_CutFilter( pCutSet, pCut, p->pPars->fUserRecLib || p->pPars->fDelayOpt ) )
if ( !p->pPars->fSkipCutFilter && fChange && If_CutFilter( pCutSet, pCut, fSave0 ) )
continue;
if ( p->pPars->fUseDsd )
{
@ -276,19 +279,16 @@ void If_ObjPerformMappingAnd( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPrep
if ( pCut->Cost == IF_COST_MAX )
continue;
// check if the cut satisfies the required times
/// if ( p->pPars->pLutStruct )
/// pCut->Delay = If_CutDelayLutStruct( p, pCut, p->pPars->pLutStruct, p->pPars->WireDelay );
if ( p->pPars->fUserRecLib )
pCut->Delay = If_CutDelayRecCost3(p, pCut, pObj);
else if (p->pPars->fDelayOpt)
pCut->Delay = If_CutDelaySopCost(p, pCut);
else if(p->pPars->nGateSize > 0)
pCut->Delay = If_CutDelaySop(p,pCut);
else
if ( p->pPars->fDelayOpt )
pCut->Delay = If_CutDelaySopCost( p, pCut );
else if ( p->pPars->fDsdBalance )
pCut->Delay = If_DsdCutBalanceCost( p, pCut );
else if ( p->pPars->fUserRecLib )
pCut->Delay = If_CutDelayRecCost3( p, pCut, pObj );
else if( p->pPars->nGateSize > 0 )
pCut->Delay = If_CutDelaySop( p, pCut );
else
pCut->Delay = If_CutDelay( p, pObj, pCut );
//if ( pCut->Cost == IF_COST_MAX )
// continue;
// Abc_Print( 1, "%.2f ", pCut->Delay );
if ( Mode && pCut->Delay > pObj->Required + p->fEpsilon )
continue;
// compute area of the cut (this area may depend on the application specific cost)
@ -352,7 +352,7 @@ void If_ObjPerformMappingChoice( If_Man_t * p, If_Obj_t * pObj, int Mode, int fP
If_Set_t * pCutSet;
If_Obj_t * pTemp;
If_Cut_t * pCutTemp, * pCut;
int i;
int i, fSave0 = p->pPars->fDelayOpt || p->pPars->fDsdBalance || p->pPars->fUserRecLib;
assert( pObj->pEquiv != NULL );
// prepare
@ -369,8 +369,6 @@ void If_ObjPerformMappingChoice( If_Man_t * p, If_Obj_t * pObj, int Mode, int fP
// generate cuts
for ( pTemp = pObj->pEquiv; pTemp; pTemp = pTemp->pEquiv )
{
// assert( pTemp->nRefs == 0 );
// assert( p->pPars->fSeqMap || pTemp->pCutSet->nCuts > 0 ); // June 9, 2009
if ( pTemp->pCutSet->nCuts == 0 )
continue;
// go through the cuts of this node
@ -385,10 +383,10 @@ void If_ObjPerformMappingChoice( If_Man_t * p, If_Obj_t * pObj, int Mode, int fP
// copy the cut into storage
If_CutCopy( p, pCut, pCutTemp );
// check if this cut is contained in any of the available cuts
if ( If_CutFilter( pCutSet, pCut, p->pPars->fUserRecLib || p->pPars->fDelayOpt ) )
if ( If_CutFilter( pCutSet, pCut, fSave0 ) )
continue;
// check if the cut satisfies the required times
assert( pCut->Delay == If_CutDelay( p, pTemp, pCut ) );
// assert( pCut->Delay == If_CutDelay( p, pTemp, pCut ) );
if ( Mode && pCut->Delay > pObj->Required + p->fEpsilon )
continue;
// set the phase attribute