mirror of https://github.com/YosysHQ/abc.git
Trying to reduce delay degradation afer 'map' with user timing.
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@ -238,6 +238,7 @@ static int Abc_CommandUnmap ( Abc_Frame_t * pAbc, int argc, cha
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static int Abc_CommandAttach ( Abc_Frame_t * pAbc, int argc, char ** argv );
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static int Abc_CommandSuperChoice ( Abc_Frame_t * pAbc, int argc, char ** argv );
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static int Abc_CommandSuperChoiceLut ( Abc_Frame_t * pAbc, int argc, char ** argv );
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static int Abc_CommandTimeScale ( Abc_Frame_t * pAbc, int argc, char ** argv );
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//static int Abc_CommandFpga ( Abc_Frame_t * pAbc, int argc, char ** argv );
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//static int Abc_CommandFpgaFast ( Abc_Frame_t * pAbc, int argc, char ** argv );
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@ -846,6 +847,7 @@ void Abc_Init( Abc_Frame_t * pAbc )
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Cmd_CommandAdd( pAbc, "SC mapping", "attach", Abc_CommandAttach, 1 );
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Cmd_CommandAdd( pAbc, "SC mapping", "superc", Abc_CommandSuperChoice, 1 );
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Cmd_CommandAdd( pAbc, "SC mapping", "supercl", Abc_CommandSuperChoiceLut, 1 );
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Cmd_CommandAdd( pAbc, "SC mapping", "timescale", Abc_CommandTimeScale, 0 );
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// Cmd_CommandAdd( pAbc, "FPGA mapping", "fpga", Abc_CommandFpga, 1 );
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// Cmd_CommandAdd( pAbc, "FPGA mapping", "ffpga", Abc_CommandFpgaFast, 1 );
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@ -15016,6 +15018,76 @@ usage:
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return 1;
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Abc_CommandTimeScale( Abc_Frame_t * pAbc, int argc, char ** argv )
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{
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extern void Abc_NtkTimeScale( Abc_Ntk_t * pNtk, float Scale );
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Abc_Ntk_t * pNtk;
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float nTimeScale;
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int c, fVerbose;
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pNtk = Abc_FrameReadNtk(pAbc);
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// set defaults
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nTimeScale = (float)0.01;
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fVerbose = 0;
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Extra_UtilGetoptReset();
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while ( ( c = Extra_UtilGetopt( argc, argv, "Th" ) ) != EOF )
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{
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switch ( c )
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{
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case 'T':
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if ( globalUtilOptind >= argc )
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{
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Abc_Print( -1, "Command line switch \"-T\" should be followed by a positive integer.\n" );
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goto usage;
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}
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nTimeScale = atof(argv[globalUtilOptind]);
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globalUtilOptind++;
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if ( nTimeScale < 0 )
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goto usage;
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break;
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case 'v':
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fVerbose ^= 1;
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break;
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case 'h':
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goto usage;
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default:
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goto usage;
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}
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}
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if ( pNtk == NULL )
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{
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Abc_Print( -1, "Empty network.\n" );
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return 1;
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}
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if ( pNtk->pManTime == NULL )
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{
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Abc_Print( -1, "Timing manager is not defined.\n" );
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return 1;
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}
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Abc_NtkTimeScale( pNtk, nTimeScale );
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return 0;
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usage:
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Abc_Print( -2, "usage: timescale [-T float] [-vh]\n" );
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Abc_Print( -2, "\t scales timing information of the current network\n" );
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Abc_Print( -2, "\t-T float : multiplicative factor [default = %f]\n", nTimeScale );
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Abc_Print( -2, "\t-v : toggles verbose output [default = %s]\n", fVerbose? "yes": "no" );
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Abc_Print( -2, "\t-h : print the command usage\n");
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return 1;
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}
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/**Function*************************************************************
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Synopsis []
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@ -290,6 +290,7 @@ Aig_Man_t * Abc_NtkToDar( Abc_Ntk_t * pNtk, int fExors, int fRegisters )
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// initialize logic level of the CIs
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((Aig_Obj_t *)pObj->pCopy)->Level = pObj->Level;
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}
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// complement the 1-values registers
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if ( fRegisters ) {
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Abc_NtkForEachLatch( pNtk, pObj, i )
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@ -114,6 +114,16 @@ Abc_Ntk_t * Abc_NtkIf( Abc_Ntk_t * pNtk, If_Par_t * pPars )
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pPars->pTimesArr = Abc_NtkGetCiArrivalFloats(pNtk);
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pPars->pTimesReq = Abc_NtkGetCoRequiredFloats(pNtk);
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// update timing info to reflect logic level
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if ( (pPars->fDelayOpt || pPars->fDsdBalance || pPars->fUserRecLib) && pNtk->AndGateDelay != 0.0 )
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{
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int c;
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for ( c = 0; c < Abc_NtkCiNum(pNtk); c++ )
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pPars->pTimesArr[c] /= pNtk->AndGateDelay;
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for ( c = 0; c < Abc_NtkCoNum(pNtk); c++ )
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pPars->pTimesReq[c] /= pNtk->AndGateDelay;
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}
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// set the latch paths
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if ( pPars->fLatchPaths && pPars->pTimesArr )
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{
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@ -363,6 +363,54 @@ void Abc_NtkTimeInitialize( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkOld )
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}
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}
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/**Function*************************************************************
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Synopsis [Finalizes the timing manager after setting arr/req times.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Abc_NtkTimeScale( Abc_Ntk_t * pNtk, float Scale )
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{
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Abc_Obj_t * pObj;
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Abc_Time_t ** ppTimes, * pTime;
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int i;
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if ( pNtk->pManTime == NULL )
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return;
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// arrival
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pNtk->pManTime->tArrDef.Fall *= Scale;
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pNtk->pManTime->tArrDef.Rise *= Scale;
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// departure
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if ( pNtk->pManTime->tReqDef.Fall != ABC_INFINITY )
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pNtk->pManTime->tReqDef.Fall *= Scale;
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if ( pNtk->pManTime->tReqDef.Rise != ABC_INFINITY )
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pNtk->pManTime->tReqDef.Rise *= Scale;
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// set the default timing
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ppTimes = (Abc_Time_t **)pNtk->pManTime->vArrs->pArray;
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Abc_NtkForEachCi( pNtk, pObj, i )
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{
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pTime = ppTimes[pObj->Id];
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if ( Abc_MaxFloat(pTime->Fall, pTime->Rise) != -ABC_INFINITY )
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continue;
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pTime->Fall *= Scale;
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pTime->Rise *= Scale;
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}
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// set the default timing
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ppTimes = (Abc_Time_t **)pNtk->pManTime->vReqs->pArray;
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Abc_NtkForEachCo( pNtk, pObj, i )
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{
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pTime = ppTimes[pObj->Id];
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if ( Abc_MaxFloat(pTime->Fall, pTime->Rise) != ABC_INFINITY )
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continue;
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pTime->Fall *= Scale;
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pTime->Rise *= Scale;
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}
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}
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/**Function*************************************************************
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Synopsis [Prepares the timing manager for delay trace.]
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