mirror of https://github.com/YosysHQ/abc.git
Adding option 'gen -b' to generate signed Booth multipliers.
This commit is contained in:
Alan Mishchenko
parent
395614a4dd
commit
3a1705e8bb
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@ -12406,6 +12406,7 @@ int Abc_CommandGen( Abc_Frame_t * pAbc, int argc, char ** argv )
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int fSorter;
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int fMesh;
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int fMulti;
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int fBooth;
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int fFpga;
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int fOneHot;
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int fRandom;
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@ -12416,6 +12417,7 @@ int Abc_CommandGen( Abc_Frame_t * pAbc, int argc, char ** argv )
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extern void Abc_GenSorter( char * pFileName, int nVars );
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extern void Abc_GenMesh( char * pFileName, int nVars );
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extern void Abc_GenMulti( char * pFileName, int nVars );
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extern void Abc_GenBooth( char * pFileName, int nVars );
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extern void Abc_GenFpga( char * pFileName, int nLutSize, int nLuts, int nVars );
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extern void Abc_GenOneHot( char * pFileName, int nVars );
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extern void Abc_GenRandom( char * pFileName, int nPis );
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@ -12429,12 +12431,13 @@ int Abc_CommandGen( Abc_Frame_t * pAbc, int argc, char ** argv )
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fSorter = 0;
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fMesh = 0;
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fMulti = 0;
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fBooth = 0;
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fFpga = 0;
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fOneHot = 0;
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fRandom = 0;
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fVerbose = 0;
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Extra_UtilGetoptReset();
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while ( ( c = Extra_UtilGetopt( argc, argv, "NAKLabsemftrvh" ) ) != EOF )
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while ( ( c = Extra_UtilGetopt( argc, argv, "NAKLatsembfnrvh" ) ) != EOF )
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{
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switch ( c )
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{
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@ -12485,7 +12488,7 @@ int Abc_CommandGen( Abc_Frame_t * pAbc, int argc, char ** argv )
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case 'a':
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fAdder ^= 1;
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break;
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case 'b':
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case 't':
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fAdderTree ^= 1;
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break;
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case 's':
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@ -12497,10 +12500,13 @@ int Abc_CommandGen( Abc_Frame_t * pAbc, int argc, char ** argv )
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case 'm':
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fMulti ^= 1;
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break;
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case 'b':
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fBooth ^= 1;
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break;
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case 'f':
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fFpga ^= 1;
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break;
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case 't':
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case 'n':
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fOneHot ^= 1;
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break;
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case 'r':
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@ -12535,6 +12541,8 @@ int Abc_CommandGen( Abc_Frame_t * pAbc, int argc, char ** argv )
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Abc_GenMesh( FileName, nVars );
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else if ( fMulti )
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Abc_GenMulti( FileName, nVars );
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else if ( fBooth )
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Abc_GenBooth( FileName, nVars );
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else if ( fFpga )
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Abc_GenFpga( FileName, nLutSize, nLuts, nVars );
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// Abc_GenFpga( FileName, 2, 2, 3 );
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@ -12562,19 +12570,20 @@ int Abc_CommandGen( Abc_Frame_t * pAbc, int argc, char ** argv )
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return 0;
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usage:
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Abc_Print( -2, "usage: gen [-NAKL num] [-asemftrvh] <file>\n" );
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Abc_Print( -2, "usage: gen [-NAKL num] [-atsembfnrvh] <file>\n" );
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Abc_Print( -2, "\t generates simple circuits\n" );
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Abc_Print( -2, "\t-N num : the number of variables [default = %d]\n", nVars );
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Abc_Print( -2, "\t-A num : the number of agruments (for adder tree) [default = %d]\n", nArgs );
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Abc_Print( -2, "\t-K num : the LUT size (to be used with switch -f) [default = %d]\n", nLutSize );
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Abc_Print( -2, "\t-L num : the LUT count (to be used with switch -f) [default = %d]\n", nLuts );
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Abc_Print( -2, "\t-a : generate ripple-carry adder [default = %s]\n", fAdder? "yes": "no" );
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Abc_Print( -2, "\t-b : generate an adder tree [default = %s]\n", fAdderTree? "yes": "no" );
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Abc_Print( -2, "\t-t : generate an adder tree [default = %s]\n", fAdderTree? "yes": "no" );
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Abc_Print( -2, "\t-s : generate a sorter [default = %s]\n", fSorter? "yes": "no" );
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Abc_Print( -2, "\t-e : generate a mesh [default = %s]\n", fMesh? "yes": "no" );
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Abc_Print( -2, "\t-m : generate a multiplier [default = %s]\n", fMulti? "yes": "no" );
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Abc_Print( -2, "\t-b : generate a signed Booth multiplier [default = %s]\n", fBooth? "yes": "no" );
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Abc_Print( -2, "\t-f : generate a LUT FPGA structure [default = %s]\n", fFpga? "yes": "no" );
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Abc_Print( -2, "\t-t : generate one-hotness conditions [default = %s]\n", fOneHot? "yes": "no" );
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Abc_Print( -2, "\t-n : generate one-hotness conditions [default = %s]\n", fOneHot? "yes": "no" );
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Abc_Print( -2, "\t-r : generate random single-output function [default = %s]\n", fRandom? "yes": "no" );
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Abc_Print( -2, "\t-v : prints verbose information [default = %s]\n", fVerbose? "yes": "no" );
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Abc_Print( -2, "\t-h : print the command usage\n");
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@ -19,6 +19,7 @@
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***********************************************************************/
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#include "base/abc/abc.h"
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#include "aig/miniaig/miniaig.h"
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ABC_NAMESPACE_IMPL_START
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@ -870,6 +871,276 @@ void Abc_GenAdderTree( char * pFileName, int nArgs, int nBits )
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fclose( pFile );
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}
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/**Function*************************************************************
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Synopsis [Generating signed Booth multiplier.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Abc_GenSignedBoothPP( Gia_Man_t * p, int a, int b, int c, int d, int e )
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{
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/*
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abc> lutexact -I 5 -N 7 -g F335ACC0
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05 = 4'b0110( d e )
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06 = 4'b0110( c d )
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07 = 4'b0100( a 06 )
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08 = 4'b1000( b 06 )
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09 = 4'b0100( 05 07 )
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10 = 4'b0110( 08 09 )
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11 = 4'b0110( d 10 )
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*/
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int n05 = Gia_ManHashXor( p, d, e );
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int n06 = Gia_ManHashXor( p, c, d );
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int n07 = Gia_ManHashAnd( p, a, Abc_LitNot(n06) );
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int n08 = Gia_ManHashAnd( p, b, n06 );
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int n09 = Gia_ManHashAnd( p, n05, Abc_LitNot(n07) );
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int n10 = Gia_ManHashXor( p, n08, n09 );
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int n11 = Gia_ManHashXor( p, d, n10 );
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return n11;
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}
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Gia_Man_t * Abc_GenSignedBoothPPTest( int nArgA, int nArgB )
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{
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Gia_Man_t * pNew; int i, iLit;
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pNew = Gia_ManStart( 1000 );
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pNew->pName = Abc_UtilStrsav( "booth" );
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for ( i = 0; i < 5; i++ )
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Gia_ManAppendCi(pNew);
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iLit = Abc_GenSignedBoothPP( pNew, 2, 4, 6, 8, 10 );
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Gia_ManAppendCo(pNew, iLit);
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return pNew;
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}
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/*
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// parametrized implementation of signed Booth multiplier
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module booth #(
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parameter N = 4 // bit-width of input a
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,parameter M = 4 // bit-width of input b
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)(
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input [N-1:0] a // input data
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,input [M-1:0] b // input data
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,output [N+M-1:0] z // output data
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);
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localparam TT = 32'hF335ACC0;
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localparam W = N+M+1;
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localparam L = (M+1)/2;
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wire [W-1:0] data1[L:0];
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wire [W-1:0] data2[L:0];
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assign data2[0] = data1[0];
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assign z = data2[L][N+M-1:0];
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wire [N+1:0] a2 = {a[N-1], a, 1'b0};
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wire [M+1:0] b2 = {b[M-1], b, 1'b0};
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genvar j;
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generate
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for ( j = 0; j < W; j = j + 1 ) begin : J
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assign data1[0][j] = (j%2 == 0 && j/2 < L) ? b2[j+2] : 1'b0;
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end
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endgenerate
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genvar k, i0, i1, i2;
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generate
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for ( k = 0; k < 2*L; k = k + 2 ) begin : K
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for ( i0 = 0; i0 < k; i0 = i0 + 1 ) begin : I0
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assign data1[k/2+1][i0] = 1'b0;
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end
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for ( i1 = 0; i1 <= N; i1 = i1 + 1 ) begin : I1
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wire [4:0] in = {b2[k+2], b2[k+1], b2[k], a2[i1+1], a2[i1]};
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assign data1[k/2+1][k+i1] = (k > 0 && i1 == N) ? ~TT[in] : TT[in];
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end
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assign data1[k/2+1][k+N+1] = k > 0 ? 1'b1 : data1[k/2+1][k+N];
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for ( i2 = k+N+2; i2 < W; i2 = i2 + 1 ) begin : I2
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assign data1[k/2+1][i2] = (k > 0 || i2 > k+N+2)? 1'b0 : ~data1[k/2+1][k+N];
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end
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assign data2[k/2+1] = data2[k/2] + data1[k/2+1];
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end
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endgenerate
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endmodule
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*/
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Gia_Man_t * Abc_GenSignedBooth( int nArgN, int nArgM )
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{
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int nWidth = nArgN + nArgM + 1;
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int Length = (nArgM + 1) / 2;
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int i, k, iLit;
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Vec_Int_t * vPPs = Vec_IntAlloc( nWidth * (Length + 1) );
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Vec_Int_t * vArgN = Vec_IntAlloc( nArgN + 2 );
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Vec_Int_t * vArgM = Vec_IntAlloc( nArgM + 2 );
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int * pArgN = Vec_IntArray( vArgN );
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int * pArgM = Vec_IntArray( vArgM );
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Gia_Man_t * pTemp, * pNew;
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pNew = Gia_ManStart( 1000 );
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pNew->pName = Abc_UtilStrsav( "booth" );
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Vec_IntPush( vArgN, 0 );
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for ( i = 0; i < nArgN; i++ )
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Vec_IntPush( vArgN, Gia_ManAppendCi(pNew) );
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Vec_IntPush( vArgN, Vec_IntEntryLast(vArgN) );
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Vec_IntPush( vArgM, 0 );
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for ( i = 0; i < nArgM; i++ )
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Vec_IntPush( vArgM, Gia_ManAppendCi(pNew) );
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Vec_IntPush( vArgM, Vec_IntEntryLast(vArgM) );
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for ( i = 0; i < nWidth; i++ )
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Vec_IntPush( vPPs, (i%2 == 0 && i/2 < Length) ? pArgM[i+2] : 0 );
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Gia_ManHashAlloc( pNew );
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for ( k = 0; k < 2*Length; k += 2 )
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{
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for ( i = 0; i < k; i++ )
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Vec_IntPush( vPPs, 0 );
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for ( i = 0; i <= nArgN; i++ )
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{
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iLit = Abc_GenSignedBoothPP( pNew, pArgN[i], pArgN[i+1], pArgM[k], pArgM[k+1], pArgM[k+2] );
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Vec_IntPush( vPPs, Abc_LitNotCond( iLit, k > 0 && i == nArgN ) );
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}
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iLit = Vec_IntEntryLast(vPPs);
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Vec_IntPush( vPPs, k > 0 ? 1 : iLit );
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for ( i = k+nArgN+2; i < nWidth; i++ )
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Vec_IntPush( vPPs, (k > 0 || i > k+nArgN+2) ? 0 : Abc_LitNot(iLit) );
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}
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Gia_ManHashStop( pNew );
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for ( k = 0; k <= Length; k++ )
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for ( i = 0; i < nArgN+nArgM; i++ )
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Gia_ManAppendCo( pNew, Vec_IntEntry(vPPs, k*(nArgN+nArgM+1) + i) );
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Vec_IntFree( vPPs );
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Vec_IntFree( vArgN );
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Vec_IntFree( vArgM );
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pNew = Gia_ManCleanup( pTemp = pNew );
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Gia_ManStop( pTemp );
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return pNew;
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}
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Mini_Aig_t * Abc_GenSignedBoothMini( int nArgN, int nArgM )
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{
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extern Mini_Aig_t * Gia_ManToMiniAig( Gia_Man_t * pGia );
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Gia_Man_t * pGia = Abc_GenSignedBooth( nArgN, nArgM );
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Mini_Aig_t * pMini = Gia_ManToMiniAig( pGia );
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Gia_ManStop( pGia );
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return pMini;
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Abc_WriteBoothPartialProducts( FILE * pFile, int nVars )
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{
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Mini_Aig_t * p = Abc_GenSignedBoothMini( nVars, nVars );
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int i, nNodes = Mini_AigNodeNum(p);
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int nDigits = Abc_Base10Log( nVars );
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int nDigits2 = Abc_Base10Log( 2*nVars );
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int nDigits3 = Abc_Base10Log( nNodes );
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int nOut = 0;
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fprintf( pFile, ".names pp%0*d\n", nDigits3, 0 );
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for ( i = 1; i < nNodes; i++ )
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{
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if ( Mini_AigNodeIsPi( p, i ) )
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{
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if ( i > 0 && i <= nVars )
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fprintf( pFile, ".names a%0*d pp%0*d\n1 1\n", nDigits, i-1, nDigits3, i );
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else if ( i > nVars && i <= 2*nVars )
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fprintf( pFile, ".names b%0*d pp%0*d\n1 1\n", nDigits, i-1-nVars, nDigits3, i );
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else assert( 0 );
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}
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else if ( Mini_AigNodeIsPo( p, i ) )
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{
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int Lit = Mini_AigNodeFanin0( p, i );
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fprintf( pFile, ".names pp%0*d y%0*d_%0*d\n%d 1\n", nDigits3, Abc_Lit2Var(Lit), nDigits, nOut/(2*nVars), nDigits2, nOut%(2*nVars), !Abc_LitIsCompl(Lit) );
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nOut++;
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}
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else if ( Mini_AigNodeIsAnd( p, i ) )
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{
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int Lit0 = Mini_AigNodeFanin0( p, i );
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int Lit1 = Mini_AigNodeFanin1( p, i );
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fprintf( pFile, ".names pp%0*d pp%0*d pp%0*d\n%d%d 1\n",
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nDigits3, Abc_Lit2Var(Lit0), nDigits3, Abc_Lit2Var(Lit1), nDigits3, i, !Abc_LitIsCompl(Lit0), !Abc_LitIsCompl(Lit1) );
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}
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else assert( 0 );
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}
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Mini_AigStop( p );
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}
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void Abc_WriteBooth( FILE * pFile, int nVars )
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{
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int i, k, nDigits = Abc_Base10Log( nVars ), nDigits2 = Abc_Base10Log( 2*nVars );
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int Length = 1+(nVars + 1)/2;
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assert( nVars > 0 );
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fprintf( pFile, ".model Multi%d\n", nVars );
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fprintf( pFile, ".inputs" );
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for ( i = 0; i < nVars; i++ )
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fprintf( pFile, " a%0*d", nDigits, i );
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for ( i = 0; i < nVars; i++ )
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fprintf( pFile, " b%0*d", nDigits, i );
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fprintf( pFile, "\n" );
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fprintf( pFile, ".outputs" );
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for ( i = 0; i < 2*nVars; i++ )
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fprintf( pFile, " m%0*d", nDigits2, i );
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fprintf( pFile, "\n" );
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Abc_WriteBoothPartialProducts( pFile, nVars );
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for ( i = 0; i < 2*nVars; i++ )
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fprintf( pFile, ".names x%0*d_%0*d\n", nDigits, 0, nDigits2, i );
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for ( k = 0; k < Length; k++ )
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{
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fprintf( pFile, ".subckt ADD%d", 2*nVars );
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for ( i = 0; i < 2*nVars; i++ )
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fprintf( pFile, " a%0*d=x%0*d_%0*d", nDigits2, i, nDigits, k, nDigits2, i );
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for ( i = 0; i < 2*nVars; i++ )
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fprintf( pFile, " b%0*d=y%0*d_%0*d", nDigits2, i, nDigits, k, nDigits2, i );
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for ( i = 0; i <= 2*nVars; i++ )
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fprintf( pFile, " s%0*d=x%0*d_%0*d", nDigits2, i, nDigits, k+1, nDigits2, i );
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fprintf( pFile, "\n" );
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}
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for ( i = 0; i < 2 * nVars; i++ )
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fprintf( pFile, ".names x%0*d_%0*d m%0*d\n1 1\n", nDigits, k, nDigits2, i, nDigits2, i );
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fprintf( pFile, ".end\n" );
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fprintf( pFile, "\n" );
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Abc_WriteAdder( pFile, 2*nVars );
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}
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void Abc_GenBooth( char * pFileName, int nVars )
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{
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FILE * pFile;
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assert( nVars > 0 );
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pFile = fopen( pFileName, "w" );
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fprintf( pFile, "# %d-bit signed Booth multiplier generated by ABC on %s\n", nVars, Extra_TimeStamp() );
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Abc_WriteBooth( pFile, nVars );
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fclose( pFile );
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}
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////////////////////////////////////////////////////////////////////////
|
||||
/// END OF FILE ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
|
|
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Reference in New Issue