mirror of https://github.com/YosysHQ/abc.git
Version abc51205
This commit is contained in:
Alan Mishchenko
parent
a6086f0881
commit
37f19d8dfb
657
abc.plg
657
abc.plg
|
|
@ -6,327 +6,13 @@
|
|||
--------------------Configuration: abc - Win32 Release--------------------
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||||
</h3>
|
||||
<h3>Command Lines</h3>
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP7A.tmp" with contents
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP20D.tmp" with contents
|
||||
[
|
||||
/nologo /ML /W3 /GX /O2 /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mapp" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D "HAVE_ASSERT_H" /FR"Release/" /Fp"Release/abc.pch" /YX /Fo"Release/" /Fd"Release/" /FD /c
|
||||
"C:\_projects\abc\src\base\abc\abcAig.c"
|
||||
"C:\_projects\abc\src\base\abc\abcCheck.c"
|
||||
"C:\_projects\abc\src\base\abc\abcDfs.c"
|
||||
"C:\_projects\abc\src\base\abc\abcFanio.c"
|
||||
"C:\_projects\abc\src\base\abc\abcFunc.c"
|
||||
"C:\_projects\abc\src\base\abc\abcLatch.c"
|
||||
"C:\_projects\abc\src\base\abc\abcMinBase.c"
|
||||
"C:\_projects\abc\src\base\abc\abcNames.c"
|
||||
"C:\_projects\abc\src\base\abc\abcNetlist.c"
|
||||
"C:\_projects\abc\src\base\abc\abcNtk.c"
|
||||
"C:\_projects\abc\src\base\abc\abcObj.c"
|
||||
"C:\_projects\abc\src\base\abc\abcRefs.c"
|
||||
"C:\_projects\abc\src\base\abc\abcShow.c"
|
||||
"C:\_projects\abc\src\base\abc\abcSop.c"
|
||||
"C:\_projects\abc\src\base\abc\abcUtil.c"
|
||||
"C:\_projects\abc\src\base\abci\abc.c"
|
||||
"C:\_projects\abc\src\base\abci\abcAttach.c"
|
||||
"C:\_projects\abc\src\base\abci\abcBalance.c"
|
||||
"C:\_projects\abc\src\base\abci\abcCollapse.c"
|
||||
"C:\_projects\abc\src\base\abci\abcCut.c"
|
||||
"C:\_projects\abc\src\base\abci\abcDsd.c"
|
||||
"C:\_projects\abc\src\base\abci\abcFpga.c"
|
||||
"C:\_projects\abc\src\base\abci\abcFraig.c"
|
||||
"C:\_projects\abc\src\base\abci\abcFxu.c"
|
||||
"C:\_projects\abc\src\base\abci\abcMap.c"
|
||||
"C:\_projects\abc\src\base\abci\abcMiter.c"
|
||||
"C:\_projects\abc\src\base\abci\abcNtbdd.c"
|
||||
"C:\_projects\abc\src\base\abci\abcPga.c"
|
||||
"C:\_projects\abc\src\base\abci\abcPrint.c"
|
||||
"C:\_projects\abc\src\base\abci\abcReconv.c"
|
||||
"C:\_projects\abc\src\base\abci\abcRefactor.c"
|
||||
"C:\_projects\abc\src\base\abci\abcRenode.c"
|
||||
"C:\_projects\abc\src\base\abci\abcRewrite.c"
|
||||
"C:\_projects\abc\src\base\abci\abcSat.c"
|
||||
"C:\_projects\abc\src\base\abci\abcStrash.c"
|
||||
"C:\_projects\abc\src\base\abci\abcSweep.c"
|
||||
"C:\_projects\abc\src\base\abci\abcSymm.c"
|
||||
"C:\_projects\abc\src\base\abci\abcTiming.c"
|
||||
"C:\_projects\abc\src\base\abci\abcUnreach.c"
|
||||
"C:\_projects\abc\src\base\abci\abcVanEijk.c"
|
||||
"C:\_projects\abc\src\base\abci\abcVanImp.c"
|
||||
"C:\_projects\abc\src\base\abci\abcVerify.c"
|
||||
"C:\_projects\abc\src\base\seq\seqAigCore.c"
|
||||
"C:\_projects\abc\src\base\seq\seqAigIter.c"
|
||||
"C:\_projects\abc\src\base\seq\seqCreate.c"
|
||||
"C:\_projects\abc\src\base\seq\seqFpgaCore.c"
|
||||
"C:\_projects\abc\src\base\seq\seqFpgaIter.c"
|
||||
"C:\_projects\abc\src\base\seq\seqLatch.c"
|
||||
"C:\_projects\abc\src\base\seq\seqMan.c"
|
||||
"C:\_projects\abc\src\base\seq\seqMapCore.c"
|
||||
"C:\_projects\abc\src\base\seq\seqMapIter.c"
|
||||
"C:\_projects\abc\src\base\seq\seqRetCore.c"
|
||||
"C:\_projects\abc\src\base\seq\seqRetIter.c"
|
||||
"C:\_projects\abc\src\base\seq\seqShare.c"
|
||||
"C:\_projects\abc\src\base\seq\seqUtil.c"
|
||||
"C:\_projects\abc\src\base\cmd\cmd.c"
|
||||
"C:\_projects\abc\src\base\cmd\cmdAlias.c"
|
||||
"C:\_projects\abc\src\base\cmd\cmdApi.c"
|
||||
"C:\_projects\abc\src\base\cmd\cmdFlag.c"
|
||||
"C:\_projects\abc\src\base\cmd\cmdHist.c"
|
||||
"C:\_projects\abc\src\base\cmd\cmdUtils.c"
|
||||
"C:\_projects\abc\src\base\io\io.c"
|
||||
"C:\_projects\abc\src\base\io\ioRead.c"
|
||||
"C:\_projects\abc\src\base\io\ioReadBaf.c"
|
||||
"C:\_projects\abc\src\base\io\ioReadBench.c"
|
||||
"C:\_projects\abc\src\base\io\ioReadBlif.c"
|
||||
"C:\_projects\abc\src\base\io\ioReadEdif.c"
|
||||
"C:\_projects\abc\src\base\io\ioReadEqn.c"
|
||||
"C:\_projects\abc\src\base\io\ioReadPla.c"
|
||||
"C:\_projects\abc\src\base\io\ioReadVerilog.c"
|
||||
"C:\_projects\abc\src\base\io\ioUtil.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteBaf.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteBench.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteBlif.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteCnf.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteDot.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteEqn.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteGml.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteList.c"
|
||||
"C:\_projects\abc\src\base\io\ioWritePla.c"
|
||||
"C:\_projects\abc\src\base\main\libSupport.c"
|
||||
"C:\_projects\abc\src\base\main\main.c"
|
||||
"C:\_projects\abc\src\base\main\mainFrame.c"
|
||||
"C:\_projects\abc\src\base\main\mainInit.c"
|
||||
"C:\_projects\abc\src\base\main\mainUtils.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddAddAbs.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddAddApply.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddAddFind.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddAddInv.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddAddIte.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddAddNeg.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddAddWalsh.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddAndAbs.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddAnneal.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddApa.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddAPI.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddApprox.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddBddAbs.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddBddCorr.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddBddIte.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddBridge.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddCache.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddCheck.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddClip.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddCof.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddCompose.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddDecomp.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddEssent.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddExact.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddExport.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddGenCof.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddGenetic.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddGroup.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddHarwell.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddInit.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddInteract.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddLCache.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddLevelQ.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddLinear.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddLiteral.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddMatMult.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddPriority.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddRead.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddRef.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddReorder.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddSat.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddSign.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddSolve.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddSplit.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddSubsetHB.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddSubsetSP.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddSymmetry.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddTable.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddUtil.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddWindow.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddZddCount.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddZddFuncs.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddZddGroup.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddZddIsop.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddZddLin.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddZddMisc.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddZddPort.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddZddReord.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddZddSetop.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddZddSymm.c"
|
||||
"C:\_projects\abc\src\bdd\cudd\cuddZddUtil.c"
|
||||
"C:\_projects\abc\src\bdd\epd\epd.c"
|
||||
"C:\_projects\abc\src\bdd\mtr\mtrBasic.c"
|
||||
"C:\_projects\abc\src\bdd\mtr\mtrGroup.c"
|
||||
"C:\_projects\abc\src\bdd\parse\parseCore.c"
|
||||
"C:\_projects\abc\src\bdd\parse\parseStack.c"
|
||||
"C:\_projects\abc\src\bdd\dsd\dsdApi.c"
|
||||
"C:\_projects\abc\src\bdd\dsd\dsdCheck.c"
|
||||
"C:\_projects\abc\src\bdd\dsd\dsdLocal.c"
|
||||
"C:\_projects\abc\src\bdd\dsd\dsdMan.c"
|
||||
"C:\_projects\abc\src\bdd\dsd\dsdProc.c"
|
||||
"C:\_projects\abc\src\bdd\dsd\dsdTree.c"
|
||||
"C:\_projects\abc\src\bdd\reo\reoApi.c"
|
||||
"C:\_projects\abc\src\bdd\reo\reoCore.c"
|
||||
"C:\_projects\abc\src\bdd\reo\reoProfile.c"
|
||||
"C:\_projects\abc\src\bdd\reo\reoSift.c"
|
||||
"C:\_projects\abc\src\bdd\reo\reoSwap.c"
|
||||
"C:\_projects\abc\src\bdd\reo\reoTest.c"
|
||||
"C:\_projects\abc\src\bdd\reo\reoTransfer.c"
|
||||
"C:\_projects\abc\src\bdd\reo\reoUnits.c"
|
||||
"C:\_projects\abc\src\sat\asat\added.c"
|
||||
"C:\_projects\abc\src\sat\asat\solver.c"
|
||||
"C:\_projects\abc\src\sat\msat\msatActivity.c"
|
||||
"C:\_projects\abc\src\sat\msat\msatClause.c"
|
||||
"C:\_projects\abc\src\sat\msat\msatClauseVec.c"
|
||||
"C:\_projects\abc\src\sat\msat\msatMem.c"
|
||||
"C:\_projects\abc\src\sat\msat\msatOrderH.c"
|
||||
"C:\_projects\abc\src\sat\msat\msatQueue.c"
|
||||
"C:\_projects\abc\src\sat\msat\msatRead.c"
|
||||
"C:\_projects\abc\src\sat\msat\msatSolverApi.c"
|
||||
"C:\_projects\abc\src\sat\msat\msatSolverCore.c"
|
||||
"C:\_projects\abc\src\sat\msat\msatSolverIo.c"
|
||||
"C:\_projects\abc\src\sat\msat\msatSolverSearch.c"
|
||||
"C:\_projects\abc\src\sat\msat\msatSort.c"
|
||||
"C:\_projects\abc\src\sat\msat\msatVec.c"
|
||||
"C:\_projects\abc\src\sat\fraig\fraigApi.c"
|
||||
"C:\_projects\abc\src\sat\fraig\fraigCanon.c"
|
||||
"C:\_projects\abc\src\sat\fraig\fraigFanout.c"
|
||||
"C:\_projects\abc\src\sat\fraig\fraigFeed.c"
|
||||
"C:\_projects\abc\src\sat\fraig\fraigMan.c"
|
||||
"C:\_projects\abc\src\sat\fraig\fraigMem.c"
|
||||
"C:\_projects\abc\src\sat\fraig\fraigNode.c"
|
||||
"C:\_projects\abc\src\sat\fraig\fraigPrime.c"
|
||||
"C:\_projects\abc\src\sat\fraig\fraigSat.c"
|
||||
"C:\_projects\abc\src\sat\fraig\fraigTable.c"
|
||||
"C:\_projects\abc\src\sat\fraig\fraigUtil.c"
|
||||
"C:\_projects\abc\src\sat\fraig\fraigVec.c"
|
||||
"C:\_projects\abc\src\sat\csat\csat_apis.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxu.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuCreate.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuHeapD.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuHeapS.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuList.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuMatrix.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuPair.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuPrint.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuReduce.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuSelect.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuSingle.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuUpdate.c"
|
||||
"C:\_projects\abc\src\opt\rwr\rwrDec.c"
|
||||
"C:\_projects\abc\src\opt\rwr\rwrEva.c"
|
||||
"C:\_projects\abc\src\opt\rwr\rwrExp.c"
|
||||
"C:\_projects\abc\src\opt\rwr\rwrLib.c"
|
||||
"C:\_projects\abc\src\opt\rwr\rwrMan.c"
|
||||
"C:\_projects\abc\src\opt\rwr\rwrPrint.c"
|
||||
"C:\_projects\abc\src\opt\rwr\rwrUtil.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutApi.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutCut.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutMan.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutMerge.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutNode.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutOracle.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutSeq.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutTruth.c"
|
||||
"C:\_projects\abc\src\opt\dec\decAbc.c"
|
||||
"C:\_projects\abc\src\opt\dec\decFactor.c"
|
||||
"C:\_projects\abc\src\opt\dec\decMan.c"
|
||||
"C:\_projects\abc\src\opt\dec\decPrint.c"
|
||||
"C:\_projects\abc\src\opt\dec\decUtil.c"
|
||||
"C:\_projects\abc\src\opt\sim\simMan.c"
|
||||
"C:\_projects\abc\src\opt\sim\simSat.c"
|
||||
"C:\_projects\abc\src\opt\sim\simSeq.c"
|
||||
"C:\_projects\abc\src\opt\sim\simSupp.c"
|
||||
"C:\_projects\abc\src\opt\sim\simSwitch.c"
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||||
"C:\_projects\abc\src\opt\sim\simSym.c"
|
||||
"C:\_projects\abc\src\opt\sim\simSymSat.c"
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||||
"C:\_projects\abc\src\opt\sim\simSymSim.c"
|
||||
"C:\_projects\abc\src\opt\sim\simSymStr.c"
|
||||
"C:\_projects\abc\src\opt\sim\simUtils.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpga.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaCore.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaCreate.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaCut.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaCutUtils.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaFanout.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaLib.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaMatch.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaSwitch.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaTime.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaTruth.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaUtils.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaVec.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapper.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperCanon.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperCore.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperCreate.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperCut.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperCutUtils.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperFanout.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperLib.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperMatch.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperRefs.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperSuper.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperSwitch.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperTable.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperTime.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperTree.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperTruth.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperUtils.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperVec.c"
|
||||
"C:\_projects\abc\src\map\mio\mio.c"
|
||||
"C:\_projects\abc\src\map\mio\mioApi.c"
|
||||
"C:\_projects\abc\src\map\mio\mioFunc.c"
|
||||
"C:\_projects\abc\src\map\mio\mioRead.c"
|
||||
"C:\_projects\abc\src\map\mio\mioUtils.c"
|
||||
"C:\_projects\abc\src\map\super\super.c"
|
||||
"C:\_projects\abc\src\map\super\superAnd.c"
|
||||
"C:\_projects\abc\src\map\super\superGate.c"
|
||||
"C:\_projects\abc\src\map\super\superWrite.c"
|
||||
"C:\_projects\abc\src\map\pga\pgaCore.c"
|
||||
"C:\_projects\abc\src\map\pga\pgaMan.c"
|
||||
"C:\_projects\abc\src\map\pga\pgaMatch.c"
|
||||
"C:\_projects\abc\src\map\pga\pgaUtil.c"
|
||||
"C:\_projects\abc\src\misc\extra\extraBddKmap.c"
|
||||
"C:\_projects\abc\src\misc\extra\extraBddMisc.c"
|
||||
"C:\_projects\abc\src\misc\extra\extraBddSymm.c"
|
||||
"C:\_projects\abc\src\misc\extra\extraUtilBitMatrix.c"
|
||||
"C:\_projects\abc\src\misc\extra\extraUtilCanon.c"
|
||||
"C:\_projects\abc\src\misc\extra\extraUtilFile.c"
|
||||
"C:\_projects\abc\src\misc\extra\extraUtilMemory.c"
|
||||
"C:\_projects\abc\src\misc\extra\extraUtilMisc.c"
|
||||
"C:\_projects\abc\src\misc\extra\extraUtilProgress.c"
|
||||
"C:\_projects\abc\src\misc\extra\extraUtilReader.c"
|
||||
"C:\_projects\abc\src\misc\st\st.c"
|
||||
"C:\_projects\abc\src\misc\st\stmm.c"
|
||||
"C:\_projects\abc\src\misc\util\cpu_stats.c"
|
||||
"C:\_projects\abc\src\misc\util\cpu_time.c"
|
||||
"C:\_projects\abc\src\misc\util\datalimit.c"
|
||||
"C:\_projects\abc\src\misc\util\getopt.c"
|
||||
"C:\_projects\abc\src\misc\util\pathsearch.c"
|
||||
"C:\_projects\abc\src\misc\util\safe_mem.c"
|
||||
"C:\_projects\abc\src\misc\util\strsav.c"
|
||||
"C:\_projects\abc\src\misc\util\texpand.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvc.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvcApi.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvcCompare.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvcContain.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvcCover.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvcCube.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvcDivide.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvcDivisor.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvcList.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvcLits.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvcMan.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvcOpAlg.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvcOpBool.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvcPrint.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvcSort.c"
|
||||
"C:\_projects\abc\src\misc\mvc\mvcUtils.c"
|
||||
]
|
||||
Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP7A.tmp"
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP7B.tmp" with contents
|
||||
Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP20D.tmp"
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP20E.tmp" with contents
|
||||
[
|
||||
kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /incremental:no /pdb:"Release/abc.pdb" /machine:I386 /out:"_TEST/abc.exe"
|
||||
.\Release\abcAig.obj
|
||||
|
|
@ -645,341 +331,12 @@ kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32
|
|||
.\Release\mvcSort.obj
|
||||
.\Release\mvcUtils.obj
|
||||
]
|
||||
Creating command line "link.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP7B.tmp"
|
||||
Creating command line "link.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP20E.tmp"
|
||||
<h3>Output Window</h3>
|
||||
Compiling...
|
||||
abcAig.c
|
||||
abcCheck.c
|
||||
abcDfs.c
|
||||
abcFanio.c
|
||||
abcFunc.c
|
||||
abcLatch.c
|
||||
abcMinBase.c
|
||||
abcNames.c
|
||||
abcNetlist.c
|
||||
abcNtk.c
|
||||
abcObj.c
|
||||
abcRefs.c
|
||||
abcShow.c
|
||||
abcSop.c
|
||||
abcUtil.c
|
||||
abc.c
|
||||
abcAttach.c
|
||||
abcBalance.c
|
||||
abcCollapse.c
|
||||
abcCut.c
|
||||
abcDsd.c
|
||||
abcFpga.c
|
||||
abcFraig.c
|
||||
abcFxu.c
|
||||
abcMap.c
|
||||
abcMiter.c
|
||||
abcNtbdd.c
|
||||
abcPga.c
|
||||
abcPrint.c
|
||||
abcReconv.c
|
||||
abcRefactor.c
|
||||
abcRenode.c
|
||||
abcRewrite.c
|
||||
abcSat.c
|
||||
abcStrash.c
|
||||
abcSweep.c
|
||||
abcSymm.c
|
||||
abcTiming.c
|
||||
abcUnreach.c
|
||||
abcVanEijk.c
|
||||
abcVanImp.c
|
||||
abcVerify.c
|
||||
seqAigCore.c
|
||||
seqAigIter.c
|
||||
seqCreate.c
|
||||
seqFpgaCore.c
|
||||
seqFpgaIter.c
|
||||
seqLatch.c
|
||||
seqMan.c
|
||||
seqMapCore.c
|
||||
seqMapIter.c
|
||||
seqRetCore.c
|
||||
seqRetIter.c
|
||||
seqShare.c
|
||||
seqUtil.c
|
||||
cmd.c
|
||||
cmdAlias.c
|
||||
cmdApi.c
|
||||
cmdFlag.c
|
||||
cmdHist.c
|
||||
cmdUtils.c
|
||||
io.c
|
||||
ioRead.c
|
||||
ioReadBaf.c
|
||||
ioReadBench.c
|
||||
ioReadBlif.c
|
||||
ioReadEdif.c
|
||||
ioReadEqn.c
|
||||
ioReadPla.c
|
||||
ioReadVerilog.c
|
||||
ioUtil.c
|
||||
ioWriteBaf.c
|
||||
ioWriteBench.c
|
||||
ioWriteBlif.c
|
||||
ioWriteCnf.c
|
||||
ioWriteDot.c
|
||||
ioWriteEqn.c
|
||||
ioWriteGml.c
|
||||
ioWriteList.c
|
||||
ioWritePla.c
|
||||
libSupport.c
|
||||
main.c
|
||||
mainFrame.c
|
||||
mainInit.c
|
||||
mainUtils.c
|
||||
cuddAddAbs.c
|
||||
cuddAddApply.c
|
||||
cuddAddFind.c
|
||||
cuddAddInv.c
|
||||
cuddAddIte.c
|
||||
cuddAddNeg.c
|
||||
cuddAddWalsh.c
|
||||
cuddAndAbs.c
|
||||
cuddAnneal.c
|
||||
cuddApa.c
|
||||
C:\_projects\abc\src\bdd\cudd\cuddApa.c(181) : warning C4244: 'return' : conversion from 'unsigned long ' to 'unsigned short ', possible loss of data
|
||||
C:\_projects\abc\src\bdd\cudd\cuddApa.c(213) : warning C4244: 'return' : conversion from 'unsigned long ' to 'unsigned short ', possible loss of data
|
||||
C:\_projects\abc\src\bdd\cudd\cuddApa.c(530) : warning C4244: '=' : conversion from 'unsigned short ' to 'unsigned char ', possible loss of data
|
||||
C:\_projects\abc\src\bdd\cudd\cuddApa.c(588) : warning C4244: '=' : conversion from 'unsigned short ' to 'unsigned char ', possible loss of data
|
||||
cuddAPI.c
|
||||
cuddApprox.c
|
||||
cuddBddAbs.c
|
||||
cuddBddCorr.c
|
||||
cuddBddIte.c
|
||||
cuddBridge.c
|
||||
cuddCache.c
|
||||
C:\_projects\abc\src\bdd\cudd\cuddCache.c(902) : warning C4146: unary minus operator applied to unsigned type, result still unsigned
|
||||
cuddCheck.c
|
||||
cuddClip.c
|
||||
cuddCof.c
|
||||
cuddCompose.c
|
||||
cuddDecomp.c
|
||||
cuddEssent.c
|
||||
cuddExact.c
|
||||
cuddExport.c
|
||||
cuddGenCof.c
|
||||
cuddGenetic.c
|
||||
cuddGroup.c
|
||||
C:\_projects\abc\src\bdd\cudd\cuddGroup.c(2062) : warning C4018: '<=' : signed/unsigned mismatch
|
||||
cuddHarwell.c
|
||||
cuddInit.c
|
||||
cuddInteract.c
|
||||
cuddLCache.c
|
||||
C:\_projects\abc\src\bdd\cudd\cuddLCache.c(1387) : warning C4146: unary minus operator applied to unsigned type, result still unsigned
|
||||
cuddLevelQ.c
|
||||
cuddLinear.c
|
||||
cuddLiteral.c
|
||||
cuddMatMult.c
|
||||
cuddPriority.c
|
||||
cuddRead.c
|
||||
cuddRef.c
|
||||
cuddReorder.c
|
||||
C:\_projects\abc\src\bdd\cudd\cuddReorder.c(395) : warning C4146: unary minus operator applied to unsigned type, result still unsigned
|
||||
cuddSat.c
|
||||
C:\_projects\abc\src\bdd\cudd\cuddReorder.c(2016) : warning C4700: local variable 'minLevel' used without having been initialized
|
||||
C:\_projects\abc\src\bdd\cudd\cuddReorder.c(2020) : warning C4700: local variable 'maxLevel' used without having been initialized
|
||||
cuddSign.c
|
||||
cuddSolve.c
|
||||
cuddSplit.c
|
||||
cuddSubsetHB.c
|
||||
cuddSubsetSP.c
|
||||
cuddSymmetry.c
|
||||
cuddTable.c
|
||||
C:\_projects\abc\src\bdd\cudd\cuddTable.c(1822) : warning C4018: '<' : signed/unsigned mismatch
|
||||
C:\_projects\abc\src\bdd\cudd\cuddTable.c(1927) : warning C4018: '<' : signed/unsigned mismatch
|
||||
C:\_projects\abc\src\bdd\cudd\cuddTable.c(2235) : warning C4018: '<' : signed/unsigned mismatch
|
||||
C:\_projects\abc\src\bdd\cudd\cuddTable.c(2303) : warning C4018: '<' : signed/unsigned mismatch
|
||||
C:\_projects\abc\src\bdd\cudd\cuddTable.c(2358) : warning C4146: unary minus operator applied to unsigned type, result still unsigned
|
||||
cuddUtil.c
|
||||
cuddWindow.c
|
||||
cuddZddCount.c
|
||||
cuddZddFuncs.c
|
||||
cuddZddGroup.c
|
||||
cuddZddIsop.c
|
||||
cuddZddLin.c
|
||||
cuddZddMisc.c
|
||||
cuddZddPort.c
|
||||
cuddZddReord.c
|
||||
cuddZddSetop.c
|
||||
cuddZddSymm.c
|
||||
cuddZddUtil.c
|
||||
epd.c
|
||||
mtrBasic.c
|
||||
mtrGroup.c
|
||||
parseCore.c
|
||||
parseStack.c
|
||||
dsdApi.c
|
||||
dsdCheck.c
|
||||
dsdLocal.c
|
||||
dsdMan.c
|
||||
dsdProc.c
|
||||
dsdTree.c
|
||||
reoApi.c
|
||||
reoCore.c
|
||||
reoProfile.c
|
||||
reoSift.c
|
||||
reoSwap.c
|
||||
reoTest.c
|
||||
reoTransfer.c
|
||||
reoUnits.c
|
||||
added.c
|
||||
solver.c
|
||||
msatActivity.c
|
||||
msatClause.c
|
||||
msatClauseVec.c
|
||||
msatMem.c
|
||||
msatOrderH.c
|
||||
msatQueue.c
|
||||
msatRead.c
|
||||
msatSolverApi.c
|
||||
msatSolverCore.c
|
||||
msatSolverIo.c
|
||||
msatSolverSearch.c
|
||||
msatSort.c
|
||||
msatVec.c
|
||||
fraigApi.c
|
||||
fraigCanon.c
|
||||
fraigFanout.c
|
||||
fraigFeed.c
|
||||
fraigMan.c
|
||||
fraigMem.c
|
||||
fraigNode.c
|
||||
fraigPrime.c
|
||||
fraigSat.c
|
||||
fraigTable.c
|
||||
fraigUtil.c
|
||||
fraigVec.c
|
||||
csat_apis.c
|
||||
fxu.c
|
||||
fxuCreate.c
|
||||
fxuHeapD.c
|
||||
fxuHeapS.c
|
||||
fxuList.c
|
||||
fxuMatrix.c
|
||||
fxuPair.c
|
||||
fxuPrint.c
|
||||
fxuReduce.c
|
||||
fxuSelect.c
|
||||
fxuSingle.c
|
||||
fxuUpdate.c
|
||||
rwrDec.c
|
||||
rwrEva.c
|
||||
rwrExp.c
|
||||
rwrLib.c
|
||||
rwrMan.c
|
||||
rwrPrint.c
|
||||
rwrUtil.c
|
||||
cutApi.c
|
||||
cutCut.c
|
||||
cutMan.c
|
||||
cutMerge.c
|
||||
cutNode.c
|
||||
cutOracle.c
|
||||
cutSeq.c
|
||||
cutTruth.c
|
||||
decAbc.c
|
||||
decFactor.c
|
||||
decMan.c
|
||||
decPrint.c
|
||||
decUtil.c
|
||||
simMan.c
|
||||
simSat.c
|
||||
simSeq.c
|
||||
simSupp.c
|
||||
simSwitch.c
|
||||
simSym.c
|
||||
simSymSat.c
|
||||
simSymSim.c
|
||||
simSymStr.c
|
||||
simUtils.c
|
||||
fpga.c
|
||||
fpgaCore.c
|
||||
fpgaCreate.c
|
||||
fpgaCut.c
|
||||
fpgaCutUtils.c
|
||||
fpgaFanout.c
|
||||
fpgaLib.c
|
||||
fpgaMatch.c
|
||||
fpgaSwitch.c
|
||||
fpgaTime.c
|
||||
fpgaTruth.c
|
||||
fpgaUtils.c
|
||||
fpgaVec.c
|
||||
mapper.c
|
||||
mapperCanon.c
|
||||
mapperCore.c
|
||||
mapperCreate.c
|
||||
mapperCut.c
|
||||
mapperCutUtils.c
|
||||
mapperFanout.c
|
||||
mapperLib.c
|
||||
mapperMatch.c
|
||||
mapperRefs.c
|
||||
mapperSuper.c
|
||||
mapperSwitch.c
|
||||
mapperTable.c
|
||||
mapperTime.c
|
||||
mapperTree.c
|
||||
mapperTruth.c
|
||||
mapperUtils.c
|
||||
mapperVec.c
|
||||
mio.c
|
||||
mioApi.c
|
||||
mioFunc.c
|
||||
mioRead.c
|
||||
mioUtils.c
|
||||
super.c
|
||||
superAnd.c
|
||||
superGate.c
|
||||
superWrite.c
|
||||
pgaCore.c
|
||||
pgaMan.c
|
||||
pgaMatch.c
|
||||
pgaUtil.c
|
||||
extraBddKmap.c
|
||||
extraBddMisc.c
|
||||
extraBddSymm.c
|
||||
extraUtilBitMatrix.c
|
||||
extraUtilCanon.c
|
||||
extraUtilFile.c
|
||||
extraUtilMemory.c
|
||||
extraUtilMisc.c
|
||||
extraUtilProgress.c
|
||||
extraUtilReader.c
|
||||
st.c
|
||||
stmm.c
|
||||
cpu_stats.c
|
||||
cpu_time.c
|
||||
datalimit.c
|
||||
getopt.c
|
||||
pathsearch.c
|
||||
safe_mem.c
|
||||
strsav.c
|
||||
texpand.c
|
||||
mvc.c
|
||||
mvcApi.c
|
||||
mvcCompare.c
|
||||
mvcContain.c
|
||||
mvcCover.c
|
||||
mvcCube.c
|
||||
mvcDivide.c
|
||||
mvcDivisor.c
|
||||
mvcList.c
|
||||
mvcLits.c
|
||||
mvcMan.c
|
||||
mvcOpAlg.c
|
||||
mvcOpBool.c
|
||||
mvcPrint.c
|
||||
mvcSort.c
|
||||
mvcUtils.c
|
||||
Linking...
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP7D.tmp" with contents
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP210.tmp" with contents
|
||||
[
|
||||
/nologo /o"Release/abc.bsc"
|
||||
.\Release\abcAig.sbr
|
||||
|
|
@ -1297,14 +654,14 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP7D.tmp" with conten
|
|||
.\Release\mvcPrint.sbr
|
||||
.\Release\mvcSort.sbr
|
||||
.\Release\mvcUtils.sbr]
|
||||
Creating command line "bscmake.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP7D.tmp"
|
||||
Creating command line "bscmake.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP210.tmp"
|
||||
Creating browse info file...
|
||||
<h3>Output Window</h3>
|
||||
|
||||
|
||||
|
||||
<h3>Results</h3>
|
||||
abc.exe - 0 error(s), 15 warning(s)
|
||||
abc.exe - 0 error(s), 0 warning(s)
|
||||
</pre>
|
||||
</body>
|
||||
</html>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,4 +1,4 @@
|
|||
.model iscas\s444.bench
|
||||
.model s444
|
||||
.inputs G0 G1 G2
|
||||
.outputs G118 G167 G107 G119 G168 G108
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
113
regtest.script
113
regtest.script
|
|
@ -1,103 +1,12 @@
|
|||
r examples/apex4.pla
|
||||
resyn
|
||||
sharem
|
||||
fpga
|
||||
cec
|
||||
ps
|
||||
|
||||
clp
|
||||
share
|
||||
resyn
|
||||
map
|
||||
cec
|
||||
ps
|
||||
|
||||
r examples/C2670.blif
|
||||
resyn
|
||||
fpga
|
||||
cec
|
||||
ps
|
||||
|
||||
u
|
||||
map
|
||||
cec
|
||||
ps
|
||||
|
||||
r examples/frg2.blif
|
||||
dsd
|
||||
muxes
|
||||
cec
|
||||
clp
|
||||
share
|
||||
resyn
|
||||
map
|
||||
cec
|
||||
ps
|
||||
|
||||
r examples/pj1.blif
|
||||
resyn
|
||||
fpga
|
||||
cec
|
||||
ps
|
||||
|
||||
u
|
||||
map
|
||||
cec
|
||||
ps
|
||||
|
||||
r examples/s38584.bench
|
||||
resyn
|
||||
fpga
|
||||
cec
|
||||
ps
|
||||
|
||||
u
|
||||
map
|
||||
cec
|
||||
ps
|
||||
|
||||
r examples/ac.v
|
||||
resyn
|
||||
fpga
|
||||
cec
|
||||
ps
|
||||
|
||||
u
|
||||
map
|
||||
cec
|
||||
ps
|
||||
|
||||
r examples/s444.blif
|
||||
b
|
||||
esd -v
|
||||
dsd
|
||||
cec
|
||||
ps
|
||||
|
||||
r examples/i10.blif
|
||||
fpga
|
||||
cec
|
||||
ps
|
||||
u
|
||||
map
|
||||
cec
|
||||
ps
|
||||
|
||||
r examples/i10.blif
|
||||
b
|
||||
fraig_store
|
||||
resyn
|
||||
fraig_store
|
||||
resyn2
|
||||
fraig_store
|
||||
fraig_restore
|
||||
fpga
|
||||
cec
|
||||
ps
|
||||
|
||||
u
|
||||
map
|
||||
cec
|
||||
ps
|
||||
|
||||
r examples/apex4.pla; resyn; sharem; fpga; cec; ps; clp; share; resyn; map; cec; ps
|
||||
r examples/C2670.blif; resyn; fpga; cec; ps; u; map; cec; ps
|
||||
r examples/frg2.blif; dsd; muxes; cec; clp; share; resyn; map; cec; ps
|
||||
r examples/pj1.blif; resyn; fpga; cec; ps; u; map; cec; ps
|
||||
r examples/s38584.bench; resyn; fpga; cec; ps; u; map; cec; ps
|
||||
r examples/ac.v; resyn; fpga; cec; ps; u; map; cec; ps
|
||||
r examples/s444.blif; b; esd -v; dsd; cec; ps
|
||||
r examples/i10.blif; fpga; cec; ps; u; map; cec; ps
|
||||
r examples/i10.blif; choice; fpga; cec; ps; u; map; cec; ps
|
||||
r examples/s6669.blif; fpga; ps; sec; u; sfpga; ps; sec; u; fpga; ret; ps; sec
|
||||
r examples/s5378.blif; map -s; ps; sec; u; smap; ps; sec; u; map; ret; ps; sec
|
||||
time
|
||||
|
|
|
|||
|
|
@ -1,110 +1,39 @@
|
|||
UC Berkeley, ABC 1.01 (compiled Sep 5 2005 23:36:08)
|
||||
UC Berkeley, ABC 1.01 (compiled Dec 3 2005 16:58:37)
|
||||
abc 01> so regtest.script
|
||||
abc - > r examples/apex4.pla
|
||||
abc - > resyn
|
||||
abc - > sharem
|
||||
abc - > fpga
|
||||
abc - > cec
|
||||
abc - > r examples/apex4.pla; resyn; sharem; fpga; cec; ps; clp; share; resyn; map; cec; ps
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
examples/apex4.pla: i/o = 9/ 19 lat = 0 nd = 784 cube = 1985 lev = 5
|
||||
abc - >
|
||||
abc - > clp
|
||||
The shared BDD size is 917 nodes.
|
||||
abc - > share
|
||||
abc - > resyn
|
||||
abc - > map
|
||||
examples/apex4: i/o = 9/ 19 lat = 0 nd = 1182 cube = 2193 lev = 7
|
||||
The shared BDD size is 900 nodes.
|
||||
A simple supergate library is derived from gate library "mcnc_temp.genlib".
|
||||
Loaded 20 unique 5-input supergates from "mcnc_temp.super". Time = 0.02 sec
|
||||
abc - > cec
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
examples/apex4.pla: i/o = 9/ 19 lat = 0 nd = 1816 area = 4599.00 delay = 11.50 lev = 11
|
||||
abc - >
|
||||
abc - > r examples/C2670.blif
|
||||
abc - > resyn
|
||||
abc - > fpga
|
||||
abc - > cec
|
||||
examples/apex4: i/o = 9/ 19 lat = 0 nd = 1849 area = 4581.00 delay = 11.60 lev = 11
|
||||
abc - > r examples/C2670.blif; resyn; fpga; cec; ps; u; map; cec; ps
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
C2670.iscas : i/o = 233/ 140 lat = 0 nd = 169 cube = 482 lev = 6
|
||||
abc - >
|
||||
abc - > u
|
||||
abc - > map
|
||||
abc - > cec
|
||||
C2670.iscas : i/o = 233/ 140 lat = 0 nd = 219 cube = 446 lev = 7
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
C2670.iscas : i/o = 233/ 140 lat = 0 nd = 465 area = 1142.00 delay = 15.50 lev = 14
|
||||
abc - >
|
||||
abc - > r examples/frg2.blif
|
||||
abc - > dsd
|
||||
abc - > muxes
|
||||
abc - > cec
|
||||
C2670.iscas : i/o = 233/ 140 lat = 0 nd = 466 area = 1160.00 delay = 15.50 lev = 14
|
||||
abc - > r examples/frg2.blif; dsd; muxes; cec; clp; share; resyn; map; cec; ps
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > clp
|
||||
The shared BDD size is 1111 nodes.
|
||||
abc - > share
|
||||
abc - > resyn
|
||||
abc - > map
|
||||
abc - > cec
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
frg2 : i/o = 143/ 139 lat = 0 nd = 540 area = 1360.00 delay = 10.10 lev = 9
|
||||
abc - >
|
||||
abc - > r examples/pj1.blif
|
||||
abc - > resyn
|
||||
abc - > fpga
|
||||
abc - > cec
|
||||
frg2 : i/o = 143/ 139 lat = 0 nd = 547 area = 1381.00 delay = 9.70 lev = 9
|
||||
abc - > r examples/pj1.blif; resyn; fpga; cec; ps; u; map; cec; ps
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
exCombCkt : i/o = 1769/1063 lat = 0 nd = 4730 cube = 10662 lev = 12
|
||||
abc - >
|
||||
abc - > u
|
||||
abc - > map
|
||||
abc - > cec
|
||||
exCombCkt : i/o = 1769/1063 lat = 0 nd = 5611 cube = 10398 lev = 15
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
exCombCkt : i/o = 1769/1063 lat = 0 nd = 10396 area = 25170.00 delay = 29.20 lev = 27
|
||||
abc - >
|
||||
abc - > r examples/s38584.bench
|
||||
abc - > resyn
|
||||
The network has 26 self-feeding latches.
|
||||
abc - > fpga
|
||||
abc - > cec
|
||||
The network has 26 self-feeding latches.
|
||||
The network has 26 self-feeding latches.
|
||||
exCombCkt : i/o = 1769/1063 lat = 0 nd = 10317 area = 24980.00 delay = 29.80 lev = 27
|
||||
abc - > r examples/s38584.bench; resyn; fpga; cec; ps; u; map; cec; ps
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
examples/s38584.bench: i/o = 12/ 278 lat = 1452 nd = 3239 cube = 6769 lev = 7
|
||||
abc - >
|
||||
abc - > u
|
||||
abc - > map
|
||||
The network has 26 self-feeding latches.
|
||||
abc - > cec
|
||||
The network has 26 self-feeding latches.
|
||||
The network has 26 self-feeding latches.
|
||||
examples/s38584: i/o = 12/ 278 lat = 1452 nd = 4411 cube = 7544 lev = 9
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
examples/s38584.bench: i/o = 12/ 278 lat = 1452 nd = 8522 area = 19305.00 delay = 20.60 lev = 17
|
||||
abc - >
|
||||
abc - > r examples/ac.v
|
||||
abc - > resyn
|
||||
abc - > fpga
|
||||
abc - > cec
|
||||
examples/s38584: i/o = 12/ 278 lat = 1452 nd = 8510 area = 19315.00 delay = 20.60 lev = 17
|
||||
abc - > r examples/ac.v; resyn; fpga; cec; ps; u; map; cec; ps
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
ac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 3652 cube = 9391 lev = 3
|
||||
abc - >
|
||||
abc - > u
|
||||
abc - > map
|
||||
abc - > cec
|
||||
ac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 4086 cube = 7790 lev = 4
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
ac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 8337 area = 19861.00 delay = 8.10 lev = 8
|
||||
abc - >
|
||||
abc - > r examples/s444.blif
|
||||
abc - > b
|
||||
abc - > esd -v
|
||||
ac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 8278 area = 19714.00 delay = 8.10 lev = 8
|
||||
abc - > r examples/s444.blif; b; esd -v; dsd; cec; ps
|
||||
The shared BDD size is 181 nodes.
|
||||
BDD nodes in the transition relation before reordering 557.
|
||||
BDD nodes in the transition relation after reordering 456.
|
||||
|
|
@ -112,54 +41,50 @@ Reachability analysis completed in 151 iterations.
|
|||
The number of minterms in the reachable state set = 8865.
|
||||
BDD nodes in the unreachable states before reordering 124.
|
||||
BDD nodes in the unreachable states after reordering 113.
|
||||
abc - > dsd
|
||||
abc - > cec
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
iscas\s444.bench: i/o = 3/ 6 lat = 21 nd = 81 cube = 119 lev = 7
|
||||
abc - >
|
||||
abc - > r examples/i10.blif
|
||||
abc - > fpga
|
||||
s444 : i/o = 3/ 6 lat = 21 nd = 81 cube = 120 lev = 7
|
||||
abc - > r examples/i10.blif; fpga; cec; ps; u; map; cec; ps
|
||||
The network was strashed and balanced before FPGA mapping.
|
||||
abc - > cec
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
i10 : i/o = 257/ 224 lat = 0 nd = 741 cube = 1616 lev = 11
|
||||
abc - > u
|
||||
abc - > map
|
||||
i10 : i/o = 257/ 224 lat = 0 nd = 898 cube = 1603 lev = 13
|
||||
The network was strashed and balanced before mapping.
|
||||
abc - > cec
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
i10 : i/o = 257/ 224 lat = 0 nd = 1659 area = 4215.00 delay = 30.80 lev = 27
|
||||
abc - >
|
||||
abc - > r examples/i10.blif
|
||||
abc - > b
|
||||
abc - > fraig_store
|
||||
The number of AIG nodes added to storage = 2425.
|
||||
abc - > resyn
|
||||
abc - > fraig_store
|
||||
The number of AIG nodes added to storage = 1678.
|
||||
abc - > resyn2
|
||||
abc - > fraig_store
|
||||
The number of AIG nodes added to storage = 1323.
|
||||
abc - > fraig_restore
|
||||
Currently stored 3 networks with 5426 nodes will be fraiged.
|
||||
abc - > fpga
|
||||
i10 : i/o = 257/ 224 lat = 0 nd = 1708 area = 4275.00 delay = 30.80 lev = 28
|
||||
abc - > r examples/i10.blif; choice; fpga; cec; ps; u; map; cec; ps
|
||||
The number of AIG nodes added to storage = 2675.
|
||||
The number of AIG nodes added to storage = 1744.
|
||||
The number of AIG nodes added to storage = 1431.
|
||||
Currently stored 3 networks with 5850 nodes will be fraiged.
|
||||
Performing FPGA mapping with choices.
|
||||
abc - > cec
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
i10 : i/o = 257/ 224 lat = 0 nd = 674 cube = 1498 lev = 10
|
||||
abc - >
|
||||
abc - > u
|
||||
abc - > map
|
||||
i10 : i/o = 257/ 224 lat = 0 nd = 793 cube = 1454 lev = 12
|
||||
Performing mapping with choices.
|
||||
abc - > cec
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > ps
|
||||
i10 : i/o = 257/ 224 lat = 0 nd = 1505 area = 3561.00 delay = 25.00 lev = 22
|
||||
abc - >
|
||||
abc 109> time
|
||||
elapse: 77.52 seconds, total: 77.52 seconds
|
||||
abc 109>
|
||||
i10 : i/o = 257/ 224 lat = 0 nd = 1485 area = 3521.00 delay = 25.60 lev = 23
|
||||
abc - > r examples/s6669.blif; fpga; ps; sec; u; sfpga; ps; sec; u; fpga; ret; ps; sec
|
||||
The network was strashed and balanced before FPGA mapping.
|
||||
s6669 : i/o = 83/ 55 lat = 239 nd = 678 bdd = 3036 lev = 20
|
||||
Networks are equivalent after fraiging.
|
||||
The network was strashed and balanced before FPGA mapping/retiming.
|
||||
The number of LUTs with incompatible edges = 99.
|
||||
The number of LUTs with more than 4 inputs = 61.
|
||||
s6669 : i/o = 83/ 55 lat = 451 nd = 865 bdd = 4221 lev = 6
|
||||
Networks are equivalent after fraiging.
|
||||
The network was strashed and balanced before FPGA mapping.
|
||||
s6669 : i/o = 83/ 55 lat = 393 nd = 787 bdd = 3300 lev = 8
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > r examples/s5378.blif; map -s; ps; sec; u; smap; ps; sec; u; map; ret; ps; sec
|
||||
The network was strashed and balanced before mapping.
|
||||
s5378 : i/o = 35/ 49 lat = 164 nd = 1015 area = 2384.00 delay = 12.40 lev = 10
|
||||
Networks are equivalent after fraiging.
|
||||
The number of nodes with equal fanins = 5.
|
||||
The network was strashed and balanced before SC mapping/retiming.
|
||||
The mininum clock period computed is 10.00.
|
||||
The resulting network is derived as BDD logic network (this is temporary).
|
||||
s5378 : i/o = 35/ 49 lat = 396 nd = 1252 bdd = 4619 lev = 7
|
||||
Networks are equivalent after fraiging.
|
||||
The network was strashed and balanced before mapping.
|
||||
s5378 : i/o = 35/ 49 lat = 364 nd = 1084 area = 2453.00 delay = 11.70 lev = 11
|
||||
Networks are equivalent after fraiging.
|
||||
abc - > time
|
||||
elapse: 42.05 seconds, total: 42.05 secondsabc - >abc - > r examples/s38584.benchabc - > resynThe network has 26 self-feeding latches.abc - > fpgaabc - > cecThe network has 26 self-feeding latches.The network has 26 self-feeding latches.Networks are equivalent after fraiging.abc - > psexamples/s38584.bench: i/o = 12/ 278 lat = 1452 nd = 3239 cube = 6769 lev = 7abc - >abc - > uabc - > mapThe network has 26 self-feeding latches.abc - > cecThe network has 26 self-feeding latches.The network has 26 self-feeding latches.Networks are equivalent after fraiging.abc - > psexamples/s38584.bench: i/o = 12/ 278 lat = 1452 nd = 8522 area = 19305.00 delay = 20.60 lev = 17abc - >abc - > r examples/ac.vabc - > resynabc - > fpgaabc - > cecNetworks are equivalent after fraiging.abc - > psac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 3652 cube = 9391 lev = 3abc - >abc - > uabc - > mapabc - > cecNetworks are equivalent after fraiging.abc - > psac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 8337 area = 19861.00 delay = 8.10 lev = 8abc - >abc - > r examples/s444.blifabc - > babc - > esd -vThe shared BDD size is 181 nodes.BDD nodes in the transition relation before reordering 557.BDD nodes in the transition relation after reordering 456.Reachability analysis completed in 151 iterations.The number of minterms in the reachable state set = 8865.BDD nodes in the unreachable states before reordering 124.BDD nodes in the unreachable states after reordering 113.abc - > dsdabc - > cecNetworks are equivalent after fraiging.abc - > psiscas\s444.bench: i/o = 3/ 6 lat = 21 nd = 81 cube = 119 lev = 7abc - >abc - > r examples/i10.blifabc - > fpgaThe network was strashed and balanced before FPGA mapping.abc - > cecNetworks are equivalent after fraiging.abc - > psi10 : i/o = 257/ 224 lat = 0 nd = 741 cube = 1616 lev = 11abc - > uabc - > mapThe network was strashed and balanced before mapping.abc - > cecNetworks are equivalent after fraiging.abc - > psi10 : i/o = 257/ 224 lat = 0 nd = 1659 area = 4215.00 delay = 30.80 lev = 27abc - >abc - > r examples/i10.blifabc - > babc - > fraig_storeThe number of AIG nodes added to storage = 2425.abc - > resynabc - > fraig_storeThe number of AIG nodes added to storage = 1678.abc - > resyn2abc - > fraig_storeThe number of AIG nodes added to storage = 1323.abc - > fraig_restoreCurrently stored 3 networks with 5426 nodes will be fraiged.abc - > fpgaPerforming FPGA mapping with choices.abc - > cecNetworks are equivalent after fraiging.abc - > psi10 : i/o = 257/ 224 lat = 0 nd = 674 cube = 1498 lev = 10abc - >abc - > uabc - > mapPerforming mapping with choices.abc - > cecNetworks are equivalent after fraiging.abc - > psi10 : i/o = 257/ 224 lat = 0 nd = 1505 area = 3561.00 delay = 25.00 lev = 22abc - >abc 109> timeelapse: 77.52 seconds, total: 77.52 secondsabc 109>
|
||||
|
|
@ -236,7 +236,7 @@ Abc_Ntk_t * Abc_NtkStartRead( char * pName )
|
|||
pNtkNew = Abc_NtkAlloc( ABC_NTK_NETLIST, ABC_FUNC_SOP );
|
||||
// set the specs
|
||||
pNtkNew->pName = util_strsav( Extra_FileNameGeneric(pName) );
|
||||
pNtkNew->pSpec = util_strsav( Extra_FileNameGeneric(pName) );
|
||||
pNtkNew->pSpec = util_strsav( pName );
|
||||
return pNtkNew;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@ static int Abc_CommandPrintSupport ( Abc_Frame_t * pAbc, int argc, char ** argv
|
|||
static int Abc_CommandPrintSymms ( Abc_Frame_t * pAbc, int argc, char ** argv );
|
||||
static int Abc_CommandPrintKMap ( Abc_Frame_t * pAbc, int argc, char ** argv );
|
||||
static int Abc_CommandPrintGates ( Abc_Frame_t * pAbc, int argc, char ** argv );
|
||||
static int Abc_CommandPrintSharing ( Abc_Frame_t * pAbc, int argc, char ** argv );
|
||||
|
||||
static int Abc_CommandShowBdd ( Abc_Frame_t * pAbc, int argc, char ** argv );
|
||||
static int Abc_CommandShowCut ( Abc_Frame_t * pAbc, int argc, char ** argv );
|
||||
|
|
@ -137,6 +138,7 @@ void Abc_Init( Abc_Frame_t * pAbc )
|
|||
Cmd_CommandAdd( pAbc, "Printing", "print_symm", Abc_CommandPrintSymms, 0 );
|
||||
Cmd_CommandAdd( pAbc, "Printing", "print_kmap", Abc_CommandPrintKMap, 0 );
|
||||
Cmd_CommandAdd( pAbc, "Printing", "print_gates", Abc_CommandPrintGates, 0 );
|
||||
Cmd_CommandAdd( pAbc, "Printing", "print_sharing", Abc_CommandPrintSharing, 0 );
|
||||
|
||||
Cmd_CommandAdd( pAbc, "Printing", "show_bdd", Abc_CommandShowBdd, 0 );
|
||||
Cmd_CommandAdd( pAbc, "Printing", "show_cut", Abc_CommandShowCut, 0 );
|
||||
|
|
@ -1008,6 +1010,69 @@ usage:
|
|||
return 1;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis []
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
int Abc_CommandPrintSharing( Abc_Frame_t * pAbc, int argc, char ** argv )
|
||||
{
|
||||
FILE * pOut, * pErr;
|
||||
Abc_Ntk_t * pNtk;
|
||||
int c;
|
||||
int fUseLibrary;
|
||||
|
||||
extern void Abc_NtkPrintSharing( Abc_Ntk_t * pNtk );
|
||||
|
||||
pNtk = Abc_FrameReadNet(pAbc);
|
||||
pOut = Abc_FrameReadOut(pAbc);
|
||||
pErr = Abc_FrameReadErr(pAbc);
|
||||
|
||||
// set defaults
|
||||
fUseLibrary = 1;
|
||||
util_getopt_reset();
|
||||
while ( ( c = util_getopt( argc, argv, "lh" ) ) != EOF )
|
||||
{
|
||||
switch ( c )
|
||||
{
|
||||
case 'l':
|
||||
fUseLibrary ^= 1;
|
||||
break;
|
||||
case 'h':
|
||||
goto usage;
|
||||
default:
|
||||
goto usage;
|
||||
}
|
||||
}
|
||||
|
||||
if ( pNtk == NULL )
|
||||
{
|
||||
fprintf( pErr, "Empty network.\n" );
|
||||
return 1;
|
||||
}
|
||||
if ( Abc_NtkIsSeq(pNtk) )
|
||||
{
|
||||
fprintf( pErr, "Printing logic sharing does not work for sequential AIGs.\n" );
|
||||
return 1;
|
||||
}
|
||||
|
||||
Abc_NtkPrintSharing( pNtk );
|
||||
return 0;
|
||||
|
||||
usage:
|
||||
fprintf( pErr, "usage: print_sharing [-h]\n" );
|
||||
fprintf( pErr, "\t prints the number of shared nodes in the TFO cones of the COs\n" );
|
||||
// fprintf( pErr, "\t-l : used library gate names (if mapped) [default = %s]\n", fUseLibrary? "yes": "no" );
|
||||
fprintf( pErr, "\t-h : print the command usage\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis []
|
||||
|
|
@ -4245,14 +4310,14 @@ usage:
|
|||
sprintf( Buffer, "not used" );
|
||||
else
|
||||
sprintf( Buffer, "%.3f", DelayTarget );
|
||||
fprintf( pErr, "usage: map [-D num] [-aspvh]\n" );
|
||||
fprintf( pErr, "\t performs standard cell mapping of the current network\n" );
|
||||
fprintf( pErr, "\t-D num : sets the global required times [default = %s]\n", Buffer );
|
||||
fprintf( pErr, "\t-a : toggles area recovery [default = %s]\n", fRecovery? "yes": "no" );
|
||||
fprintf( pErr, "\t-s : toggles sweep after mapping [default = %s]\n", fSweep? "yes": "no" );
|
||||
fprintf( pErr, "\t-p : optimizes power by minimizing switching activity [default = %s]\n", fSwitching? "yes": "no" );
|
||||
fprintf( pErr, "\t-v : toggles verbose output [default = %s]\n", fVerbose? "yes": "no" );
|
||||
fprintf( pErr, "\t-h : print the command usage\n");
|
||||
fprintf( pErr, "usage: map [-D float] [-aspvh]\n" );
|
||||
fprintf( pErr, "\t performs standard cell mapping of the current network\n" );
|
||||
fprintf( pErr, "\t-D float : sets the global required times [default = %s]\n", Buffer );
|
||||
fprintf( pErr, "\t-a : toggles area recovery [default = %s]\n", fRecovery? "yes": "no" );
|
||||
fprintf( pErr, "\t-s : toggles sweep after mapping [default = %s]\n", fSweep? "yes": "no" );
|
||||
fprintf( pErr, "\t-p : optimizes power by minimizing switching [default = %s]\n", fSwitching? "yes": "no" );
|
||||
fprintf( pErr, "\t-v : toggles verbose output [default = %s]\n", fVerbose? "yes": "no" );
|
||||
fprintf( pErr, "\t-h : print the command usage\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
@ -4461,24 +4526,28 @@ usage:
|
|||
***********************************************************************/
|
||||
int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
|
||||
{
|
||||
char Buffer[100];
|
||||
FILE * pOut, * pErr;
|
||||
Abc_Ntk_t * pNtk, * pNtkRes;
|
||||
int c;
|
||||
int fRecovery;
|
||||
int fSwitching;
|
||||
int fVerbose;
|
||||
extern Abc_Ntk_t * Abc_NtkFpga( Abc_Ntk_t * pNtk, int fRecovery, int fSwitching, int fVerbose );
|
||||
float DelayTarget;
|
||||
|
||||
extern Abc_Ntk_t * Abc_NtkFpga( Abc_Ntk_t * pNtk, float DelayTarget, int fRecovery, int fSwitching, int fVerbose );
|
||||
|
||||
pNtk = Abc_FrameReadNet(pAbc);
|
||||
pOut = Abc_FrameReadOut(pAbc);
|
||||
pErr = Abc_FrameReadErr(pAbc);
|
||||
|
||||
// set defaults
|
||||
fRecovery = 1;
|
||||
fSwitching = 0;
|
||||
fVerbose = 0;
|
||||
fRecovery = 1;
|
||||
fSwitching = 0;
|
||||
fVerbose = 0;
|
||||
DelayTarget =-1;
|
||||
util_getopt_reset();
|
||||
while ( ( c = util_getopt( argc, argv, "apvh" ) ) != EOF )
|
||||
while ( ( c = util_getopt( argc, argv, "apvhD" ) ) != EOF )
|
||||
{
|
||||
switch ( c )
|
||||
{
|
||||
|
|
@ -4493,6 +4562,17 @@ int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
|
|||
break;
|
||||
case 'h':
|
||||
goto usage;
|
||||
case 'D':
|
||||
if ( util_optind >= argc )
|
||||
{
|
||||
fprintf( pErr, "Command line switch \"-D\" should be followed by a floating point number.\n" );
|
||||
goto usage;
|
||||
}
|
||||
DelayTarget = (float)atof(argv[util_optind]);
|
||||
util_optind++;
|
||||
if ( DelayTarget <= 0.0 )
|
||||
goto usage;
|
||||
break;
|
||||
default:
|
||||
goto usage;
|
||||
}
|
||||
|
|
@ -4528,7 +4608,7 @@ int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
|
|||
}
|
||||
fprintf( pOut, "The network was strashed and balanced before FPGA mapping.\n" );
|
||||
// get the new network
|
||||
pNtkRes = Abc_NtkFpga( pNtk, fRecovery, fSwitching, fVerbose );
|
||||
pNtkRes = Abc_NtkFpga( pNtk, DelayTarget, fRecovery, fSwitching, fVerbose );
|
||||
if ( pNtkRes == NULL )
|
||||
{
|
||||
Abc_NtkDelete( pNtk );
|
||||
|
|
@ -4540,7 +4620,7 @@ int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
|
|||
else
|
||||
{
|
||||
// get the new network
|
||||
pNtkRes = Abc_NtkFpga( pNtk, fRecovery, fSwitching, fVerbose );
|
||||
pNtkRes = Abc_NtkFpga( pNtk, DelayTarget, fRecovery, fSwitching, fVerbose );
|
||||
if ( pNtkRes == NULL )
|
||||
{
|
||||
fprintf( pErr, "FPGA mapping has failed.\n" );
|
||||
|
|
@ -4552,10 +4632,15 @@ int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
|
|||
return 0;
|
||||
|
||||
usage:
|
||||
fprintf( pErr, "usage: fpga [-apvh]\n" );
|
||||
if ( DelayTarget == -1 )
|
||||
sprintf( Buffer, "not used" );
|
||||
else
|
||||
sprintf( Buffer, "%.2f", DelayTarget );
|
||||
fprintf( pErr, "usage: fpga [-D float] [-apvh]\n" );
|
||||
fprintf( pErr, "\t performs FPGA mapping of the current network\n" );
|
||||
fprintf( pErr, "\t-a : toggles area recovery [default = %s]\n", fRecovery? "yes": "no" );
|
||||
fprintf( pErr, "\t-p : optimizes power by minimizing switching activity [default = %s]\n", fSwitching? "yes": "no" );
|
||||
fprintf( pErr, "\t-D : sets the required time for the mapping [default = %s]\n", Buffer );
|
||||
fprintf( pErr, "\t-v : toggles verbose output [default = %s]\n", fVerbose? "yes": "no" );
|
||||
fprintf( pErr, "\t-h : prints the command usage\n");
|
||||
return 1;
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ static Abc_Obj_t * Abc_NodeFromFpga_rec( Abc_Ntk_t * pNtkNew, Fpga_Node_t * pNo
|
|||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Abc_Ntk_t * Abc_NtkFpga( Abc_Ntk_t * pNtk, int fRecovery, int fSwitching, int fVerbose )
|
||||
Abc_Ntk_t * Abc_NtkFpga( Abc_Ntk_t * pNtk, float DelayTarget, int fRecovery, int fSwitching, int fVerbose )
|
||||
{
|
||||
int fShowSwitching = 1;
|
||||
Abc_Ntk_t * pNtkNew;
|
||||
|
|
@ -73,6 +73,7 @@ Abc_Ntk_t * Abc_NtkFpga( Abc_Ntk_t * pNtk, int fRecovery, int fSwitching, int fV
|
|||
if ( pMan == NULL )
|
||||
return NULL;
|
||||
Fpga_ManSetSwitching( pMan, fSwitching );
|
||||
Fpga_ManSetDelayTarget( pMan, DelayTarget );
|
||||
if ( !Fpga_Mapping( pMan ) )
|
||||
{
|
||||
Fpga_ManFree( pMan );
|
||||
|
|
|
|||
|
|
@ -667,6 +667,55 @@ void Abc_NtkPrintGates( Abc_Ntk_t * pNtk, int fUseLibrary )
|
|||
Abc_NtkSopToBdd(pNtk);
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Prints statistics about gates used in the network.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
void Abc_NtkPrintSharing( Abc_Ntk_t * pNtk )
|
||||
{
|
||||
Vec_Ptr_t * vNodes1, * vNodes2;
|
||||
Abc_Obj_t * pObj1, * pObj2, * pNode1, * pNode2;
|
||||
int i, k, m, n, Counter;
|
||||
|
||||
// print the template
|
||||
printf( "Statistics about sharing of logic nodes among the CO pairs.\n" );
|
||||
printf( "(CO1,CO2)=NumShared : " );
|
||||
// go though the CO pairs
|
||||
Abc_NtkForEachCo( pNtk, pObj1, i )
|
||||
{
|
||||
vNodes1 = Abc_NtkDfsNodes( pNtk, &pObj1, 1 );
|
||||
// mark the nodes
|
||||
Vec_PtrForEachEntry( vNodes1, pNode1, m )
|
||||
pNode1->fMarkA = 1;
|
||||
// go through the second COs
|
||||
Abc_NtkForEachCo( pNtk, pObj2, k )
|
||||
{
|
||||
if ( i >= k )
|
||||
continue;
|
||||
vNodes2 = Abc_NtkDfsNodes( pNtk, &pObj2, 1 );
|
||||
// count the number of marked
|
||||
Counter = 0;
|
||||
Vec_PtrForEachEntry( vNodes2, pNode2, n )
|
||||
Counter += pNode2->fMarkA;
|
||||
// print
|
||||
printf( "(%d,%d)=%d ", i, k, Counter );
|
||||
Vec_PtrFree( vNodes2 );
|
||||
}
|
||||
// unmark the nodes
|
||||
Vec_PtrForEachEntry( vNodes1, pNode1, m )
|
||||
pNode1->fMarkA = 0;
|
||||
Vec_PtrFree( vNodes1 );
|
||||
}
|
||||
printf( "\n" );
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// END OF FILE ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
|
|
|||
|
|
@ -68,8 +68,8 @@ Abc_Ntk_t * Abc_NtkStrash( Abc_Ntk_t * pNtk, bool fAllNodes, bool fCleanup )
|
|||
Abc_NtkStrashPerform( pNtk, pNtkAig, fAllNodes );
|
||||
Abc_NtkFinalize( pNtk, pNtkAig );
|
||||
// print warning about self-feed latches
|
||||
if ( Abc_NtkCountSelfFeedLatches(pNtkAig) )
|
||||
printf( "Warning: The network has %d self-feeding latches.\n", Abc_NtkCountSelfFeedLatches(pNtkAig) );
|
||||
// if ( Abc_NtkCountSelfFeedLatches(pNtkAig) )
|
||||
// printf( "Warning: The network has %d self-feeding latches.\n", Abc_NtkCountSelfFeedLatches(pNtkAig) );
|
||||
if ( fCleanup && (nNodes = Abc_AigCleanup(pNtkAig->pManFunc)) )
|
||||
printf( "Warning: AIG cleanup removed %d nodes (this is not a bug).\n", nNodes );
|
||||
// duplicate EXDC
|
||||
|
|
|
|||
|
|
@ -82,6 +82,7 @@ Abc_Ntk_t * Seq_MapRetime( Abc_Ntk_t * pNtk, int nMaxIters, int fVerbose )
|
|||
printf( "The mininum clock period computed is %5.2f.\n", p->FiBestFloat );
|
||||
return NULL;
|
||||
}
|
||||
printf( "The mininum clock period computed is %5.2f.\n", p->FiBestFloat );
|
||||
printf( "The resulting network is derived as BDD logic network (this is temporary).\n" );
|
||||
|
||||
// duplicate the nodes contained in multiple cuts
|
||||
|
|
|
|||
|
|
@ -57,8 +57,8 @@ void Fpga_Init( Abc_Frame_t * pAbc )
|
|||
{
|
||||
// set the default library
|
||||
//Fpga_LutLib_t s_LutLib = { "lutlib", 6, {0,1,2,4,8,16,32}, {0,1,2,3,4,5,6} };
|
||||
Fpga_LutLib_t s_LutLib = { "lutlib", 5, {0,1,1,1,1,1}, {0,1,1,1,1,1} };
|
||||
//Fpga_LutLib_t s_LutLib = { "lutlib", 4, {0,1,1,1,1}, {0,1,1,1,1} };
|
||||
// Fpga_LutLib_t s_LutLib = { "lutlib", 5, {0,1,1,1,1,1}, {0,1,1,1,1,1} };
|
||||
Fpga_LutLib_t s_LutLib = { "lutlib", 4, {0,1,1,1,1}, {0,1,1,1,1} };
|
||||
//Fpga_LutLib_t s_LutLib = { "lutlib", 3, {0,1,1,1}, {0,1,1,1} };
|
||||
|
||||
Abc_FrameSetLibLut( Fpga_LutLibDup(&s_LutLib) );
|
||||
|
|
|
|||
|
|
@ -92,6 +92,7 @@ extern void Fpga_ManSetChoiceNodeNum( Fpga_Man_t * p, int nChoiceNode
|
|||
extern void Fpga_ManSetChoiceNum( Fpga_Man_t * p, int nChoices );
|
||||
extern void Fpga_ManSetVerbose( Fpga_Man_t * p, int fVerbose );
|
||||
extern void Fpga_ManSetSwitching( Fpga_Man_t * p, int fSwitching );
|
||||
extern void Fpga_ManSetDelayTarget( Fpga_Man_t * p, float DelayTarget );
|
||||
extern void Fpga_ManSetLatchNum( Fpga_Man_t * p, int nLatches );
|
||||
extern void Fpga_ManSetName( Fpga_Man_t * p, char * pFileName );
|
||||
|
||||
|
|
|
|||
|
|
@ -118,7 +118,7 @@ PRT( "Time", p->timeMatch );
|
|||
{
|
||||
clk = clock();
|
||||
// compute the required times and the fanouts
|
||||
Fpga_TimeComputeRequiredGlobal( p );
|
||||
Fpga_TimeComputeRequiredGlobal( p, 1 );
|
||||
// remap topologically
|
||||
Fpga_MappingMatches( p, 0 );
|
||||
// get the resulting area
|
||||
|
|
@ -143,7 +143,7 @@ PRT( "Time", clock() - clk );
|
|||
{
|
||||
clk = clock();
|
||||
// compute the required times and the fanouts
|
||||
Fpga_TimeComputeRequiredGlobal( p );
|
||||
Fpga_TimeComputeRequiredGlobal( p, 0 );
|
||||
// remap topologically
|
||||
if ( p->fSwitching )
|
||||
Fpga_MappingMatchesSwitch( p );
|
||||
|
|
|
|||
|
|
@ -66,6 +66,7 @@ void Fpga_ManSetChoiceNodeNum( Fpga_Man_t * p, int nChoiceNodes ) { p
|
|||
void Fpga_ManSetChoiceNum( Fpga_Man_t * p, int nChoices ) { p->nChoices = nChoices; }
|
||||
void Fpga_ManSetVerbose( Fpga_Man_t * p, int fVerbose ) { p->fVerbose = fVerbose; }
|
||||
void Fpga_ManSetSwitching( Fpga_Man_t * p, int fSwitching ) { p->fSwitching = fSwitching; }
|
||||
void Fpga_ManSetDelayTarget( Fpga_Man_t * p, float DelayTarget ) { p->DelayTarget = DelayTarget; }
|
||||
void Fpga_ManSetLatchNum( Fpga_Man_t * p, int nLatches ) { p->nLatches = nLatches; }
|
||||
void Fpga_ManSetName( Fpga_Man_t * p, char * pFileName ) { p->pFileName = pFileName; }
|
||||
|
||||
|
|
|
|||
|
|
@ -123,7 +123,8 @@ struct Fpga_ManStruct_t_
|
|||
int fAreaRecovery; // the flag to use area flow as the first parameter
|
||||
int fVerbose; // the verbosiness flag
|
||||
int fSwitching; // minimize the switching activity (instead of area)
|
||||
int nTravIds;
|
||||
int nTravIds; // the counter of traversal IDs
|
||||
float DelayTarget; // the target required times
|
||||
|
||||
// support of choice nodes
|
||||
int nChoiceNodes; // the number of choice nodes
|
||||
|
|
@ -331,7 +332,7 @@ extern float Fpga_MappingGetSwitching( Fpga_Man_t * pMan, Fpga_NodeV
|
|||
extern float Fpga_TimeCutComputeArrival( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
|
||||
extern float Fpga_TimeCutComputeArrival_rec( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
|
||||
extern float Fpga_TimeComputeArrivalMax( Fpga_Man_t * p );
|
||||
extern void Fpga_TimeComputeRequiredGlobal( Fpga_Man_t * p );
|
||||
extern void Fpga_TimeComputeRequiredGlobal( Fpga_Man_t * p, int fFirstTime );
|
||||
extern void Fpga_TimeComputeRequired( Fpga_Man_t * p, float fRequired );
|
||||
extern void Fpga_TimePropagateRequired( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes );
|
||||
extern void Fpga_TimePropagateArrival( Fpga_Man_t * p );
|
||||
|
|
|
|||
|
|
@ -501,7 +501,7 @@ void Fpga_Experiment( Fpga_Man_t * p )
|
|||
AreaBefore = pNode->pCutBest->aFlow;
|
||||
pNode->pCutBest->aFlow = FPGA_FLOAT_LARGE;
|
||||
|
||||
Fpga_TimeComputeRequiredGlobal( p );
|
||||
Fpga_TimeComputeRequiredGlobal( p, 0 );
|
||||
|
||||
vNodesTfo = Fpga_CollectNodeTfo( p, pNode );
|
||||
if ( Fpga_MappingMatchesAreaArray( p, vNodesTfo ) == 0 )
|
||||
|
|
|
|||
|
|
@ -109,9 +109,24 @@ float Fpga_TimeComputeArrivalMax( Fpga_Man_t * p )
|
|||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
void Fpga_TimeComputeRequiredGlobal( Fpga_Man_t * p )
|
||||
void Fpga_TimeComputeRequiredGlobal( Fpga_Man_t * p, int fFirstTime )
|
||||
{
|
||||
p->fRequiredGlo = Fpga_TimeComputeArrivalMax( p );
|
||||
// update the required times according to the target
|
||||
if ( p->DelayTarget != -1 )
|
||||
{
|
||||
if ( p->fRequiredGlo > p->DelayTarget + p->fEpsilon )
|
||||
{
|
||||
if ( fFirstTime )
|
||||
printf( "Cannot meet the target required times (%4.2f). Mapping continues anyway.\n", p->DelayTarget );
|
||||
}
|
||||
else if ( p->fRequiredGlo < p->DelayTarget - p->fEpsilon )
|
||||
{
|
||||
if ( fFirstTime )
|
||||
printf( "Relaxing the required times from (%4.2f) to the target (%4.2f).\n", p->fRequiredGlo, p->DelayTarget );
|
||||
p->fRequiredGlo = p->DelayTarget;
|
||||
}
|
||||
}
|
||||
Fpga_TimeComputeRequired( p, p->fRequiredGlo );
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ static int Fpga_MappingCompareOutputDelay( Fpga_Node_t ** ppNode1, Fpga_Node_t
|
|||
static void Fpga_MappingFindLatest( Fpga_Man_t * p, int * pNodes, int nNodesMax );
|
||||
static void Fpga_DfsLim_rec( Fpga_Node_t * pNode, int Level, Fpga_NodeVec_t * vNodes );
|
||||
static int Fpga_CollectNodeTfo_rec( Fpga_Node_t * pNode, Fpga_Node_t * pPivot, Fpga_NodeVec_t * vVisited, Fpga_NodeVec_t * vTfo );
|
||||
static Fpga_NodeVec_t * Fpga_MappingOrderCosByLevel( Fpga_Man_t * pMan );
|
||||
static Fpga_Man_t * s_pMan = NULL;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -50,9 +51,11 @@ static Fpga_Man_t * s_pMan = NULL;
|
|||
***********************************************************************/
|
||||
Fpga_NodeVec_t * Fpga_MappingDfs( Fpga_Man_t * pMan, int fCollectEquiv )
|
||||
{
|
||||
Fpga_NodeVec_t * vNodes;
|
||||
Fpga_NodeVec_t * vNodes, * vNodesCo;
|
||||
Fpga_Node_t * pNode;
|
||||
int i;
|
||||
// collect the CO nodes by level
|
||||
vNodesCo = Fpga_MappingOrderCosByLevel( pMan );
|
||||
// start the array
|
||||
vNodes = Fpga_NodeVecAlloc( 100 );
|
||||
// collect the PIs
|
||||
|
|
@ -63,12 +66,17 @@ Fpga_NodeVec_t * Fpga_MappingDfs( Fpga_Man_t * pMan, int fCollectEquiv )
|
|||
pNode->fMark0 = 1;
|
||||
}
|
||||
// perform the traversal
|
||||
for ( i = 0; i < pMan->nOutputs; i++ )
|
||||
Fpga_MappingDfs_rec( Fpga_Regular(pMan->pOutputs[i]), vNodes, fCollectEquiv );
|
||||
// for ( i = 0; i < pMan->nOutputs; i++ )
|
||||
// Fpga_MappingDfs_rec( Fpga_Regular(pMan->pOutputs[i]), vNodes, fCollectEquiv );
|
||||
for ( i = 0; i < vNodesCo->nSize; i++ )
|
||||
for ( pNode = vNodesCo->pArray[i]; pNode; pNode = (Fpga_Node_t *)pNode->pData0 )
|
||||
Fpga_MappingDfs_rec( pNode, vNodes, fCollectEquiv );
|
||||
// clean the node marks
|
||||
for ( i = 0; i < vNodes->nSize; i++ )
|
||||
vNodes->pArray[i]->fMark0 = 0;
|
||||
// for ( i = 0; i < pMan->nOutputs; i++ )
|
||||
// Fpga_MappingUnmark_rec( Fpga_Regular(pMan->pOutputs[i]) );
|
||||
Fpga_NodeVecFree( vNodesCo );
|
||||
return vNodes;
|
||||
}
|
||||
|
||||
|
|
@ -930,6 +938,47 @@ void Fpga_ManReportChoices( Fpga_Man_t * pMan )
|
|||
*/
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Returns the array of CO nodes sorted by level.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Fpga_NodeVec_t * Fpga_MappingOrderCosByLevel( Fpga_Man_t * pMan )
|
||||
{
|
||||
Fpga_Node_t * pNode;
|
||||
Fpga_NodeVec_t * vNodes;
|
||||
int i, nLevels;
|
||||
// get the largest node
|
||||
nLevels = Fpga_MappingMaxLevel( pMan );
|
||||
// allocate the array of nodes
|
||||
vNodes = Fpga_NodeVecAlloc( nLevels + 1 );
|
||||
for ( i = 0; i <= nLevels; i++ )
|
||||
Fpga_NodeVecPush( vNodes, NULL );
|
||||
// clean the marks
|
||||
for ( i = 0; i < pMan->nOutputs; i++ )
|
||||
Fpga_Regular(pMan->pOutputs[i])->fMark0 = 0;
|
||||
// put the nodes into the structure
|
||||
for ( i = 0; i < pMan->nOutputs; i++ )
|
||||
{
|
||||
pNode = Fpga_Regular(pMan->pOutputs[i]);
|
||||
if ( pNode->fMark0 )
|
||||
continue;
|
||||
pNode->fMark0 = 1;
|
||||
pNode->pData0 = (char *)Fpga_NodeVecReadEntry( vNodes, pNode->Level );
|
||||
Fpga_NodeVecWriteEntry( vNodes, pNode->Level, pNode );
|
||||
}
|
||||
for ( i = 0; i < pMan->nOutputs; i++ )
|
||||
Fpga_Regular(pMan->pOutputs[i])->fMark0 = 0;
|
||||
return vNodes;
|
||||
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// END OF FILE ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
|
|
|||
|
|
@ -1,373 +0,0 @@
|
|||
/**CFile****************************************************************
|
||||
|
||||
FileName [vecFan.h]
|
||||
|
||||
SystemName [ABC: Logic synthesis and verification system.]
|
||||
|
||||
PackageName [Resizable arrays.]
|
||||
|
||||
Synopsis [Resizable arrays of integers (fanins/fanouts) with memory management.]
|
||||
|
||||
Author [Alan Mishchenko]
|
||||
|
||||
Affiliation [UC Berkeley]
|
||||
|
||||
Date [Ver. 1.0. Started - June 20, 2005.]
|
||||
|
||||
Revision [$Id: vecFan.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
|
||||
|
||||
***********************************************************************/
|
||||
|
||||
#ifndef __VEC_FAN_H__
|
||||
#define __VEC_FAN_H__
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// INCLUDES ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include <stdio.h>
|
||||
#include "extra.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// PARAMETERS ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// BASIC TYPES ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef struct Abc_Fan_t_ Abc_Fan_t;
|
||||
struct Abc_Fan_t_ // 1 word
|
||||
{
|
||||
unsigned iFan : 31; // the ID of the object
|
||||
unsigned fCompl : 1; // the complemented attribute
|
||||
};
|
||||
|
||||
typedef struct Vec_Fan_t_ Vec_Fan_t;
|
||||
struct Vec_Fan_t_
|
||||
{
|
||||
int nCap;
|
||||
int nSize;
|
||||
Abc_Fan_t * pArray;
|
||||
};
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// MACRO DEFINITIONS ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define Vec_FanForEachEntry( vVec, Entry, i ) \
|
||||
for ( i = 0; (i < Vec_FanSize(vVec)) && (((Entry) = Vec_FanEntry(vVec, i)), 1); i++ )
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// FUNCTION DEFINITIONS ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Converts an integer into the simple fanin structure.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
static inline Abc_Fan_t Vec_Int2Fan( int iFan )
|
||||
{
|
||||
return *((Abc_Fan_t *)&iFan);
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis []
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
static inline Abc_Fan_t * Vec_FanArray( Vec_Fan_t * p )
|
||||
{
|
||||
return p->pArray;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis []
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
static inline int Vec_FanSize( Vec_Fan_t * p )
|
||||
{
|
||||
return p->nSize;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis []
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
static inline Abc_Fan_t Vec_FanEntry( Vec_Fan_t * p, int i )
|
||||
{
|
||||
assert( i >= 0 && i < p->nSize );
|
||||
return p->pArray[i];
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis []
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
static inline void Vec_FanWriteEntry( Vec_Fan_t * p, int i, Abc_Fan_t Entry )
|
||||
{
|
||||
assert( i >= 0 && i < p->nSize );
|
||||
p->pArray[i] = Entry;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis []
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
static inline Abc_Fan_t Vec_FanEntryLast( Vec_Fan_t * p )
|
||||
{
|
||||
return p->pArray[p->nSize-1];
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis []
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
static inline void Vec_FanShrink( Vec_Fan_t * p, int nSizeNew )
|
||||
{
|
||||
assert( p->nSize >= nSizeNew );
|
||||
p->nSize = nSizeNew;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis []
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
static inline void Vec_FanClear( Vec_Fan_t * p )
|
||||
{
|
||||
p->nSize = 0;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis []
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
static inline void Vec_FanPush( Extra_MmStep_t * pMemMan, Vec_Fan_t * p, Abc_Fan_t Entry )
|
||||
{
|
||||
if ( p->nSize == p->nCap )
|
||||
{
|
||||
Abc_Fan_t * pArray;
|
||||
int i;
|
||||
|
||||
if ( p->nSize == 0 )
|
||||
p->nCap = 1;
|
||||
pArray = (Abc_Fan_t *)Extra_MmStepEntryFetch( pMemMan, p->nCap * 8 );
|
||||
// pArray = ALLOC( int, p->nCap * 2 );
|
||||
if ( p->pArray )
|
||||
{
|
||||
for ( i = 0; i < p->nSize; i++ )
|
||||
pArray[i] = p->pArray[i];
|
||||
Extra_MmStepEntryRecycle( pMemMan, (char *)p->pArray, p->nCap * 4 );
|
||||
// free( p->pArray );
|
||||
}
|
||||
p->nCap *= 2;
|
||||
p->pArray = pArray;
|
||||
}
|
||||
p->pArray[p->nSize++] = Entry;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Returns the last entry and removes it from the list.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
static inline Abc_Fan_t Vec_FanPop( Vec_Fan_t * p )
|
||||
{
|
||||
assert( p->nSize > 0 );
|
||||
return p->pArray[--p->nSize];
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Find entry.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
static inline int Vec_FanFindEntry( Vec_Fan_t * p, unsigned iFan )
|
||||
{
|
||||
int i;
|
||||
for ( i = 0; i < p->nSize; i++ )
|
||||
if ( p->pArray[i].iFan == iFan )
|
||||
return i;
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Deletes entry.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
static inline int Vec_FanDeleteEntry( Vec_Fan_t * p, unsigned iFan )
|
||||
{
|
||||
/*
|
||||
int i, k, fFound = 0;
|
||||
for ( i = k = 0; i < p->nSize; i++ )
|
||||
{
|
||||
if ( p->pArray[i].iFan == iFan )
|
||||
fFound = 1;
|
||||
else
|
||||
p->pArray[k++] = p->pArray[i];
|
||||
}
|
||||
p->nSize = k;
|
||||
return fFound;
|
||||
*/
|
||||
int i;
|
||||
for ( i = 0; i < p->nSize; i++ )
|
||||
if ( p->pArray[i].iFan == iFan )
|
||||
break;
|
||||
if ( i == p->nSize )
|
||||
return 0;
|
||||
for ( i++; i < p->nSize; i++ )
|
||||
p->pArray[i-1] = p->pArray[i];
|
||||
p->nSize--;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Comparison procedure for two integers.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
static inline int Vec_FanSortCompare1( int * pp1, int * pp2 )
|
||||
{
|
||||
// for some reason commenting out lines (as shown) led to crashing of the release version
|
||||
if ( *pp1 < *pp2 )
|
||||
return -1;
|
||||
if ( *pp1 > *pp2 ) //
|
||||
return 1;
|
||||
return 0; //
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Comparison procedure for two integers.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
static inline int Vec_FanSortCompare2( int * pp1, int * pp2 )
|
||||
{
|
||||
// for some reason commenting out lines (as shown) led to crashing of the release version
|
||||
if ( *pp1 > *pp2 )
|
||||
return -1;
|
||||
if ( *pp1 < *pp2 ) //
|
||||
return 1;
|
||||
return 0; //
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Sorting the entries by their integer value.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
static inline void Vec_FanSort( Vec_Fan_t * p, int fReverse )
|
||||
{
|
||||
if ( fReverse )
|
||||
qsort( (void *)p->pArray, p->nSize, sizeof(int),
|
||||
(int (*)(const void *, const void *)) Vec_FanSortCompare2 );
|
||||
else
|
||||
qsort( (void *)p->pArray, p->nSize, sizeof(int),
|
||||
(int (*)(const void *, const void *)) Vec_FanSortCompare1 );
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// END OF FILE ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue