mirror of https://github.com/YosysHQ/abc.git
Improvements to command 'twoexact'.
This commit is contained in:
Alan Mishchenko
parent
99b33e5dbf
commit
1368a920b9
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@ -144,6 +144,18 @@ static Mini_Aig_t * Mini_AigStart()
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Mini_AigPush( p, MINI_AIG_NULL, MINI_AIG_NULL );
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return p;
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}
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static Mini_Aig_t * Mini_AigStartSupport( int nIns, int nObjsAlloc )
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{
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Mini_Aig_t * p; int i;
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assert( 1+nIns < nObjsAlloc );
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p = MINI_AIG_CALLOC( Mini_Aig_t, 1 );
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p->nCap = 2*nObjsAlloc;
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p->nSize = 2*(1+nIns);
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p->pArray = MINI_AIG_ALLOC( int, p->nCap );
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for ( i = 0; i < p->nSize; i++ )
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p->pArray[i] = MINI_AIG_NULL;
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return p;
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}
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static void Mini_AigStop( Mini_Aig_t * p )
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{
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MINI_AIG_FREE( p->pArray );
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@ -170,6 +182,31 @@ static int Mini_AigAndNum( Mini_Aig_t * p )
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nNodes++;
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return nNodes;
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}
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static int Mini_AigXorNum( Mini_Aig_t * p )
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{
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int i, nNodes = 0;
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Mini_AigForEachAnd( p, i )
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nNodes += p->pArray[2*i] > p->pArray[2*i+1];
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return nNodes;
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}
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static int Mini_AigLevelNum( Mini_Aig_t * p )
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{
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int i, Level = 0;
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int * pLevels = MINI_AIG_CALLOC( int, Mini_AigNodeNum(p) );
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Mini_AigForEachAnd( p, i )
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{
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int Lel0 = pLevels[Mini_AigLit2Var(Mini_AigNodeFanin0(p, i))];
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int Lel1 = pLevels[Mini_AigLit2Var(Mini_AigNodeFanin1(p, i))];
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pLevels[i] = 1 + (Lel0 > Lel1 ? Lel0 : Lel1);
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}
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Mini_AigForEachPo( p, i )
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{
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int Lel0 = pLevels[Mini_AigLit2Var(Mini_AigNodeFanin0(p, i))];
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Level = Level > Lel0 ? Level : Lel0;
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}
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MINI_AIG_FREE( pLevels );
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return Level;
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}
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static void Mini_AigPrintStats( Mini_Aig_t * p )
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{
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printf( "MiniAIG stats: PI = %d PO = %d FF = %d AND = %d\n", Mini_AigPiNum(p), Mini_AigPoNum(p), Mini_AigRegNum(p), Mini_AigAndNum(p) );
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@ -22,6 +22,7 @@
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#include "misc/extra/extra.h"
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#include "misc/util/utilTruth.h"
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#include "sat/glucose/AbcGlucose.h"
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#include "aig/miniaig/miniaig.h"
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ABC_NAMESPACE_IMPL_START
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@ -1459,6 +1460,115 @@ void Exa3_ManExactSynthesis( Bmc_EsPar_t * pPars )
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Abc_PrintTime( 1, "Total runtime", Abc_Clock() - clkTotal );
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Exa_ManIsNormalized( Vec_Wrd_t * vSimsIn, Vec_Wrd_t * vSimsOut )
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{
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int i, Count = 0; word Temp;
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Vec_WrdForEachEntry( vSimsIn, Temp, i )
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if ( Temp & 1 )
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Count++;
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if ( Count )
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printf( "The data for %d divisors are not normalized.\n", Count );
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if ( !(Vec_WrdEntry(vSimsOut, 0) & 1) )
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printf( "The data for the outputs is not normalized.\n", Count );
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// else if ( Count == 0 )
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// printf( "The data is fully normalized.\n" );
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}
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static inline void Exa_ManPrintFanin( int nIns, int nDivs, int iNode, int fComp )
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{
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if ( iNode == 0 )
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printf( " %s", fComp ? "const1" : "const0" );
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else if ( iNode > 0 && iNode <= nIns )
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printf( " %s%c", fComp ? "~" : "", 'a'+iNode-1 );
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else if ( iNode > nIns && iNode < nDivs )
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printf( " %s%c", fComp ? "~" : "", 'A'+iNode-nIns-1 );
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else
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printf( " %s%d", fComp ? "~" : "", iNode );
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}
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void Exa_ManMiniPrint( Mini_Aig_t * p, int nIns )
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{
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int i, nDivs = 1 + Mini_AigPiNum(p), nNodes = Mini_AigAndNum(p);
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printf( "This %d-var function (%d divisors) has %d gates (%d xor) and %d levels:\n",
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nIns, nDivs, nNodes, Mini_AigXorNum(p), Mini_AigLevelNum(p) );
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for ( i = nDivs + nNodes; i < Mini_AigNodeNum(p); i++ )
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{
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int Lit0 = Mini_AigNodeFanin0( p, i );
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printf( "%2d = ", i );
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Exa_ManPrintFanin( nIns, nDivs, Abc_Lit2Var(Lit0), Abc_LitIsCompl(Lit0) );
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printf( "\n" );
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}
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for ( i = nDivs + nNodes - 1; i >= nDivs; i-- )
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{
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int Lit0 = Mini_AigNodeFanin0( p, i );
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int Lit1 = Mini_AigNodeFanin1( p, i );
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printf( "%2d = ", i );
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if ( Lit0 < Lit1 )
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{
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Exa_ManPrintFanin( nIns, nDivs, Abc_Lit2Var(Lit0), Abc_LitIsCompl(Lit0) );
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printf( " &" );
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Exa_ManPrintFanin( nIns, nDivs, Abc_Lit2Var(Lit1), Abc_LitIsCompl(Lit1) );
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}
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else
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{
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Exa_ManPrintFanin( nIns, nDivs, Abc_Lit2Var(Lit1), Abc_LitIsCompl(Lit1) );
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printf( " ^" );
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Exa_ManPrintFanin( nIns, nDivs, Abc_Lit2Var(Lit0), Abc_LitIsCompl(Lit0) );
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}
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printf( "\n" );
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}
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}
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void Exa_ManMiniVerify( Mini_Aig_t * p, Vec_Wrd_t * vSimsIn, Vec_Wrd_t * vSimsOut )
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{
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extern void Extra_BitMatrixTransposeP( Vec_Wrd_t * vSimsIn, int nWordsIn, Vec_Wrd_t * vSimsOut, int nWordsOut );
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int i, nDivs = 1 + Mini_AigPiNum(p), nNodes = Mini_AigAndNum(p);
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int k, nOuts = Mini_AigPoNum(p), nErrors = 0; word Outs[6] = {0};
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Vec_Wrd_t * vSimsIn2 = Vec_WrdStart( 64 );
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assert( nOuts <= 6 );
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assert( Vec_WrdSize(vSimsIn) <= 64 );
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assert( Vec_WrdSize(vSimsIn) == Vec_WrdSize(vSimsOut) );
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Vec_WrdFillExtra( vSimsIn, 64, 0 );
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Extra_BitMatrixTransposeP( vSimsIn, 1, vSimsIn2, 1 );
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assert( Mini_AigNodeNum(p) <= 64 );
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for ( i = nDivs; i < nDivs + nNodes; i++ )
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{
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int Lit0 = Mini_AigNodeFanin0( p, i );
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int Lit1 = Mini_AigNodeFanin1( p, i );
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word Sim0 = Vec_WrdEntry( vSimsIn2, Abc_Lit2Var(Lit0) );
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word Sim1 = Vec_WrdEntry( vSimsIn2, Abc_Lit2Var(Lit1) );
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Sim0 = Abc_LitIsCompl(Lit0) ? ~Sim0 : Sim0;
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Sim1 = Abc_LitIsCompl(Lit1) ? ~Sim1 : Sim1;
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Vec_WrdWriteEntry( vSimsIn2, i, Lit0 < Lit1 ? Sim0 & Sim1 : Sim0 ^ Sim1 );
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}
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for ( i = nDivs + nNodes; i < Mini_AigNodeNum(p); i++ )
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{
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int Lit0 = Mini_AigNodeFanin0( p, i );
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word Sim0 = Vec_WrdEntry( vSimsIn2, Abc_Lit2Var(Lit0) );
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Outs[i - (nDivs + nNodes)] = Abc_LitIsCompl(Lit0) ? ~Sim0 : Sim0;
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}
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Vec_WrdFree( vSimsIn2 );
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for ( i = 0; i < Vec_WrdSize(vSimsOut); i++ )
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{
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int iOutMint = 0;
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for ( k = 0; k < nOuts; k++ )
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if ( (Outs[k] >> i) & 1 )
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iOutMint |= 1 << k;
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nErrors += !Abc_TtGetBit(Vec_WrdEntryP(vSimsOut, i), iOutMint);
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}
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if ( nErrors == 0 )
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printf( "Verification successful. " );
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else
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printf( "Verification failed for %d (out of %d) minterms.\n", nErrors, Vec_WrdSize(vSimsOut) );
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}
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/**Function*************************************************************
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@ -1519,6 +1629,15 @@ Vec_Int_t * Exa4_ManSolve( char * pFileNameIn, char * pFileNameOut, int TimeOut,
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char * pKissat = "kissat";
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#endif
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char Command[1000], * pCommand = (char *)&Command;
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{
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FILE * pFile = fopen( pKissat, "rb" );
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if ( pFile == NULL )
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{
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printf( "Cannot find the Kissat binary \"%s\".\n", pKissat );
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return NULL;
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}
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fclose( pFile );
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}
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if ( TimeOut )
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sprintf( pCommand, "%s --time=%d %s %s > %s", pKissat, TimeOut, fVerboseSolver ? "": "-q", pFileNameIn, pFileNameOut );
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else
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@ -1585,7 +1704,7 @@ int Exa4_ManMarkup( Exa4_Man_t * p )
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if ( p->fVerbose )
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printf( "Variables: Function = %d. Structure = %d. Internal = %d. Total = %d.\n",
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nVars[0], nVars[1], nVars[2], nVars[0] + nVars[1] + nVars[2] );
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if ( 1 )
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if ( 0 )
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{
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for ( j = 0; j < 2; j++ )
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{
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@ -1947,6 +2066,69 @@ void Exa4_ManPrintSolution( Exa4_Man_t * p, Vec_Int_t * vValues, int fFancy )
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printf( "\n" );
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}
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}
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Mini_Aig_t * Exa4_ManMiniAig( Exa4_Man_t * p, Vec_Int_t * vValues, int fFancy )
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{
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int i, k, Compl[MAJ_NOBJS] = {0};
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Mini_Aig_t * pMini = Mini_AigStartSupport( p->nDivs-1, p->nObjs );
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for ( i = p->nDivs; i < p->nDivs + p->nNodes; i++ )
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{
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int iNodes[2] = {0};
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int iVarStart = 1 + 5*(i - p->nDivs);//
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if ( fFancy )
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{
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int Val1 = Vec_IntEntry(vValues, iVarStart);
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int Val2 = Vec_IntEntry(vValues, iVarStart+1);
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int Val3 = Vec_IntEntry(vValues, iVarStart+2);
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int Val4 = Vec_IntEntry(vValues, iVarStart+3);
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int Val5 = Vec_IntEntry(vValues, iVarStart+4);
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for ( k = 0; k < 2; k++ )
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{
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int iNode = Exa4_ManFindFanin( p, vValues, i, !k );
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int fComp = k ? Val1 | Val3 : Val2 | Val3;
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iNodes[k] = Abc_Var2Lit(iNode, fComp ^ Compl[iNode]);
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}
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if ( Val1 || Val2 || Val3 )
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Mini_AigAnd( pMini, iNodes[0], iNodes[1] );
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else
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{
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if ( Val4 )
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Mini_AigOr( pMini, iNodes[0], iNodes[1] );
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else if ( Val5 )
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Mini_AigXorSpecial( pMini, iNodes[0], iNodes[1] );
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else assert( 0 );
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}
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}
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else
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{
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int Val1 = Vec_IntEntry(vValues, iVarStart);
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int Val2 = Vec_IntEntry(vValues, iVarStart+1);
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int Val3 = Vec_IntEntry(vValues, iVarStart+2);
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Compl[i] = Val1 && Val2 && Val3;
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for ( k = 0; k < 2; k++ )
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{
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int iNode = Exa4_ManFindFanin( p, vValues, i, !k );
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int fComp = k ? !Val1 && Val2 && !Val3 : Val1 && !Val2 && !Val3;
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iNodes[k] = Abc_Var2Lit(iNode, fComp ^ Compl[iNode]);
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}
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if ( Val1 && Val2 )
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{
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if ( Val3 )
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Mini_AigOr( pMini, iNodes[0], iNodes[1] );
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else
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Mini_AigXorSpecial( pMini, iNodes[0], iNodes[1] );
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}
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else
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Mini_AigAnd( pMini, iNodes[0], iNodes[1] );
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}
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}
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for ( i = p->nDivs + p->nNodes; i < p->nObjs; i++ )
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{
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int iVar = Exa4_ManFindFanin( p, vValues, i, 0 );
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Mini_AigCreatePo( pMini, Abc_Var2Lit(iVar, Compl[iVar]) );
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}
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assert( p->nObjs == Mini_AigNodeNum(pMini) );
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return pMini;
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}
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/**Function*************************************************************
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@ -1959,26 +2141,33 @@ void Exa4_ManPrintSolution( Exa4_Man_t * p, Vec_Int_t * vValues, int fFancy )
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SeeAlso []
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***********************************************************************/
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void Exa4_ManGenTest( Vec_Wrd_t * vSimsIn, Vec_Wrd_t * vSimsOut, int nIns, int nDivs, int nOuts, int nNodes, int TimeOut, int fOnlyAnd, int fFancy, int fOrderNodes, int fUniqFans, int fVerbose )
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Mini_Aig_t * Exa4_ManGenTest( Vec_Wrd_t * vSimsIn, Vec_Wrd_t * vSimsOut, int nIns, int nDivs, int nOuts, int nNodes, int TimeOut, int fOnlyAnd, int fFancy, int fOrderNodes, int fUniqFans, int fVerbose )
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{
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Mini_Aig_t * pMini = NULL;
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abctime clkTotal = Abc_Clock();
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Vec_Int_t * vValues = NULL;
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char * pFileNameIn = "_temp_.cnf";
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char * pFileNameOut = "_temp_out.cnf";
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Exa4_Man_t * p = Exa4_ManAlloc( vSimsIn, vSimsOut, nIns, nDivs, nOuts, nNodes, fVerbose );
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Exa_ManIsNormalized( vSimsIn, vSimsOut );
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Exa4_ManGenCnf( p, pFileNameIn, fOnlyAnd, fFancy, fOrderNodes, fUniqFans );
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if ( fVerbose )
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printf( "Timeout = %d. OnlyAnd = %d. Fancy = %d. OrderNodes = %d. UniqueFans = %d. Verbose = %d.\n", TimeOut, fOnlyAnd, fFancy, fOrderNodes, fUniqFans, fVerbose );
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if ( fVerbose )
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printf( "CNF with %d variables and %d clauses was dumped into file \"%s\".\n", p->nCnfVars, p->nCnfClauses, pFileNameIn );
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vValues = Exa4_ManSolve( pFileNameIn, pFileNameOut, TimeOut, fVerbose );
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if ( vValues ) Exa4_ManPrintSolution( p, vValues, fFancy );
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if ( vValues ) pMini = Exa4_ManMiniAig( p, vValues, fFancy );
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//if ( vValues ) Exa4_ManPrintSolution( p, vValues, fFancy );
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if ( vValues ) Exa_ManMiniPrint( pMini, p->nIns );
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if ( vValues ) Exa_ManMiniVerify( pMini, vSimsIn, vSimsOut );
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Vec_IntFreeP( &vValues );
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Exa4_ManFree( p );
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Abc_PrintTime( 1, "Total runtime", Abc_Clock() - clkTotal );
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return pMini;
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}
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void Exa_ManExactSynthesis4_( Bmc_EsPar_t * pPars )
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{
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Mini_Aig_t * pMini = NULL;
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int i, m;
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Vec_Wrd_t * vSimsIn = Vec_WrdStart( 8 );
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Vec_Wrd_t * vSimsOut = Vec_WrdStart( 8 );
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@ -1994,12 +2183,14 @@ void Exa_ManExactSynthesis4_( Bmc_EsPar_t * pPars )
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if ( (m >> i) & 1 )
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Abc_TtSetBit( Vec_WrdEntryP(vSimsIn, m), 1+i );
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}
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Exa4_ManGenTest( vSimsIn, vSimsOut, 3, 4, 2, pPars->nNodes, pPars->RuntimeLim, pPars->fOnlyAnd, pPars->fFewerVars, pPars->fOrderNodes, pPars->fUniqFans, pPars->fVerbose );
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pMini = Exa4_ManGenTest( vSimsIn, vSimsOut, 3, 4, 2, pPars->nNodes, pPars->RuntimeLim, pPars->fOnlyAnd, pPars->fFewerVars, pPars->fOrderNodes, pPars->fUniqFans, pPars->fVerbose );
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if ( pMini ) Mini_AigStop( pMini );
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Vec_WrdFree( vSimsIn );
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Vec_WrdFree( vSimsOut );
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}
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void Exa_ManExactSynthesis4( Bmc_EsPar_t * pPars )
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{
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Mini_Aig_t * pMini = NULL;
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int i, m, nMints = 1 << pPars->nVars, fCompl = 0;
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Vec_Wrd_t * vSimsIn = Vec_WrdStart( nMints );
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Vec_Wrd_t * vSimsOut = Vec_WrdStart( nMints );
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@ -2014,7 +2205,8 @@ void Exa_ManExactSynthesis4( Bmc_EsPar_t * pPars )
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Abc_TtSetBit( Vec_WrdEntryP(vSimsIn, m), 1+i );
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}
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assert( Vec_WrdSize(vSimsIn) == (1 << pPars->nVars) );
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Exa4_ManGenTest( vSimsIn, vSimsOut, pPars->nVars, 1+pPars->nVars, 1, pPars->nNodes, pPars->RuntimeLim, pPars->fOnlyAnd, pPars->fFewerVars, pPars->fOrderNodes, pPars->fUniqFans, pPars->fVerbose );
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pMini = Exa4_ManGenTest( vSimsIn, vSimsOut, pPars->nVars, 1+pPars->nVars, 1, pPars->nNodes, pPars->RuntimeLim, pPars->fOnlyAnd, pPars->fFewerVars, pPars->fOrderNodes, pPars->fUniqFans, pPars->fVerbose );
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if ( pMini ) Mini_AigStop( pMini );
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if ( fCompl ) printf( "The resulting circuit, if computed, will be complemented.\n" );
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Vec_WrdFree( vSimsIn );
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Vec_WrdFree( vSimsOut );
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@ -2073,7 +2265,7 @@ int Exa5_ManMarkup( Exa5_Man_t * p )
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if ( p->fVerbose )
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printf( "Variables: Function = %d. Structure = %d. Internal = %d. Total = %d.\n",
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nVars[0], nVars[1], nVars[2], nVars[0] + nVars[1] + nVars[2] );
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if ( 1 )
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if ( 0 )
|
||||
{
|
||||
{
|
||||
printf( " : " );
|
||||
|
|
@ -2263,7 +2455,7 @@ int Exa5_ManGenStart( Exa5_Man_t * p, int fOnlyAnd, int fFancy, int fOrderNodes,
|
|||
Vec_IntPush( vArray, Abc_Var2Lit(p->VarMarks[k][i], 0) );
|
||||
Exa5_ManAddClause( p, Vec_IntArray(vArray), Vec_IntSize(vArray) );
|
||||
if ( fUniqFans )
|
||||
Exa5_ManAddOneHot( p, pLits, nLits );
|
||||
Exa5_ManAddOneHot( p, Vec_IntArray(vArray), Vec_IntSize(vArray) );
|
||||
}
|
||||
Vec_IntFree( vArray );
|
||||
for ( i = p->nDivs + p->nNodes; i < p->nObjs; i++ )
|
||||
|
|
@ -2407,6 +2599,60 @@ void Exa5_ManPrintSolution( Exa5_Man_t * p, Vec_Int_t * vValues, int fFancy )
|
|||
printf( "\n" );
|
||||
}
|
||||
}
|
||||
Mini_Aig_t * Exa5_ManMiniAig( Exa5_Man_t * p, Vec_Int_t * vValues )
|
||||
{
|
||||
Mini_Aig_t * pMini = Mini_AigStartSupport( p->nDivs-1, p->nObjs );
|
||||
int Compl[MAJ_NOBJS] = {0};
|
||||
int Fan0[MAJ_NOBJS] = {0};
|
||||
int Fan1[MAJ_NOBJS] = {0};
|
||||
int Count[MAJ_NOBJS] = {0};
|
||||
int i, k, iObj, iNodes[3];
|
||||
Vec_IntForEachEntry( p->vFans, iObj, i )
|
||||
{
|
||||
if ( iObj == 0 || Vec_IntEntry(vValues, i) == 0 )
|
||||
continue;
|
||||
iNodes[0] = (iObj >> 0) & 0xFF;
|
||||
iNodes[1] = (iObj >> 8) & 0xFF;
|
||||
iNodes[2] = (iObj >> 16) & 0xFF;
|
||||
assert( p->nDivs <= iNodes[2] && iNodes[2] < p->nDivs + p->nNodes );
|
||||
Fan0[iNodes[2]] = iNodes[0];
|
||||
Fan1[iNodes[2]] = iNodes[1];
|
||||
Count[iNodes[2]]++;
|
||||
}
|
||||
assert( p->nDivs == Mini_AigNodeNum(pMini) );
|
||||
for ( i = p->nDivs; i < p->nDivs + p->nNodes; i++ )
|
||||
{
|
||||
int iNodes[2] = {0};
|
||||
int iVarStart = 1 + 3*(i - p->nDivs);//
|
||||
int Val1 = Vec_IntEntry(vValues, iVarStart);
|
||||
int Val2 = Vec_IntEntry(vValues, iVarStart+1);
|
||||
int Val3 = Vec_IntEntry(vValues, iVarStart+2);
|
||||
assert( Count[i] == 1 );
|
||||
Compl[i] = Val1 && Val2 && Val3;
|
||||
for ( k = 0; k < 2; k++ )
|
||||
{
|
||||
int iNode = k ? Fan1[i] : Fan0[i];
|
||||
int fComp = k ? !Val1 && Val2 && !Val3 : Val1 && !Val2 && !Val3;
|
||||
iNodes[k] = Abc_Var2Lit(iNode, fComp ^ Compl[iNode]);
|
||||
}
|
||||
if ( Val1 && Val2 )
|
||||
{
|
||||
if ( Val3 )
|
||||
Mini_AigOr( pMini, iNodes[0], iNodes[1] );
|
||||
else
|
||||
Mini_AigXorSpecial( pMini, iNodes[0], iNodes[1] );
|
||||
}
|
||||
else
|
||||
Mini_AigAnd( pMini, iNodes[0], iNodes[1] );
|
||||
}
|
||||
for ( i = p->nDivs + p->nNodes; i < p->nObjs; i++ )
|
||||
{
|
||||
int iVar = Exa5_ManFindFanin( p, vValues, i );
|
||||
Mini_AigCreatePo( pMini, Abc_Var2Lit(iVar, Compl[iVar]) );
|
||||
}
|
||||
assert( p->nObjs == Mini_AigNodeNum(pMini) );
|
||||
return pMini;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
|
|
@ -2419,26 +2665,33 @@ void Exa5_ManPrintSolution( Exa5_Man_t * p, Vec_Int_t * vValues, int fFancy )
|
|||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
void Exa5_ManGenTest( Vec_Wrd_t * vSimsIn, Vec_Wrd_t * vSimsOut, int nIns, int nDivs, int nOuts, int nNodes, int TimeOut, int fOnlyAnd, int fFancy, int fOrderNodes, int fUniqFans, int fVerbose )
|
||||
Mini_Aig_t * Exa5_ManGenTest( Vec_Wrd_t * vSimsIn, Vec_Wrd_t * vSimsOut, int nIns, int nDivs, int nOuts, int nNodes, int TimeOut, int fOnlyAnd, int fFancy, int fOrderNodes, int fUniqFans, int fVerbose )
|
||||
{
|
||||
abctime clkTotal = Abc_Clock();
|
||||
Mini_Aig_t * pMini = NULL;
|
||||
Vec_Int_t * vValues = NULL;
|
||||
char * pFileNameIn = "_temp_.cnf";
|
||||
char * pFileNameOut = "_temp_out.cnf";
|
||||
Exa5_Man_t * p = Exa5_ManAlloc( vSimsIn, vSimsOut, nIns, nDivs, nOuts, nNodes, fVerbose );
|
||||
Exa_ManIsNormalized( vSimsIn, vSimsOut );
|
||||
Exa5_ManGenCnf( p, pFileNameIn, fOnlyAnd, fFancy, fOrderNodes, fUniqFans );
|
||||
if ( fVerbose )
|
||||
printf( "Timeout = %d. OnlyAnd = %d. Fancy = %d. OrderNodes = %d. UniqueFans = %d. Verbose = %d.\n", TimeOut, fOnlyAnd, fFancy, fOrderNodes, fUniqFans, fVerbose );
|
||||
if ( fVerbose )
|
||||
printf( "CNF with %d variables and %d clauses was dumped into file \"%s\".\n", p->nCnfVars, p->nCnfClauses, pFileNameIn );
|
||||
vValues = Exa4_ManSolve( pFileNameIn, pFileNameOut, TimeOut, fVerbose );
|
||||
if ( vValues ) Exa5_ManPrintSolution( p, vValues, fFancy );
|
||||
if ( vValues ) pMini = Exa5_ManMiniAig( p, vValues );
|
||||
//if ( vValues ) Exa5_ManPrintSolution( p, vValues, fFancy );
|
||||
if ( vValues ) Exa_ManMiniPrint( pMini, p->nIns );
|
||||
if ( vValues ) Exa_ManMiniVerify( pMini, vSimsIn, vSimsOut );
|
||||
Vec_IntFreeP( &vValues );
|
||||
Exa5_ManFree( p );
|
||||
Abc_PrintTime( 1, "Total runtime", Abc_Clock() - clkTotal );
|
||||
return pMini;
|
||||
}
|
||||
void Exa_ManExactSynthesis5( Bmc_EsPar_t * pPars )
|
||||
{
|
||||
Mini_Aig_t * pMini = NULL;
|
||||
int i, m, nMints = 1 << pPars->nVars, fCompl = 0;
|
||||
Vec_Wrd_t * vSimsIn = Vec_WrdStart( nMints );
|
||||
Vec_Wrd_t * vSimsOut = Vec_WrdStart( nMints );
|
||||
|
|
@ -2453,7 +2706,8 @@ void Exa_ManExactSynthesis5( Bmc_EsPar_t * pPars )
|
|||
Abc_TtSetBit( Vec_WrdEntryP(vSimsIn, m), 1+i );
|
||||
}
|
||||
assert( Vec_WrdSize(vSimsIn) == (1 << pPars->nVars) );
|
||||
Exa5_ManGenTest( vSimsIn, vSimsOut, pPars->nVars, 1+pPars->nVars, 1, pPars->nNodes, pPars->RuntimeLim, pPars->fOnlyAnd, pPars->fFewerVars, pPars->fOrderNodes, pPars->fUniqFans, pPars->fVerbose );
|
||||
pMini = Exa5_ManGenTest( vSimsIn, vSimsOut, pPars->nVars, 1+pPars->nVars, 1, pPars->nNodes, pPars->RuntimeLim, pPars->fOnlyAnd, pPars->fFewerVars, pPars->fOrderNodes, pPars->fUniqFans, pPars->fVerbose );
|
||||
if ( pMini ) Mini_AigStop( pMini );
|
||||
if ( fCompl ) printf( "The resulting circuit, if computed, will be complemented.\n" );
|
||||
Vec_WrdFree( vSimsIn );
|
||||
Vec_WrdFree( vSimsOut );
|
||||
|
|
|
|||
Loading…
Reference in New Issue