luke
/
abc
mirror of https://github.com/YosysHQ/abc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Investigating complex miters.

This commit is contained in:
Alan Mishchenko 2022-08-03 10:09:44 -07:00
parent a9237f50ea
commit 132b893921
4 changed files with 185 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

88
src/aig/gia/giaSimBase.c
View File

@ -2706,6 +2706,81 @@ Vec_Ptr_t * Gia_ManPtrWrdReadBin( char * pFileName, int fVerbose )
return p;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Gia_ManProcessBuffs( Gia_Man_t * pHie, Vec_Wrd_t * vSimsH, int nWords, Vec_Mem_t * vStore, Vec_Int_t * vLabels )
{
Vec_Int_t * vPoSigs = Vec_IntAlloc( Gia_ManBufNum(pHie) );
Vec_Int_t * vMap;
Vec_Wec_t * vNodes = Vec_WecStart( Gia_ManBufNum(pHie) );
Gia_Obj_t * pObj; int i, Sig, Value;
Gia_ManForEachBuf( pHie, pObj, i )
{
word * pSim = Vec_WrdEntryP(vSimsH, Gia_ObjId(pHie, pObj)*nWords);
int fCompl = pSim[0] & 1;
if ( fCompl )
Abc_TtNot( pSim, nWords );
Vec_IntPush( vPoSigs, Vec_MemHashInsert(vStore, pSim) );
if ( fCompl )
Abc_TtNot( pSim, nWords );
}
Vec_IntPrint( vPoSigs );
vMap = Vec_IntStartFull( Vec_MemEntryNum(vStore) );
Vec_IntForEachEntry( vPoSigs, Sig, i )
{
assert( Vec_IntEntry(vMap, Sig) == -1 );
Vec_IntWriteEntry( vMap, Sig, i );
}
Vec_IntForEachEntry( vLabels, Sig, i )
{
if ( Sig < 0 )
continue;
Value = Vec_IntEntry(vMap, Sig);
if ( Value == -1 )
continue;
assert( Value >= 0 && Value < Gia_ManBufNum(pHie) );
Vec_WecPush( vNodes, Value, i );
}
Vec_WecPrint( vNodes, 0 );
Vec_WecFree( vNodes );
Vec_IntFree( vMap );
Vec_IntFree( vPoSigs );
return NULL;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ManUpdateCoPhase( Gia_Man_t * pNew, Gia_Man_t * pOld )
{
Gia_Obj_t * pObj; int i;
Gia_ManSetPhase( pNew );
Gia_ManSetPhase( pOld );
Gia_ManForEachCo( pNew, pObj, i )
if ( pObj->fPhase ^ Gia_ManCo(pOld, i)->fPhase )
{
printf( "Updating out %d.\n", i );
Gia_ObjFlipFaninC0( pObj );
}
}
/**Function*************************************************************
Synopsis []
@ -2723,7 +2798,8 @@ void Gia_ManCompareSims( Gia_Man_t * pHie, Gia_Man_t * pFlat, int nWords, int fV
Vec_Wrd_t * vSims = pFlat->vSimsPi = pHie->vSimsPi = Vec_WrdStartRandom( Gia_ManCiNum(pFlat) * nWords );
Vec_Wrd_t * vSims0 = Gia_ManSimPatSim( pFlat );
Vec_Wrd_t * vSims1 = Gia_ManSimPatSim( pHie );
Gia_Obj_t * pObj; int * pSpot, * pSpot2, i, nC0s = 0, nC1s = 0, nUnique = 0, nFound[3] = {0}, nBoundary = 0, nMatched = 0;
Vec_Int_t * vLabels = Vec_IntStartFull( Gia_ManObjNum(pFlat) );
Gia_Obj_t * pObj; int fCompl, Value, * pSpot, * pSpot2, i, nC0s = 0, nC1s = 0, nUnique = 0, nFound[3] = {0}, nBoundary = 0, nMatched = 0;
Vec_Mem_t * vStore = Vec_MemAlloc( nWords, 12 ); // 2^12 N-word entries per page
pFlat->vSimsPi = NULL;
pHie->vSimsPi = NULL;
@ -2739,7 +2815,13 @@ void Gia_ManCompareSims( Gia_Man_t * pHie, Gia_Man_t * pFlat, int nWords, int fV
word * pSim = Vec_WrdEntryP(vSims0, i*nWords);
nC0s += Abc_TtIsConst0(pSim, nWords);
nC1s += Abc_TtIsConst1(pSim, nWords);
Vec_MemHashInsert( vStore, pSim );
fCompl = pSim[0] & 1;
if ( fCompl )
Abc_TtNot( pSim, nWords );
Value = Vec_MemHashInsert( vStore, pSim );
if ( fCompl )
Abc_TtNot( pSim, nWords );
Vec_IntWriteEntry( vLabels, i, Value );
}
nUnique = Vec_MemEntryNum( vStore );
printf( "Simulating %d patterns through the second (flat) AIG leads to %d unique objects (%.2f %% out of %d). Const0 = %d. Const1 = %d.\n",
@ -2765,10 +2847,12 @@ void Gia_ManCompareSims( Gia_Man_t * pHie, Gia_Man_t * pFlat, int nWords, int fV
//if ( Gia_ObjIsBuf(pObj) )
// printf( "%d(%d) ", i, nBoundary-1 );
}
Gia_ManProcessBuffs( pHie, vSims1, nWords, vStore, vLabels );
Vec_MemHashFree( vStore );
Vec_MemFree( vStore );
Vec_WrdFree( vSims0 );
Vec_WrdFree( vSims1 );
Vec_IntFree( vLabels );
printf( "The first (hierarchical) AIG has %d (%.2f %%) matches, %d (%.2f %%) mismatches, including %d (%.2f %%) on the boundary. ",
nMatched, 100.0*nMatched /Abc_MaxInt(1, Gia_ManCandNum(pHie)),

8
src/base/abci/abc.c
View File

@ -50235,6 +50235,14 @@ int Abc_CommandAbc9Test( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Print( -1, "Abc_CommandAbc9Test(): There is no AIG.\n" );
return 1;
}
if ( argc == globalUtilOptind + 1 )
{
extern void Gia_ManUpdateCoPhase( Gia_Man_t * pNew, Gia_Man_t * pOld );
Gia_Man_t * pTemp = Gia_AigerRead( argv[globalUtilOptind], 0, 0, 0 );
Gia_ManUpdateCoPhase( pAbc->pGia, pTemp );
Gia_ManStop( pTemp );
return 0;
}
Abc_FrameUpdateGia( pAbc, Gia_ManPerformNewResub(pAbc->pGia, 100, 6, 1, 1) );
// printf( "AIG in \"%s\" has the sum of output support sizes equal to %d.\n", pAbc->pGia->pSpec, Gia_ManSumTotalOfSupportSizes(pAbc->pGia) );
return 0;

14
src/base/wln/wlnCom.c
View File

@ -330,13 +330,13 @@ usage:
******************************************************************************/
int Abc_CommandCollapse( Abc_Frame_t * pAbc, int argc, char ** argv )
{
extern Gia_Man_t * Rtl_LibCollapse( Rtl_Lib_t * p, char * pTopModule, int fVerbose );
extern Gia_Man_t * Rtl_LibCollapse( Rtl_Lib_t * p, char * pTopModule, int fRev, int fVerbose );
Gia_Man_t * pNew = NULL;
Rtl_Lib_t * pLib = Wln_AbcGetRtl(pAbc);
char * pTopModule = NULL;
int c, fInv = 0, fVerbose = 0;
int c, fInv = 0, fRev = 0, fVerbose = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "Tcvh" ) ) != EOF )
while ( ( c = Extra_UtilGetopt( argc, argv, "Tcrvh" ) ) != EOF )
{
switch ( c )
{
@ -352,6 +352,9 @@ int Abc_CommandCollapse( Abc_Frame_t * pAbc, int argc, char ** argv )
case 'c':
fInv ^= 1;
break;
case 'r':
fRev ^= 1;
break;
case 'v':
fVerbose ^= 1;
break;
@ -366,16 +369,17 @@ int Abc_CommandCollapse( Abc_Frame_t * pAbc, int argc, char ** argv )
printf( "The design is not entered.\n" );
return 1;
}
pNew = Rtl_LibCollapse( pLib, pTopModule, fVerbose );
pNew = Rtl_LibCollapse( pLib, pTopModule, fRev, fVerbose );
if ( fInv )
Gia_ManInvertPos( pNew );
Abc_FrameUpdateGia( pAbc, pNew );
return 0;
usage:
Abc_Print( -2, "usage: %%collapse [-T <module>] [-cvh] <file_name>\n" );
Abc_Print( -2, "usage: %%collapse [-T <module>] [-crvh] <file_name>\n" );
Abc_Print( -2, "\t collapse hierarchical design into an AIG\n" );
Abc_Print( -2, "\t-T : specify the top module of the design [default = none]\n" );
Abc_Print( -2, "\t-c : toggle complementing miter outputs after collapsing [default = %s]\n", fInv? "yes": "no" );
Abc_Print( -2, "\t-r : toggle bit order reversal in the word-level IO [default = %s]\n", fRev? "yes": "no" );
Abc_Print( -2, "\t-v : toggle printing verbose information [default = %s]\n", fVerbose? "yes": "no" );
Abc_Print( -2, "\t-h : print the command usage\n");
return 1;

83
src/base/wln/wlnRead.c
View File

@ -1725,6 +1725,42 @@ int Rtl_NtkInsertSignalRange( Rtl_Ntk_t * p, int Sig, int * pLits, int nLits )
return nBits;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Rtl_NtkRevPermInput( Rtl_Ntk_t * p )
{
Vec_Int_t * vNew = Vec_IntAlloc( 100 ); int b, i, Count = 0;
for ( i = 0; i < p->nInputs; i++ )
{
int Width = Rtl_WireWidth( p, i );
for ( b = 0; b < Width; b++ )
Vec_IntPush( vNew, Count + Width-1-b );
Count += Width;
}
return vNew;
}
Vec_Int_t * Rtl_NtkRevPermOutput( Rtl_Ntk_t * p )
{
Vec_Int_t * vNew = Vec_IntAlloc( 100 ); int b, i, Count = 0;
for ( i = 0; i < p->nOutputs; i++ )
{
int Width = Rtl_WireWidth( p, p->nInputs + i );
for ( b = 0; b < Width; b++ )
Vec_IntPush( vNew, Count + Width-1-b );
Count += Width;
}
return vNew;
}
/**Function*************************************************************
Synopsis []
@ -2693,6 +2729,41 @@ Gia_Man_t * Rtl_ReduceInverse( Rtl_Lib_t * pLib, Gia_Man_t * p )
return pNew;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Gia_ManDupPermIO( Gia_Man_t * p, Vec_Int_t * vPermI, Vec_Int_t * vPermO )
{
Gia_Man_t * pNew;
Gia_Obj_t * pObj;
int i;
assert( Vec_IntSize(vPermI) == Gia_ManCiNum(p) );
assert( Vec_IntSize(vPermO) == Gia_ManCoNum(p) );
pNew = Gia_ManStart( Gia_ManObjNum(p) );
Gia_ManConst0(p)->Value = 0;
Gia_ManForEachCi( p, pObj, i )
Gia_ManCi(p, Vec_IntEntry(vPermI, i))->Value = Gia_ManAppendCi(pNew);
Gia_ManForEachAnd( p, pObj, i )
{
if ( Gia_ObjIsBuf(pObj) )
pObj->Value = Gia_ManAppendBuf( pNew, Gia_ObjFanin0Copy(pObj) );
else
pObj->Value = Gia_ManAppendAnd( pNew, Gia_ObjFanin0Copy(pObj), Gia_ObjFanin1Copy(pObj) );
assert( Abc_Lit2Var(pObj->Value) == i );
}
Gia_ManForEachCo( p, pObj, i )
Gia_ManAppendCo( pNew, Gia_ObjFanin0Copy(Gia_ManCo(p, Vec_IntEntry(vPermO, i))) );
return pNew;
}
/**Function*************************************************************
Synopsis []
@ -2715,7 +2786,7 @@ int Rtl_LibReturnNtk( Rtl_Lib_t * p, char * pModule )
}
return iNtk;
}
Gia_Man_t * Rtl_LibCollapse( Rtl_Lib_t * p, char * pTopModule, int fVerbose )
Gia_Man_t * Rtl_LibCollapse( Rtl_Lib_t * p, char * pTopModule, int fRev, int fVerbose )
{
Gia_Man_t * pGia = NULL;
int NameId = Wln_ReadFindToken( pTopModule, p->pManName );
@ -2733,6 +2804,16 @@ Gia_Man_t * Rtl_LibCollapse( Rtl_Lib_t * p, char * pTopModule, int fVerbose )
Vec_IntPush( vRoots, iNtk );
Rtl_LibBlast2( p, vRoots, 1 );
pGia = Gia_ManDup( pTop->pGia );
if ( fRev )
{
Gia_Man_t * pTemp;
Vec_Int_t * vPermI = Rtl_NtkRevPermInput( pTop );
Vec_Int_t * vPermO = Rtl_NtkRevPermOutput( pTop );
pGia = Gia_ManDupPermIO( pTemp = pGia, vPermI, vPermO );
Vec_IntFree( vPermI );
Vec_IntFree( vPermO );
Gia_ManStop( pTemp );
}
//Gia_AigerWrite( pGia, "temp_miter.aig", 0, 0, 0 );
if ( pTop->pGia->vBarBufs )
pGia->vBarBufs = Vec_IntDup( pTop->pGia->vBarBufs );