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Bug fix in parsing hierarchical BLIF with mapping.

This commit is contained in:
Alan Mishchenko 2019-11-18 22:29:09 +08:00
parent dd5a1f5d30
commit 0d24b4e4ca
2 changed files with 18 additions and 3 deletions
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2
src/aig/gia/giaUtil.c
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@ -2377,6 +2377,8 @@ void Gia_ManDumpFiles( Gia_Man_t * p, int nCexesT, int nCexesV )
Vec_BitFree( vBitX ); Vec_BitFree( vBitX );
Vec_BitFree( vBitY ); Vec_BitFree( vBitY );
Res = 0;
} }
} }

19
src/base/io/ioReadBlifMv.c
View File

@ -1420,8 +1420,8 @@ static int Io_MvParseLineSubckt( Io_MvMod_t * p, char * pLine )
*/ */
if ( pName2 == NULL ) if ( pName2 == NULL )
{ {
Abc_Obj_t * pNode = Abc_NtkCreateNode( p->pNtk ); Abc_Obj_t * pNode = Abc_NtkCreateNodeConst0( p->pNtk );
pNode->pData = Abc_SopRegister( (Mem_Flex_t *)p->pNtk->pManFunc, " 0\n" ); //pNode->pData = Abc_SopRegister( (Mem_Flex_t *)p->pNtk->pManFunc, " 0\n" );
pNet = Abc_NtkFindOrCreateNet( p->pNtk, Abc_ObjNameSuffix(pNode, "abc") ); pNet = Abc_NtkFindOrCreateNet( p->pNtk, Abc_ObjNameSuffix(pNode, "abc") );
Abc_ObjAddFanin( pNet, pNode ); Abc_ObjAddFanin( pNet, pNode );
pTerm = Abc_NtkCreateBi( p->pNtk ); pTerm = Abc_NtkCreateBi( p->pNtk );
@ -2268,12 +2268,25 @@ static int Io_MvParseLineGateBlif( Io_MvMod_t * p, Vec_Ptr_t * vTokens )
} }
// if this is the first line with gate, update the network type // if this is the first line with gate, update the network type
if ( Abc_NtkNodeNum(p->pNtk) == 0 ) if ( Abc_NtkNodeNum(p->pNtk) == 0 && p->pNtk->ntkFunc == ABC_FUNC_SOP )
{ {
assert( p->pNtk->ntkFunc == ABC_FUNC_SOP ); assert( p->pNtk->ntkFunc == ABC_FUNC_SOP );
p->pNtk->ntkFunc = ABC_FUNC_MAP; p->pNtk->ntkFunc = ABC_FUNC_MAP;
Mem_FlexStop( (Mem_Flex_t *)p->pNtk->pManFunc, 0 ); Mem_FlexStop( (Mem_Flex_t *)p->pNtk->pManFunc, 0 );
p->pNtk->pManFunc = pGenlib; p->pNtk->pManFunc = pGenlib;
if ( p->pMan && p->pMan->pDesign && Vec_PtrSize(p->pMan->pDesign->vModules) > 0 )
{
Abc_Ntk_t * pModel; int k;
Vec_PtrForEachEntry( Abc_Ntk_t *, p->pMan->pDesign->vModules, pModel, k )
{
if ( pModel == p->pNtk )
continue;
assert( pModel->ntkFunc == ABC_FUNC_SOP );
pModel->ntkFunc = ABC_FUNC_MAP;
Mem_FlexStop( (Mem_Flex_t *)pModel->pManFunc, 0 );
pModel->pManFunc = pGenlib;
}
}
} }
// reorder the formal inputs to be in the same order as in the gate // reorder the formal inputs to be in the same order as in the gate