mirror of https://github.com/YosysHQ/abc.git
Improvements and tuning of CBA.
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@ -43,9 +43,11 @@ box = array containing model name, instance name, followed by pairs of formal
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- all formal names present in the module description should be listed
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- if an input pin is not driven or an output pin has no fanout, the actual pin name is NULL
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- word-level formal name "a" is written as bit-level names (a[0]. a[1], etc) ordered LSB to MSB
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- primitive names should be given as char*-strings in description of nodes and boxes
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- the boxes can appear in any order (topological order is not expected)
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- in description of nodes and boxes, primitive names should be given as char*-strings ("AndT", "OrT", etc)
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- constant 0/1 nets should be driven by constant nodes having primitive names "Const0T" and "Const1T"
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- primitive modules should not be written, but the list of primitives and formal names should be provided
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- constant 0/1 nets can be specified as char*-strings "NetConst0" and "NetConst1".
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- currently only "boxes" are supported (the array of "nodes" should contain no entries)
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- arrays of input-arrival/output-required times in the module description are optional
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*/
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@ -382,7 +384,6 @@ Vec_Ptr_t * Cba_PtrTransformTest( Vec_Ptr_t * vDes )
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SeeAlso []
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***********************************************************************/
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void Cba_PtrTransformTestTest()
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{
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char * pFileName = "c/hie/dump/1/netlist_1.v";
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@ -462,6 +462,7 @@ Vec_Ptr_t * Cba_PtrDeriveFromCba( Cba_Man_t * p )
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Cba_Ntk_t * pTemp; int i;
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if ( p == NULL )
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return NULL;
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Cba_ManAssignInternNames( p );
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vDes = Vec_PtrAllocExact( 1 + Cba_ManNtkNum(p) );
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Vec_PtrPush( vDes, p->pName );
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Cba_ManForEachNtk( p, pTemp, i )
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