2008-01-31 05:01:00 +01:00
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/**CFile****************************************************************
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FileName [ntlMap.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Netlist representation.]
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Synopsis [Derives mapped network from AIG.]
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Author [Alan Mishchenko]
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Affiliation [UC Berkeley]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: ntlMap.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "ntl.h"
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#include "kit.h"
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2008-03-26 16:01:00 +01:00
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#include "if.h"
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2008-01-31 05:01:00 +01:00
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////////////////////////////////////////////////////////////////////////
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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/**Function*************************************************************
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Synopsis [Allocates mapping for the given AIG.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Vec_Ptr_t * Ntl_MappingAlloc( int nLuts, int nVars )
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{
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char * pMemory;
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Ntl_Lut_t ** pArray;
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int nEntrySize, i;
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nEntrySize = sizeof(Ntl_Lut_t) + sizeof(int) * nVars + sizeof(unsigned) * Aig_TruthWordNum(nVars);
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pArray = (Ntl_Lut_t **)malloc( (sizeof(Ntl_Lut_t *) + nEntrySize) * nLuts );
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pMemory = (char *)(pArray + nLuts);
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memset( pMemory, 0, nEntrySize * nLuts );
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for ( i = 0; i < nLuts; i++ )
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{
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pArray[i] = (Ntl_Lut_t *)pMemory;
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pArray[i]->pFanins = (int *)(pMemory + sizeof(Ntl_Lut_t));
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pArray[i]->pTruth = (unsigned *)(pMemory + sizeof(Ntl_Lut_t) + sizeof(int) * nVars);
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pMemory += nEntrySize;
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}
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return Vec_PtrAllocArray( (void **)pArray, nLuts );
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}
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/**Function*************************************************************
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Synopsis [Derives trivial mapping from the AIG.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Vec_Ptr_t * Ntl_MappingFromAig( Aig_Man_t * p )
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{
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Vec_Ptr_t * vMapping;
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Ntl_Lut_t * pLut;
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Aig_Obj_t * pObj;
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int i, k = 0, nBytes = 4;
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vMapping = Ntl_MappingAlloc( Aig_ManAndNum(p) + (int)(Aig_ManConst1(p)->nRefs > 0), 2 );
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if ( Aig_ManConst1(p)->nRefs > 0 )
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{
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pLut = Vec_PtrEntry( vMapping, k++ );
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pLut->Id = 0;
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pLut->nFanins = 0;
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memset( pLut->pTruth, 0xFF, nBytes );
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}
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Aig_ManForEachNode( p, pObj, i )
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{
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pLut = Vec_PtrEntry( vMapping, k++ );
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pLut->Id = pObj->Id;
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pLut->nFanins = 2;
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pLut->pFanins[0] = Aig_ObjFaninId0(pObj);
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pLut->pFanins[1] = Aig_ObjFaninId1(pObj);
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if ( Aig_ObjFaninC0(pObj) && Aig_ObjFaninC1(pObj) )
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memset( pLut->pTruth, 0x11, nBytes );
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else if ( !Aig_ObjFaninC0(pObj) && Aig_ObjFaninC1(pObj) )
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memset( pLut->pTruth, 0x22, nBytes );
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else if ( Aig_ObjFaninC0(pObj) && !Aig_ObjFaninC1(pObj) )
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memset( pLut->pTruth, 0x44, nBytes );
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else if ( !Aig_ObjFaninC0(pObj) && !Aig_ObjFaninC1(pObj) )
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memset( pLut->pTruth, 0x88, nBytes );
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}
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assert( k == Vec_PtrSize(vMapping) );
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return vMapping;
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}
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/**Function*************************************************************
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Synopsis [Load the network into FPGA manager.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Ntk_ManSetIfParsDefault( If_Par_t * pPars )
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{
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// extern void * Abc_FrameReadLibLut();
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// set defaults
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memset( pPars, 0, sizeof(If_Par_t) );
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// user-controlable paramters
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// pPars->nLutSize = -1;
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pPars->nLutSize = 6;
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pPars->nCutsMax = 8;
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pPars->nFlowIters = 1;
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pPars->nAreaIters = 2;
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pPars->DelayTarget = -1;
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2008-03-26 16:01:00 +01:00
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pPars->Epsilon = (float)0.001;
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2008-01-31 05:01:00 +01:00
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pPars->fPreprocess = 1;
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pPars->fArea = 0;
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pPars->fFancy = 0;
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pPars->fExpRed = 0;
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pPars->fLatchPaths = 0;
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pPars->fEdge = 1;
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pPars->fCutMin = 1;
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pPars->fSeqMap = 0;
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pPars->fVerbose = 1;
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// internal parameters
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pPars->fTruth = 1;
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pPars->nLatches = 0;
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pPars->fLiftLeaves = 0;
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// pPars->pLutLib = Abc_FrameReadLibLut();
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pPars->pLutLib = NULL;
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pPars->pTimesArr = NULL;
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pPars->pTimesArr = NULL;
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pPars->pFuncCost = NULL;
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/*
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if ( pPars->nLutSize == -1 )
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{
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if ( pPars->pLutLib == NULL )
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{
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printf( "The LUT library is not given.\n" );
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return;
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}
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// get LUT size from the library
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pPars->nLutSize = pPars->pLutLib->LutMax;
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}
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*/
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}
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/**Function*************************************************************
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Synopsis [Load the network into FPGA manager.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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If_Man_t * Ntk_ManToIf_old( Aig_Man_t * p, If_Par_t * pPars )
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{
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If_Man_t * pIfMan;
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Aig_Obj_t * pNode;//, * pFanin, * pPrev;
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Vec_Ptr_t * vNodes;
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int i;
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// start the mapping manager and set its parameters
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pIfMan = If_ManStart( pPars );
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// print warning about excessive memory usage
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if ( 1.0 * Aig_ManObjNum(p) * pIfMan->nObjBytes / (1<<30) > 1.0 )
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printf( "Warning: The mapper will allocate %.1f Gb for to represent the subject graph with %d AIG nodes.\n",
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1.0 * Aig_ManObjNum(p) * pIfMan->nObjBytes / (1<<30), Aig_ManObjNum(p) );
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// load the AIG into the mapper
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vNodes = Aig_ManDfsPio( p );
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Vec_PtrForEachEntry( vNodes, pNode, i )
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{
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if ( Aig_ObjIsAnd(pNode) )
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pNode->pData = (Aig_Obj_t *)If_ManCreateAnd( pIfMan,
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If_NotCond( (If_Obj_t *)Aig_ObjFanin0(pNode)->pData, Aig_ObjFaninC0(pNode) ),
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If_NotCond( (If_Obj_t *)Aig_ObjFanin1(pNode)->pData, Aig_ObjFaninC1(pNode) ) );
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else if ( Aig_ObjIsPi(pNode) )
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pNode->pData = If_ManCreateCi( pIfMan );
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else if ( Aig_ObjIsPo(pNode) )
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If_ManCreateCo( pIfMan, If_NotCond( Aig_ObjFanin0(pNode)->pData, Aig_ObjFaninC0(pNode) ) );
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else if ( Aig_ObjIsConst1(pNode) )
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Aig_ManConst1(p)->pData = If_ManConst1( pIfMan );
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else // add the node to the mapper
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assert( 0 );
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// set up the choice node
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// if ( Aig_AigNodeIsChoice( pNode ) )
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// {
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// pIfMan->nChoices++;
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// for ( pPrev = pNode, pFanin = pNode->pData; pFanin; pPrev = pFanin, pFanin = pFanin->pData )
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// If_ObjSetChoice( (If_Obj_t *)pPrev->pData, (If_Obj_t *)pFanin->pData );
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// If_ManCreateChoice( pIfMan, (If_Obj_t *)pNode->pData );
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// }
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}
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Vec_PtrFree( vNodes );
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return pIfMan;
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}
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/**Function*************************************************************
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Synopsis [Load the network into FPGA manager.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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If_Man_t * Ntk_ManToIf( Aig_Man_t * p, If_Par_t * pPars )
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{
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If_Man_t * pIfMan;
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Aig_Obj_t * pNode;//, * pFanin, * pPrev;
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int i;
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// start the mapping manager and set its parameters
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pIfMan = If_ManStart( pPars );
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// print warning about excessive memory usage
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if ( 1.0 * Aig_ManObjNum(p) * pIfMan->nObjBytes / (1<<30) > 1.0 )
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printf( "Warning: The mapper will allocate %.1f Gb for to represent the subject graph with %d AIG nodes.\n",
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1.0 * Aig_ManObjNum(p) * pIfMan->nObjBytes / (1<<30), Aig_ManObjNum(p) );
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// load the AIG into the mapper
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Aig_ManForEachObj( p, pNode, i )
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{
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if ( Aig_ObjIsAnd(pNode) )
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pNode->pData = (Aig_Obj_t *)If_ManCreateAnd( pIfMan,
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If_NotCond( (If_Obj_t *)Aig_ObjFanin0(pNode)->pData, Aig_ObjFaninC0(pNode) ),
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If_NotCond( (If_Obj_t *)Aig_ObjFanin1(pNode)->pData, Aig_ObjFaninC1(pNode) ) );
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else if ( Aig_ObjIsPi(pNode) )
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{
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pNode->pData = If_ManCreateCi( pIfMan );
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((If_Obj_t *)pNode->pData)->Level = pNode->Level;
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if ( pIfMan->nLevelMax < (int)pNode->Level )
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pIfMan->nLevelMax = (int)pNode->Level;
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2008-01-31 05:01:00 +01:00
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}
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else if ( Aig_ObjIsPo(pNode) )
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If_ManCreateCo( pIfMan, If_NotCond( Aig_ObjFanin0(pNode)->pData, Aig_ObjFaninC0(pNode) ) );
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else if ( Aig_ObjIsConst1(pNode) )
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Aig_ManConst1(p)->pData = If_ManConst1( pIfMan );
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else // add the node to the mapper
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assert( 0 );
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// set up the choice node
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// if ( Aig_AigNodeIsChoice( pNode ) )
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// {
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// pIfMan->nChoices++;
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// for ( pPrev = pNode, pFanin = pNode->pData; pFanin; pPrev = pFanin, pFanin = pFanin->pData )
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// If_ObjSetChoice( (If_Obj_t *)pPrev->pData, (If_Obj_t *)pFanin->pData );
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// If_ManCreateChoice( pIfMan, (If_Obj_t *)pNode->pData );
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// }
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}
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return pIfMan;
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}
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/**Function*************************************************************
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Synopsis [Creates the mapped network.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Vec_Ptr_t * Ntk_ManFromIf( Aig_Man_t * p, If_Man_t * pMan )
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{
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Vec_Ptr_t * vIfMap;
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If_Obj_t * pNode, * pLeaf;
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If_Cut_t * pCutBest;
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Vec_Ptr_t * vMapping;
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Vec_Int_t * vIfToAig;
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Aig_Obj_t * pObj;
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Ntl_Lut_t * pLut;
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int * ppLeaves;
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int i, k, nLuts, nLeaves, nWords, nVarsMax;
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// create mapping of If nodes into AIG nodes
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vIfToAig = Vec_IntStart( Aig_ManObjNumMax(p) );
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Vec_IntFill( vIfToAig, Aig_ManObjNumMax(p), -1 );
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Aig_ManForEachObj( p, pObj, i )
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{
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if ( Aig_ObjIsPo(pObj) )
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continue;
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if ( Aig_ObjIsConst1(pObj) && pObj->pData == NULL )
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continue;
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if ( Aig_ObjIsPi(pObj) && pObj->pData == NULL )
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continue;
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pNode = pObj->pData;
|
|
|
|
|
assert( pNode != NULL );
|
|
|
|
|
Vec_IntWriteEntry( vIfToAig, pNode->Id, pObj->Id );
|
|
|
|
|
}
|
|
|
|
|
// create the mapping
|
|
|
|
|
vIfMap = If_ManCollectMappingDirect( pMan );
|
|
|
|
|
nVarsMax = pMan->pPars->nLutSize;
|
|
|
|
|
nWords = Aig_TruthWordNum( nVarsMax );
|
|
|
|
|
vMapping = Ntl_MappingAlloc( Vec_PtrSize(vIfMap) + (int)(Aig_ManConst1(p)->nRefs > 0), nVarsMax );
|
|
|
|
|
nLuts = 0;
|
|
|
|
|
if ( Aig_ManConst1(p)->nRefs > 0 )
|
|
|
|
|
{
|
|
|
|
|
pLut = Vec_PtrEntry( vMapping, nLuts++ );
|
|
|
|
|
pLut->Id = 0;
|
|
|
|
|
pLut->nFanins = 0;
|
|
|
|
|
memset( pLut->pTruth, 0xFF, 4 * nWords );
|
|
|
|
|
}
|
|
|
|
|
Vec_PtrForEachEntry( vIfMap, pNode, i )
|
|
|
|
|
{
|
|
|
|
|
// get the best cut
|
|
|
|
|
pCutBest = If_ObjCutBest(pNode);
|
|
|
|
|
nLeaves = If_CutLeaveNum( pCutBest );
|
|
|
|
|
ppLeaves = If_CutLeaves( pCutBest );
|
|
|
|
|
// fill the LUT
|
|
|
|
|
pLut = Vec_PtrEntry( vMapping, nLuts++ );
|
|
|
|
|
pLut->Id = Vec_IntEntry( vIfToAig, pNode->Id );
|
|
|
|
|
pLut->nFanins = nLeaves;
|
|
|
|
|
If_CutForEachLeaf( pMan, pCutBest, pLeaf, k )
|
|
|
|
|
pLut->pFanins[k] = Vec_IntEntry( vIfToAig, pLeaf->Id );
|
|
|
|
|
// compute the truth table
|
|
|
|
|
memcpy( pLut->pTruth, If_CutTruth(pCutBest), 4 * nWords );
|
|
|
|
|
}
|
|
|
|
|
assert( nLuts == Vec_PtrSize(vMapping) );
|
|
|
|
|
Vec_IntFree( vIfToAig );
|
|
|
|
|
Vec_PtrFree( vIfMap );
|
|
|
|
|
return vMapping;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**Function*************************************************************
|
|
|
|
|
|
|
|
|
|
Synopsis [Interface with the FPGA mapping package.]
|
|
|
|
|
|
|
|
|
|
Description []
|
|
|
|
|
|
|
|
|
|
SideEffects []
|
|
|
|
|
|
|
|
|
|
SeeAlso []
|
|
|
|
|
|
|
|
|
|
***********************************************************************/
|
|
|
|
|
Vec_Ptr_t * Ntl_MappingIf( Ntl_Man_t * pMan, Aig_Man_t * p )
|
|
|
|
|
{
|
|
|
|
|
Vec_Ptr_t * vMapping;
|
|
|
|
|
If_Par_t Pars, * pPars = &Pars;
|
|
|
|
|
If_Man_t * pIfMan;
|
|
|
|
|
// perform FPGA mapping
|
|
|
|
|
Ntk_ManSetIfParsDefault( pPars );
|
|
|
|
|
// set the arrival times
|
|
|
|
|
pPars->pTimesArr = ALLOC( float, Aig_ManPiNum(p) );
|
|
|
|
|
memset( pPars->pTimesArr, 0, sizeof(float) * Aig_ManPiNum(p) );
|
|
|
|
|
// translate into the mapper
|
|
|
|
|
pIfMan = Ntk_ManToIf( p, pPars );
|
|
|
|
|
if ( pIfMan == NULL )
|
|
|
|
|
return NULL;
|
2008-03-26 16:01:00 +01:00
|
|
|
pIfMan->pManTim = Tim_ManDup( pMan->pManTime, 0 );
|
2008-01-31 05:01:00 +01:00
|
|
|
if ( !If_ManPerformMapping( pIfMan ) )
|
|
|
|
|
{
|
|
|
|
|
If_ManStop( pIfMan );
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
// transform the result of mapping into the new network
|
|
|
|
|
vMapping = Ntk_ManFromIf( p, pIfMan );
|
|
|
|
|
If_ManStop( pIfMan );
|
|
|
|
|
if ( vMapping == NULL )
|
|
|
|
|
return NULL;
|
|
|
|
|
return vMapping;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
|
|
|
/// END OF FILE ///
|
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
|
|
|
|
|
