mirror of https://github.com/YosysHQ/abc.git
225 lines
6.7 KiB
C
225 lines
6.7 KiB
C
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/**CFile****************************************************************
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FileName [ioWriteBench.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Command processing package.]
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Synopsis [Procedures to write the network in BENCH format.]
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Author [Alan Mishchenko]
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Affiliation [UC Berkeley]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: ioWriteBench.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "io.h"
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////////////////////////////////////////////////////////////////////////
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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static int Io_WriteBenchOne( FILE * pFile, Abc_Ntk_t * pNtk );
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static int Io_WriteBenchOneNode( FILE * pFile, Abc_Obj_t * pNode );
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static char * Io_BenchNodeName( Abc_Obj_t * pObj, int fPhase );
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static char * Io_BenchNodeNameInv( Abc_Obj_t * pObj );
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFITIONS ///
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////////////////////////////////////////////////////////////////////////
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/**Function*************************************************************
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Synopsis [Writes the network in BENCH format.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Io_WriteBench( Abc_Ntk_t * pNtk, char * pFileName )
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{
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Abc_Ntk_t * pExdc;
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FILE * pFile;
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assert( Abc_NtkIsAig(pNtk) );
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pFile = fopen( pFileName, "w" );
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if ( pFile == NULL )
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{
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fprintf( stdout, "Io_WriteBench(): Cannot open the output file.\n" );
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return 0;
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}
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fprintf( pFile, "# Benchmark \"%s\" written by ABC on %s\n", pNtk->pSpec, Extra_TimeStamp() );
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// write the network
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Io_WriteBenchOne( pFile, pNtk );
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// write EXDC network if it exists
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pExdc = Abc_NtkExdc( pNtk );
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if ( pExdc )
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{
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printf( "Io_WriteBench: EXDC is not written (warning).\n" );
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// fprintf( pFile, "\n" );
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// fprintf( pFile, ".exdc\n" );
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// Io_LogicWriteOne( pFile, pExdc );
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}
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// finalize the file
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fclose( pFile );
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return 1;
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}
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/**Function*************************************************************
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Synopsis [Writes the network in BENCH format.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Io_WriteBenchOne( FILE * pFile, Abc_Ntk_t * pNtk )
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{
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ProgressBar * pProgress;
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Abc_Obj_t * pNode;
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int i;
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assert( Abc_NtkIsLogicSop(pNtk) || Abc_NtkIsAig(pNtk) );
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// write the PIs/POs/latches
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Abc_NtkForEachPi( pNtk, pNode, i )
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fprintf( pFile, "INPUT(%s)\n", Abc_NtkNamePi(pNtk,i) );
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Abc_NtkForEachPo( pNtk, pNode, i )
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fprintf( pFile, "OUTPUT(%s)\n", Abc_NtkNamePo(pNtk,i) );
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Abc_NtkForEachLatch( pNtk, pNode, i )
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fprintf( pFile, "%-11s = DFF(%s)\n",
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Abc_NtkNameLatch(pNtk,i), Abc_NtkNameLatchInput(pNtk,i) );
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// set the node names
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Abc_NtkCleanCopy( pNtk );
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Abc_NtkForEachCi( pNtk, pNode, i )
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pNode->pCopy = (Abc_Obj_t *)Abc_NtkNameCi(pNtk,i);
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// write intervers for COs appearing in negative polarity
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Abc_NtkForEachCi( pNtk, pNode, i )
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{
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if ( Abc_AigNodeIsUsedCompl(pNode) )
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fprintf( pFile, "%-11s = NOT(%s)\n",
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Io_BenchNodeNameInv(pNode),
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Abc_NtkNameCi(pNtk,i) );
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}
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// write internal nodes
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pProgress = Extra_ProgressBarStart( stdout, Abc_NtkNodeNum(pNtk) );
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Abc_NtkForEachNode( pNtk, pNode, i )
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{
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Extra_ProgressBarUpdate( pProgress, i, NULL );
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if ( Abc_NodeIsConst(pNode) )
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continue;
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Io_WriteBenchOneNode( pFile, pNode );
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}
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Extra_ProgressBarStop( pProgress );
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// write buffers for CO
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Abc_NtkForEachCo( pNtk, pNode, i )
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{
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fprintf( pFile, "%-11s = BUFF(%s)\n",
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(i < Abc_NtkPoNum(pNtk))? Abc_NtkNamePo(pNtk,i) :
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Abc_NtkNameLatchInput( pNtk, i-Abc_NtkPoNum(pNtk) ),
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Io_BenchNodeName( Abc_ObjFanin0(pNode), !Abc_ObjFaninC0(pNode) ) );
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}
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Abc_NtkCleanCopy( pNtk );
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return 1;
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}
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/**Function*************************************************************
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Synopsis [Writes the network in BENCH format.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Io_WriteBenchOneNode( FILE * pFile, Abc_Obj_t * pNode )
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{
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assert( Abc_ObjIsNode(pNode) );
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// write the AND gate
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fprintf( pFile, "%-11s", Io_BenchNodeName( pNode, 1 ) );
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fprintf( pFile, " = AND(%s, ", Io_BenchNodeName( Abc_ObjFanin0(pNode), !Abc_ObjFaninC0(pNode) ) );
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fprintf( pFile, "%s)\n", Io_BenchNodeName( Abc_ObjFanin1(pNode), !Abc_ObjFaninC1(pNode) ) );
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// write the inverter if necessary
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if ( Abc_AigNodeIsUsedCompl(pNode) )
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{
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fprintf( pFile, "%-11s = NOT(", Io_BenchNodeName( pNode, 0 ) );
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fprintf( pFile, "%s)\n", Io_BenchNodeName( pNode, 1 ) );
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}
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return 1;
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}
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/**Function*************************************************************
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Synopsis [Returns the name of an internal AIG node.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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char * Io_BenchNodeName( Abc_Obj_t * pObj, int fPhase )
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{
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static char Buffer[500];
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if ( pObj->pCopy ) // PIs and latches
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{
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sprintf( Buffer, "%s%s", (char *)pObj->pCopy, (fPhase? "":"_c") );
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return Buffer;
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}
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assert( Abc_ObjIsNode(pObj) );
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if ( Abc_NodeIsConst(pObj) ) // constant node
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{
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if ( fPhase )
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sprintf( Buffer, "%s", "vdd" );
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else
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sprintf( Buffer, "%s", "gnd" );
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return Buffer;
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}
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// internal nodes
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sprintf( Buffer, "%s%s", Abc_ObjName(pObj), (fPhase? "":"_c") );
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return Buffer;
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}
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/**Function*************************************************************
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Synopsis [Returns the name of an internal AIG node.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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char * Io_BenchNodeNameInv( Abc_Obj_t * pObj )
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{
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static char Buffer[500];
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sprintf( Buffer, "%s%s", Abc_ObjName(pObj), "_c" );
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return Buffer;
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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