mirror of https://github.com/YosysHQ/abc.git
498 lines
17 KiB
C
498 lines
17 KiB
C
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/**CFile****************************************************************
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FileName [abcIf.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Network and node package.]
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Synopsis [Interface with the FPGA mapping package.]
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Author [Alan Mishchenko]
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Affiliation [UC Berkeley]
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Date [Ver. 1.0. Started - November 21, 2006.]
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Revision [$Id: abcIf.c,v 1.00 2006/11/21 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "abc.h"
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#include "if.h"
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#include "kit.h"
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////////////////////////////////////////////////////////////////////////
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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static If_Man_t * Abc_NtkToIf( Abc_Ntk_t * pNtk, If_Par_t * pPars );
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static Abc_Ntk_t * Abc_NtkFromIf( If_Man_t * pIfMan, Abc_Ntk_t * pNtk );
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extern Abc_Obj_t * Abc_NodeFromIf_rec( Abc_Ntk_t * pNtkNew, If_Man_t * pIfMan, If_Obj_t * pIfObj, Vec_Int_t * vCover );
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static Hop_Obj_t * Abc_NodeIfToHop( Hop_Man_t * pHopMan, If_Man_t * pIfMan, If_Obj_t * pIfObj );
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static Vec_Ptr_t * Abc_NtkFindGoodOrder( Abc_Ntk_t * pNtk );
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extern void Abc_NtkBddReorder( Abc_Ntk_t * pNtk, int fVerbose );
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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/**Function*************************************************************
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Synopsis [Interface with the FPGA mapping package.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Abc_Ntk_t * Abc_NtkIf( Abc_Ntk_t * pNtk, If_Par_t * pPars )
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{
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Abc_Ntk_t * pNtkNew;
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If_Man_t * pIfMan;
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assert( Abc_NtkIsStrash(pNtk) );
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// get timing information
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pPars->pTimesArr = Abc_NtkGetCiArrivalFloats(pNtk);
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pPars->pTimesReq = NULL;
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// set the latch paths
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if ( pPars->fLatchPaths && pPars->pTimesArr )
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{
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int c;
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for ( c = 0; c < Abc_NtkPiNum(pNtk); c++ )
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pPars->pTimesArr[c] = -ABC_INFINITY;
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}
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// perform FPGA mapping
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pIfMan = Abc_NtkToIf( pNtk, pPars );
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if ( pIfMan == NULL )
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return NULL;
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if ( !If_ManPerformMapping( pIfMan ) )
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{
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If_ManStop( pIfMan );
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return NULL;
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}
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// transform the result of mapping into the new network
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pNtkNew = Abc_NtkFromIf( pIfMan, pNtk );
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if ( pNtkNew == NULL )
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return NULL;
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If_ManStop( pIfMan );
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// duplicate EXDC
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if ( pNtk->pExdc )
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pNtkNew->pExdc = Abc_NtkDup( pNtk->pExdc );
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// make sure that everything is okay
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if ( !Abc_NtkCheck( pNtkNew ) )
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{
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printf( "Abc_NtkIf: The network check has failed.\n" );
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Abc_NtkDelete( pNtkNew );
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return NULL;
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}
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return pNtkNew;
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}
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/**Function*************************************************************
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Synopsis [Load the network into FPGA manager.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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If_Man_t * Abc_NtkToIf( Abc_Ntk_t * pNtk, If_Par_t * pPars )
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{
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ProgressBar * pProgress;
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If_Man_t * pIfMan;
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Abc_Obj_t * pNode, * pFanin, * pPrev;
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Vec_Ptr_t * vNodes;
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int i;
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assert( Abc_NtkIsStrash(pNtk) );
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// vNodes = Abc_NtkFindGoodOrder( pNtk );
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vNodes = Abc_AigDfs( pNtk, 0, 0 );
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// start the mapping manager and set its parameters
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pIfMan = If_ManStart( pPars );
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// print warning about excessive memory usage
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if ( 1.0 * Abc_NtkObjNum(pNtk) * pIfMan->nObjBytes / (1<<30) > 1.0 )
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printf( "Warning: The mapper will allocate %.1f Gb for to represent the subject graph with %d AIG nodes.\n",
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1.0 * Abc_NtkObjNum(pNtk) * pIfMan->nObjBytes / (1<<30), Abc_NtkObjNum(pNtk) );
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// create PIs and remember them in the old nodes
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Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)If_ManConst1( pIfMan );
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Abc_NtkForEachCi( pNtk, pNode, i )
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{
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pNode->pCopy = (Abc_Obj_t *)If_ManCreateCi( pIfMan );
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//printf( "AIG CI %2d -> IF CI %2d\n", pNode->Id, ((If_Obj_t *)pNode->pCopy)->Id );
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}
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// load the AIG into the mapper
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pProgress = Extra_ProgressBarStart( stdout, Abc_NtkObjNumMax(pNtk) );
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// Abc_AigForEachAnd( pNtk, pNode, i )
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Vec_PtrForEachEntry( vNodes, pNode, i )
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{
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Extra_ProgressBarUpdate( pProgress, i, "Initial" );
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// add the node to the mapper
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pNode->pCopy = (Abc_Obj_t *)If_ManCreateAnd( pIfMan,
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If_NotCond( (If_Obj_t *)Abc_ObjFanin0(pNode)->pCopy, Abc_ObjFaninC0(pNode) ),
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If_NotCond( (If_Obj_t *)Abc_ObjFanin1(pNode)->pCopy, Abc_ObjFaninC1(pNode) ) );
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// set up the choice node
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if ( Abc_AigNodeIsChoice( pNode ) )
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{
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pIfMan->nChoices++;
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for ( pPrev = pNode, pFanin = pNode->pData; pFanin; pPrev = pFanin, pFanin = pFanin->pData )
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If_ObjSetChoice( (If_Obj_t *)pPrev->pCopy, (If_Obj_t *)pFanin->pCopy );
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If_ManCreateChoice( pIfMan, (If_Obj_t *)pNode->pCopy );
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}
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//printf( "AIG node %2d -> IF node %2d\n", pNode->Id, ((If_Obj_t *)pNode->pCopy)->Id );
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}
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Extra_ProgressBarStop( pProgress );
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Vec_PtrFree( vNodes );
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// set the primary outputs without copying the phase
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Abc_NtkForEachCo( pNtk, pNode, i )
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If_ManCreateCo( pIfMan, If_NotCond( (If_Obj_t *)Abc_ObjFanin0(pNode)->pCopy, Abc_ObjFaninC0(pNode) ) );
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return pIfMan;
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}
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/**Function*************************************************************
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Synopsis [Creates the mapped network.]
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Description [Assuming the copy field of the mapped nodes are NULL.]
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Abc_Ntk_t * Abc_NtkFromIf( If_Man_t * pIfMan, Abc_Ntk_t * pNtk )
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{
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ProgressBar * pProgress;
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Abc_Ntk_t * pNtkNew;
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Abc_Obj_t * pNode, * pNodeNew;
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Vec_Int_t * vCover;
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int i, nDupGates;
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// create the new network
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if ( pIfMan->pPars->fUseBdds || pIfMan->pPars->fUseCnfs || pIfMan->pPars->fUseMv )
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pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_BDD );
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else if ( pIfMan->pPars->fUseSops )
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pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_SOP );
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else
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pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_AIG );
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// prepare the mapping manager
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If_ManCleanNodeCopy( pIfMan );
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If_ManCleanCutData( pIfMan );
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// make the mapper point to the new network
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If_ObjSetCopy( If_ManConst1(pIfMan), Abc_NtkCreateNodeConst1(pNtkNew) );
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Abc_NtkForEachCi( pNtk, pNode, i )
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If_ObjSetCopy( If_ManCi(pIfMan, i), pNode->pCopy );
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// process the nodes in topological order
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vCover = Vec_IntAlloc( 1 << 16 );
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pProgress = Extra_ProgressBarStart( stdout, Abc_NtkCoNum(pNtk) );
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Abc_NtkForEachCo( pNtk, pNode, i )
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{
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Extra_ProgressBarUpdate( pProgress, i, "Final" );
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pNodeNew = Abc_NodeFromIf_rec( pNtkNew, pIfMan, If_ObjFanin0(If_ManCo(pIfMan, i)), vCover );
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pNodeNew = Abc_ObjNotCond( pNodeNew, If_ObjFaninC0(If_ManCo(pIfMan, i)) );
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Abc_ObjAddFanin( pNode->pCopy, pNodeNew );
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}
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Extra_ProgressBarStop( pProgress );
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Vec_IntFree( vCover );
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// remove the constant node if not used
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pNodeNew = (Abc_Obj_t *)If_ObjCopy( If_ManConst1(pIfMan) );
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if ( Abc_ObjFanoutNum(pNodeNew) == 0 )
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Abc_NtkDeleteObj( pNodeNew );
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// minimize the node
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if ( pIfMan->pPars->fUseBdds || pIfMan->pPars->fUseCnfs || pIfMan->pPars->fUseMv )
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Abc_NtkSweep( pNtkNew, 0 );
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if ( pIfMan->pPars->fUseBdds )
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Abc_NtkBddReorder( pNtkNew, 0 );
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// decouple the PO driver nodes to reduce the number of levels
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nDupGates = Abc_NtkLogicMakeSimpleCos( pNtkNew, 1 );
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// if ( nDupGates && If_ManReadVerbose(pIfMan) )
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// printf( "Duplicated %d gates to decouple the CO drivers.\n", nDupGates );
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return pNtkNew;
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}
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/**Function*************************************************************
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Synopsis [Derive one node after FPGA mapping.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Abc_Obj_t * Abc_NodeFromIf_rec( Abc_Ntk_t * pNtkNew, If_Man_t * pIfMan, If_Obj_t * pIfObj, Vec_Int_t * vCover )
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{
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Abc_Obj_t * pNodeNew;
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If_Cut_t * pCutBest;
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If_Obj_t * pIfLeaf;
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int i;
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// return if the result if known
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pNodeNew = (Abc_Obj_t *)If_ObjCopy( pIfObj );
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if ( pNodeNew )
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return pNodeNew;
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assert( pIfObj->Type == IF_AND );
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// get the parameters of the best cut
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// create a new node
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pNodeNew = Abc_NtkCreateNode( pNtkNew );
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pCutBest = If_ObjCutBest( pIfObj );
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if ( pIfMan->pPars->fUseCnfs || pIfMan->pPars->fUseMv )
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{
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If_CutForEachLeafReverse( pIfMan, pCutBest, pIfLeaf, i )
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Abc_ObjAddFanin( pNodeNew, Abc_NodeFromIf_rec(pNtkNew, pIfMan, pIfLeaf, vCover) );
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}
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else
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{
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If_CutForEachLeaf( pIfMan, pCutBest, pIfLeaf, i )
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Abc_ObjAddFanin( pNodeNew, Abc_NodeFromIf_rec(pNtkNew, pIfMan, pIfLeaf, vCover) );
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}
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// set the level of the new node
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pNodeNew->Level = Abc_ObjLevelNew( pNodeNew );
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// derive the function of this node
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if ( pIfMan->pPars->fTruth )
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{
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if ( pIfMan->pPars->fUseBdds )
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{
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// transform truth table into the BDD
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pNodeNew->pData = Kit_TruthToBdd( pNtkNew->pManFunc, If_CutTruth(pCutBest), If_CutLeaveNum(pCutBest), 0 ); Cudd_Ref(pNodeNew->pData);
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}
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else if ( pIfMan->pPars->fUseCnfs || pIfMan->pPars->fUseMv )
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{
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// transform truth table into the BDD
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pNodeNew->pData = Kit_TruthToBdd( pNtkNew->pManFunc, If_CutTruth(pCutBest), If_CutLeaveNum(pCutBest), 1 ); Cudd_Ref(pNodeNew->pData);
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}
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else if ( pIfMan->pPars->fUseSops )
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{
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// transform truth table into the SOP
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int RetValue = Kit_TruthIsop( If_CutTruth(pCutBest), If_CutLeaveNum(pCutBest), vCover, 1 );
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assert( RetValue == 0 || RetValue == 1 );
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// check the case of constant cover
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if ( Vec_IntSize(vCover) == 0 || (Vec_IntSize(vCover) == 1 && Vec_IntEntry(vCover,0) == 0) )
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{
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assert( RetValue == 0 );
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pNodeNew->pData = Abc_SopCreateAnd( pNtkNew->pManFunc, If_CutLeaveNum(pCutBest), NULL );
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pNodeNew = (Vec_IntSize(vCover) == 0) ? Abc_NtkCreateNodeConst0(pNtkNew) : Abc_NtkCreateNodeConst1(pNtkNew);
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}
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else
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{
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// derive the AIG for that tree
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pNodeNew->pData = Abc_SopCreateFromIsop( pNtkNew->pManFunc, If_CutLeaveNum(pCutBest), vCover );
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if ( RetValue )
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Abc_SopComplement( pNodeNew->pData );
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}
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}
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else
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{
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extern Hop_Obj_t * Kit_TruthToHop( Hop_Man_t * pMan, unsigned * pTruth, int nVars, Vec_Int_t * vMemory );
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pNodeNew->pData = Kit_TruthToHop( pNtkNew->pManFunc, If_CutTruth(pCutBest), If_CutLeaveNum(pCutBest), vCover );
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}
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// complement the node if the cut was complemented
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if ( pCutBest->fCompl )
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Abc_NodeComplement( pNodeNew );
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}
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else
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pNodeNew->pData = Abc_NodeIfToHop( pNtkNew->pManFunc, pIfMan, pIfObj );
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If_ObjSetCopy( pIfObj, pNodeNew );
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return pNodeNew;
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}
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/**Function*************************************************************
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Synopsis [Recursively derives the truth table for the cut.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Hop_Obj_t * Abc_NodeIfToHop_rec( Hop_Man_t * pHopMan, If_Man_t * pIfMan, If_Obj_t * pIfObj, Vec_Ptr_t * vVisited )
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{
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If_Cut_t * pCut;
|
||
|
|
Hop_Obj_t * gFunc, * gFunc0, * gFunc1;
|
||
|
|
// get the best cut
|
||
|
|
pCut = If_ObjCutBest(pIfObj);
|
||
|
|
// if the cut is visited, return the result
|
||
|
|
if ( If_CutData(pCut) )
|
||
|
|
return If_CutData(pCut);
|
||
|
|
// compute the functions of the children
|
||
|
|
gFunc0 = Abc_NodeIfToHop_rec( pHopMan, pIfMan, pIfObj->pFanin0, vVisited );
|
||
|
|
gFunc1 = Abc_NodeIfToHop_rec( pHopMan, pIfMan, pIfObj->pFanin1, vVisited );
|
||
|
|
// get the function of the cut
|
||
|
|
gFunc = Hop_And( pHopMan, Hop_NotCond(gFunc0, pIfObj->fCompl0), Hop_NotCond(gFunc1, pIfObj->fCompl1) );
|
||
|
|
assert( If_CutData(pCut) == NULL );
|
||
|
|
If_CutSetData( pCut, gFunc );
|
||
|
|
// add this cut to the visited list
|
||
|
|
Vec_PtrPush( vVisited, pCut );
|
||
|
|
return gFunc;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**Function*************************************************************
|
||
|
|
|
||
|
|
Synopsis [Derives the truth table for one cut.]
|
||
|
|
|
||
|
|
Description []
|
||
|
|
|
||
|
|
SideEffects []
|
||
|
|
|
||
|
|
SeeAlso []
|
||
|
|
|
||
|
|
***********************************************************************/
|
||
|
|
Hop_Obj_t * Abc_NodeIfToHop( Hop_Man_t * pHopMan, If_Man_t * pIfMan, If_Obj_t * pIfObj )
|
||
|
|
{
|
||
|
|
If_Cut_t * pCut;
|
||
|
|
Hop_Obj_t * gFunc;
|
||
|
|
If_Obj_t * pLeaf;
|
||
|
|
int i;
|
||
|
|
// get the best cut
|
||
|
|
pCut = If_ObjCutBest(pIfObj);
|
||
|
|
assert( pCut->nLeaves > 1 );
|
||
|
|
// set the leaf variables
|
||
|
|
If_CutForEachLeaf( pIfMan, pCut, pLeaf, i )
|
||
|
|
If_CutSetData( If_ObjCutBest(pLeaf), Hop_IthVar(pHopMan, i) );
|
||
|
|
// recursively compute the function while collecting visited cuts
|
||
|
|
Vec_PtrClear( pIfMan->vTemp );
|
||
|
|
gFunc = Abc_NodeIfToHop_rec( pHopMan, pIfMan, pIfObj, pIfMan->vTemp );
|
||
|
|
// printf( "%d ", Vec_PtrSize(p->vTemp) );
|
||
|
|
// clean the cuts
|
||
|
|
If_CutForEachLeaf( pIfMan, pCut, pLeaf, i )
|
||
|
|
If_CutSetData( If_ObjCutBest(pLeaf), NULL );
|
||
|
|
Vec_PtrForEachEntry( pIfMan->vTemp, pCut, i )
|
||
|
|
If_CutSetData( pCut, NULL );
|
||
|
|
return gFunc;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/**Function*************************************************************
|
||
|
|
|
||
|
|
Synopsis [Comparison for two nodes with the flow.]
|
||
|
|
|
||
|
|
Description []
|
||
|
|
|
||
|
|
SideEffects []
|
||
|
|
|
||
|
|
SeeAlso []
|
||
|
|
|
||
|
|
***********************************************************************/
|
||
|
|
int Abc_ObjCompareFlow( Abc_Obj_t ** ppNode0, Abc_Obj_t ** ppNode1 )
|
||
|
|
{
|
||
|
|
float Flow0 = Abc_Int2Float((int)(*ppNode0)->pCopy);
|
||
|
|
float Flow1 = Abc_Int2Float((int)(*ppNode1)->pCopy);
|
||
|
|
if ( Flow0 > Flow1 )
|
||
|
|
return -1;
|
||
|
|
if ( Flow0 < Flow1 )
|
||
|
|
return 1;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**Function*************************************************************
|
||
|
|
|
||
|
|
Synopsis [Orders AIG nodes so that nodes from larger cones go first.]
|
||
|
|
|
||
|
|
Description []
|
||
|
|
|
||
|
|
SideEffects []
|
||
|
|
|
||
|
|
SeeAlso []
|
||
|
|
|
||
|
|
***********************************************************************/
|
||
|
|
void Abc_NtkFindGoodOrder_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes )
|
||
|
|
{
|
||
|
|
if ( !Abc_ObjIsNode(pNode) )
|
||
|
|
return;
|
||
|
|
assert( Abc_ObjIsNode( pNode ) );
|
||
|
|
// if this node is already visited, skip
|
||
|
|
if ( Abc_NodeIsTravIdCurrent( pNode ) )
|
||
|
|
return;
|
||
|
|
// mark the node as visited
|
||
|
|
Abc_NodeSetTravIdCurrent( pNode );
|
||
|
|
// visit the transitive fanin of the node
|
||
|
|
Abc_NtkFindGoodOrder_rec( Abc_ObjFanin0(pNode), vNodes );
|
||
|
|
Abc_NtkFindGoodOrder_rec( Abc_ObjFanin1(pNode), vNodes );
|
||
|
|
// add the node after the fanins have been added
|
||
|
|
Vec_PtrPush( vNodes, pNode );
|
||
|
|
}
|
||
|
|
|
||
|
|
/**Function*************************************************************
|
||
|
|
|
||
|
|
Synopsis [Orders AIG nodes so that nodes from larger cones go first.]
|
||
|
|
|
||
|
|
Description []
|
||
|
|
|
||
|
|
SideEffects []
|
||
|
|
|
||
|
|
SeeAlso []
|
||
|
|
|
||
|
|
***********************************************************************/
|
||
|
|
Vec_Ptr_t * Abc_NtkFindGoodOrder( Abc_Ntk_t * pNtk )
|
||
|
|
{
|
||
|
|
Vec_Ptr_t * vNodes, * vCos;
|
||
|
|
Abc_Obj_t * pNode, * pFanin0, * pFanin1;
|
||
|
|
float Flow0, Flow1;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
// initialize the flow
|
||
|
|
Abc_AigConst1(pNtk)->pCopy = NULL;
|
||
|
|
Abc_NtkForEachCi( pNtk, pNode, i )
|
||
|
|
pNode->pCopy = NULL;
|
||
|
|
// compute the flow
|
||
|
|
Abc_AigForEachAnd( pNtk, pNode, i )
|
||
|
|
{
|
||
|
|
pFanin0 = Abc_ObjFanin0(pNode);
|
||
|
|
pFanin1 = Abc_ObjFanin1(pNode);
|
||
|
|
Flow0 = Abc_Int2Float((int)pFanin0->pCopy)/Abc_ObjFanoutNum(pFanin0);
|
||
|
|
Flow1 = Abc_Int2Float((int)pFanin1->pCopy)/Abc_ObjFanoutNum(pFanin1);
|
||
|
|
pNode->pCopy = (Abc_Obj_t *)Abc_Float2Int(Flow0 + Flow1+(float)1.0);
|
||
|
|
}
|
||
|
|
// find the flow of the COs
|
||
|
|
vCos = Vec_PtrAlloc( Abc_NtkCoNum(pNtk) );
|
||
|
|
Abc_NtkForEachCo( pNtk, pNode, i )
|
||
|
|
{
|
||
|
|
pNode->pCopy = Abc_ObjFanin0(pNode)->pCopy;
|
||
|
|
// pNode->pCopy = (Abc_Obj_t *)Abc_Float2Int((float)Abc_ObjFanin0(pNode)->Level);
|
||
|
|
Vec_PtrPush( vCos, pNode );
|
||
|
|
}
|
||
|
|
|
||
|
|
// sort nodes in the increasing order of the flow
|
||
|
|
qsort( (Abc_Obj_t **)Vec_PtrArray(vCos), Abc_NtkCoNum(pNtk),
|
||
|
|
sizeof(Abc_Obj_t *), (int (*)(const void *, const void *))Abc_ObjCompareFlow );
|
||
|
|
// verify sorting
|
||
|
|
pFanin0 = Vec_PtrEntry(vCos, 0);
|
||
|
|
pFanin1 = Vec_PtrEntryLast(vCos);
|
||
|
|
assert( Abc_Int2Float((int)pFanin0->pCopy) >= Abc_Int2Float((int)pFanin1->pCopy) );
|
||
|
|
|
||
|
|
// collect the nodes in the topological order from the new array
|
||
|
|
Abc_NtkIncrementTravId( pNtk );
|
||
|
|
vNodes = Vec_PtrAlloc( 100 );
|
||
|
|
Vec_PtrForEachEntry( vCos, pNode, i )
|
||
|
|
{
|
||
|
|
Abc_NtkFindGoodOrder_rec( Abc_ObjFanin0(pNode), vNodes );
|
||
|
|
// printf( "%.2f ", Abc_Int2Float((int)pNode->pCopy) );
|
||
|
|
}
|
||
|
|
Vec_PtrFree( vCos );
|
||
|
|
return vNodes;
|
||
|
|
}
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////
|
||
|
|
/// END OF FILE ///
|
||
|
|
////////////////////////////////////////////////////////////////////////
|
||
|
|
|
||
|
|
|