mirror of https://github.com/YosysHQ/abc.git
417 lines
12 KiB
C
417 lines
12 KiB
C
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/**CFile****************************************************************
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FileName [abcTim.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Network and node package.]
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Synopsis [Testing hierarchy/timing manager.]
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Author [Alan Mishchenko]
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Affiliation [UC Berkeley]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: abcTim.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "base/abc/abc.h"
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#include "aig/gia/giaAig.h"
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#include "misc/tim/tim.h"
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#include "opt/dar/dar.h"
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#include "proof/dch/dch.h"
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ABC_NAMESPACE_IMPL_START
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////////////////////////////////////////////////////////////////////////
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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#define TIM_TEST_BOX_RATIO 30
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// assume that every TIM_TEST_BOX_RATIO'th object is a white box
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static inline int Abc_NodeIsWhiteBox( Abc_Obj_t * pObj ) { assert( Abc_ObjIsNode(pObj) ); return Abc_ObjId(pObj) % TIM_TEST_BOX_RATIO == 0; }
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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/**Function*************************************************************
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Synopsis [Derives one delay table.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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float * Abc_NtkTestTimDelayTableOne( int nInputs, int nOutputs )
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{
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float * pTable;
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int i, k;
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pTable = ABC_ALLOC( float, 3 + nInputs * nOutputs );
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pTable[0] = (float)-1;
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pTable[1] = (float)nInputs;
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pTable[2] = (float)nOutputs;
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for ( i = 0; i < nOutputs; i++ )
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for ( k = 0; k < nInputs; k++ )
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pTable[3 + i * nInputs + k] = 1.0;
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return pTable;
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}
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/**Function*************************************************************
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Synopsis [Derives timing tables for each fanin size.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Vec_Ptr_t * Abc_NtkTestTimDelayTables( int nFaninsMax )
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{
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Vec_Ptr_t * vTables;
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float * pTable;
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int i;
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vTables = Vec_PtrAlloc( nFaninsMax + 1 );
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for ( i = 0; i <= nFaninsMax; i++ )
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{
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// derive delay table
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pTable = Abc_NtkTestTimDelayTableOne( i, 1 );
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// set its table ID
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pTable[0] = (float)Vec_PtrSize(vTables);
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// save in the resulting array
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Vec_PtrPush( vTables, pTable );
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}
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return vTables;
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}
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/**Function*************************************************************
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Synopsis [Derives GIA for the output of the local function of one node.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Abc_NtkTestTimNodeStrash_rec( Gia_Man_t * pGia, Hop_Obj_t * pObj )
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{
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assert( !Hop_IsComplement(pObj) );
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if ( !Hop_ObjIsNode(pObj) || Hop_ObjIsMarkA(pObj) )
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return;
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Abc_NtkTestTimNodeStrash_rec( pGia, Hop_ObjFanin0(pObj) );
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Abc_NtkTestTimNodeStrash_rec( pGia, Hop_ObjFanin1(pObj) );
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pObj->iData = Gia_ManHashAnd( pGia, Hop_ObjChild0CopyI(pObj), Hop_ObjChild1CopyI(pObj) );
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assert( !Hop_ObjIsMarkA(pObj) ); // loop detection
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Hop_ObjSetMarkA( pObj );
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}
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int Abc_NtkTestTimNodeStrash( Gia_Man_t * pGia, Abc_Obj_t * pNode )
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{
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Hop_Man_t * pMan;
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Hop_Obj_t * pRoot;
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Abc_Obj_t * pFanin;
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int i;
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assert( Abc_ObjIsNode(pNode) );
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assert( Abc_NtkIsAigLogic(pNode->pNtk) );
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// get the local AIG manager and the local root node
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pMan = (Hop_Man_t *)pNode->pNtk->pManFunc;
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pRoot = (Hop_Obj_t *)pNode->pData;
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// check the constant case
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if ( Abc_NodeIsConst(pNode) || Hop_Regular(pRoot) == Hop_ManConst1(pMan) )
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return !Hop_IsComplement(pRoot);
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// set elementary variables
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Abc_ObjForEachFanin( pNode, pFanin, i )
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Hop_IthVar(pMan, i)->iData = pFanin->iTemp;
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// strash the AIG of this node
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Abc_NtkTestTimNodeStrash_rec( pGia, Hop_Regular(pRoot) );
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Hop_ConeUnmark_rec( Hop_Regular(pRoot) );
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// return the final node with complement if needed
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return Abc_LitNotCond( Hop_Regular(pRoot)->iData, Hop_IsComplement(pRoot) );
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}
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/**Function*************************************************************
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Synopsis [Collect nodes reachable from this box.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Abc_NtkTestTimCollectCone_rec( Abc_Obj_t * pObj, Vec_Ptr_t * vNodes )
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{
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Abc_Obj_t * pFanin;
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int i;
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if ( Abc_NodeIsTravIdCurrent( pObj ) )
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return;
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Abc_NodeSetTravIdCurrent( pObj );
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if ( Abc_ObjIsCi(pObj) )
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return;
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assert( Abc_ObjIsNode( pObj ) );
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Abc_ObjForEachFanin( pObj, pFanin, i )
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Abc_NtkTestTimCollectCone_rec( pFanin, vNodes );
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Vec_PtrPush( vNodes, pObj );
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}
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Vec_Ptr_t * Abc_NtkTestTimCollectCone( Abc_Ntk_t * pNtk, Abc_Obj_t * pObj )
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{
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Vec_Ptr_t * vCone = Vec_PtrAlloc( 1000 );
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if ( pObj != NULL )
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{
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// collect for one node
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assert( Abc_ObjIsNode(pObj) );
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assert( !Abc_NodeIsTravIdCurrent( pObj ) );
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Abc_NtkTestTimCollectCone_rec( pObj, vCone );
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// remove the node because it is a white box
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Vec_PtrPop( vCone );
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}
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else
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{
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// collect for all COs
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Abc_Obj_t * pObj;
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int i;
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Abc_NtkForEachCo( pNtk, pObj, i )
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Abc_NtkTestTimCollectCone_rec( Abc_ObjFanin0(pObj), vCone );
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}
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return vCone;
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}
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/**Function*************************************************************
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Synopsis [Derives GIA manager together with the hierachy manager.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Gia_Man_t * Abc_NtkTestTimDeriveGia( Abc_Ntk_t * pNtk, int fVerbose )
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{
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Gia_Man_t * pTemp;
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Gia_Man_t * pGia = NULL;
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Tim_Man_t * pTim = NULL;
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Vec_Ptr_t * vNodes, * vCone;
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Abc_Obj_t * pObj, * pFanin;
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int i, k, curPi, curPo, TableID;
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// compute topological order
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vNodes = Abc_NtkDfs( pNtk, 0 );
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// construct GIA
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Abc_NtkCleanCopy( pNtk );
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pGia = Gia_ManStart( Abc_NtkObjNumMax(pNtk) );
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Gia_ManHashAlloc( pGia );
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// create primary inputs
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Abc_NtkForEachCi( pNtk, pObj, i )
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pObj->iTemp = Gia_ManAppendCi(pGia);
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// create internal nodes in a topologic order from white boxes
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Abc_NtkIncrementTravId( pNtk );
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Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
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{
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if ( !Abc_NodeIsWhiteBox(pObj) )
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continue;
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// collect nodes in the DFS order from this box
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vCone = Abc_NtkTestTimCollectCone( pNtk, pObj );
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// perform GIA constructino for these nodes
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Vec_PtrForEachEntry( Abc_Obj_t *, vCone, pFanin, k )
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pFanin->iTemp = Abc_NtkTestTimNodeStrash( pGia, pFanin );
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// create inputs of the box
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Abc_ObjForEachFanin( pObj, pFanin, k )
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Gia_ManAppendCo( pGia, pFanin->iTemp );
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// craete outputs of the box
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pObj->iTemp = Gia_ManAppendCi(pGia);
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if ( fVerbose )
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printf( "White box %7d : Cone = %7d Lit = %7d.\n", Abc_ObjId(pObj), Vec_PtrSize(vCone), pObj->iTemp );
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Vec_PtrFree( vCone );
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}
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// collect node in the DSF from the primary outputs
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vCone = Abc_NtkTestTimCollectCone( pNtk, NULL );
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// perform GIA constructino for these nodes
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Vec_PtrForEachEntry( Abc_Obj_t *, vCone, pFanin, k )
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pObj->iTemp = Abc_NtkTestTimNodeStrash( pGia, pFanin );
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Vec_PtrFree( vCone );
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// create primary outputs
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Abc_NtkForEachCo( pNtk, pObj, i )
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pObj->iTemp = Gia_ManAppendCo( pGia, Abc_ObjFanin0(pObj)->iTemp );
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// finalize GIA
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Gia_ManHashStop( pGia );
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Gia_ManSetRegNum( pGia, 0 );
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// clean up GIA
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pGia = Gia_ManCleanup( pTemp = pGia );
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Gia_ManStop( pTemp );
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//Gia_ManPrint( pGia );
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// construct the timing manager
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pTim = Tim_ManStart( Gia_ManPiNum(pGia), Gia_ManPoNum(pGia) );
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Tim_ManSetDelayTables( pTim, Abc_NtkTestTimDelayTables(Abc_NtkGetFaninMax(pNtk)) );
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// create timing boxes
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curPi = Abc_NtkPiNum( pNtk );
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curPo = 0;
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Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
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{
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if ( !Abc_NodeIsWhiteBox(pObj) )
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continue;
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TableID = Abc_ObjFaninNum(pObj); // in this case, the node size is the ID of its delay table
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Tim_ManCreateBox( pTim, curPo, Abc_ObjFaninNum(pObj), curPi, 1, TableID );
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curPi += 1;
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curPo += Abc_ObjFaninNum(pObj);
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}
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curPo += Abc_NtkPoNum( pNtk );
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assert( curPi == Gia_ManPiNum(pGia) );
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assert( curPo == Gia_ManPoNum(pGia) );
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Vec_PtrFree( vNodes );
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// attach the timing manager
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assert( pGia->pManTime == NULL );
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pGia->pManTime = pTim;
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// return
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return pGia;
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}
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/**Function*************************************************************
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Synopsis [Performs synthesis with or without structural choices.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Gia_Man_t * Abc_NtkTestTimPerformSynthesis( Gia_Man_t * p, int fChoices )
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{
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Gia_Man_t * pGia;
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Aig_Man_t * pNew, * pTemp;
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Dch_Pars_t Pars, * pPars = &Pars;
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Dch_ManSetDefaultParams( pPars );
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pNew = Gia_ManToAig( p, 0 );
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if ( fChoices )
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pNew = Dar_ManChoiceNew( pNew, pPars );
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else
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{
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pNew = Dar_ManCompress2( pTemp = pNew, 1, 1, 1, 0, 0 );
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Aig_ManStop( pTemp );
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}
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pGia = Gia_ManFromAig( pNew );
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Aig_ManStop( pNew );
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return pGia;
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}
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/**Function*************************************************************
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Synopsis [Tests the hierarchy-timing manager.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Abc_NtkTestTimByWritingFile( Gia_Man_t * pGia, char * pFileName )
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{
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Gia_Man_t * pGia2;
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// normalize choices
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if ( Gia_ManWithChoices(pGia) )
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{
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Gia_ManVerifyChoices( pGia );
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Gia_ManReverseClasses( pGia, 0 );
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}
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// write file
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Gia_WriteAiger( pGia, pFileName, 0, 0 );
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// unnormalize choices
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if ( Gia_ManWithChoices(pGia) )
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Gia_ManReverseClasses( pGia, 1 );
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// read file
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pGia2 = Gia_ReadAiger( pFileName, 1, 1 );
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// normalize choices
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if ( Gia_ManWithChoices(pGia2) )
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{
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Gia_ManVerifyChoices( pGia2 );
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Gia_ManReverseClasses( pGia2, 1 );
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}
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// compare resulting managers
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if ( Gia_ManCompare( pGia, pGia2 ) )
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printf( "Verification suceessful.\n" );
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Gia_ManStop( pGia2 );
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}
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/**Function*************************************************************
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Synopsis [Tests construction and serialization.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Abc_NtkTestTim( Abc_Ntk_t * pNtk, int fVerbose )
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{
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int fUseChoices = 1;
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Gia_Man_t * pGia, * pTemp;
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// this test only works for a logic network (for example, network with LUT mapping)
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assert( Abc_NtkIsLogic(pNtk) );
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// make sure local functions of the nodes are in the AIG form
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Abc_NtkToAig( pNtk );
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// create GIA manager (pGia) with hierarhy/timing manager attached (pGia->pManTime)
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// while assuming that some nodes are white boxes (see Abc_NodeIsWhiteBox)
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pGia = Abc_NtkTestTimDeriveGia( pNtk, fVerbose );
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printf( "Created GIA manager for network with %d white boxes.\n", Tim_ManBoxNum(pGia->pManTime) );
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// print the timing manager
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if ( fVerbose )
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Tim_ManPrint( pGia->pManTime );
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// test writing both managers into a file and reading them back
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Abc_NtkTestTimByWritingFile( pGia, "test1.aig" );
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// perform synthesis
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pGia = Abc_NtkTestTimPerformSynthesis( pTemp = pGia, fUseChoices );
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Gia_ManStop( pTemp );
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// test writing both managers into a file and reading them back
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Abc_NtkTestTimByWritingFile( pGia, "test2.aig" );
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Gia_ManStop( pGia );
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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ABC_NAMESPACE_IMPL_END
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