Updated User Documentation (markdown)

User-Documentation.md

@@ -129,9 +129,20 @@ There are counters for the number of correct and wrong read data during the inte
 The simulation also reports the status of the simulation. For example, the report below:
 > [10000 ps]  RD @ (0,   840) -> [10000 ps]  RD @ (0,   848) -> [10000 ps]  RD @ (0,   856) -> [10000 ps]  RD @ (0,   864) -> [10000 ps]  RD @ (0,   872) -> 
 
-The format is [`time_delay`] `command` @ (`bank`, `address`).
+The format is [`time_delay`] `command` @ (`bank`, `address`), so `[10000 ps]  RD @ (0,   840)` means 10000 ps delay before a read command with bank 0 and address 840. Notice how each read command has a delay of 10000 ps or 10 ns from each other, since this has a controller clock of 100 MHz (10 ns clock period) this shows that there are no interruptions between sequential read commands resulting in a very high throughput. 
+
+A short report is also shown in each test section:
+> --------------------------------
+DONE TEST 1: LAST ROW
+Number of Operations: 2304
+Time Started: 363390 ns
+Time Done: 387980 ns
+Average Rate: 10 ns/request
+--------------------------------
+
+This report is after a burst write then burst read. This report means there were 2304 write and read operation, and the average time per request is 10 ns (1 controller clock period of 100 MHz). The average rate is optimal since this is a burst write and read. But for random write and read
+
 
-> [17500 ps] ACT @ (4, 10111) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10381) -> [17500 ps]  WR @ (0,   904) -> [10000 ps]  WR @ (4,   904)
 # Sample Projects
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