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Updated User Documentation (markdown)

Angelo Jacobo 2023-11-15 17:27:52 +08:00
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User-Documentation.md

@ -14,19 +14,21 @@ The recommended way to instantiate this IP is to use the top module `rtl/ddr3_to
| ROW_BITS | width of row address. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Possible values range from `12` to `16`. |
| COL_BITS | width of column address. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Possible values range from `10` to `12`. |
| BA_BITS | width of bank address. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Usual value is `3`. |
| DQ_BITS | device width. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Possible values are `4`, `8`, or `16`. [1] |
| LANES | number of DDR3 device to be controlled. This depends on the DDR3 module used. [1] |
| AUX_WIDTH | width of auxiliary line. Value must be >= 4. [2] |
| DQ_BITS | device width. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Possible values are `4`, `8`, or `16`. <sup>[1]</sup> |
| LANES | number of DDR3 device to be controlled. This depends on the DDR3 module used. <sup>[1]</sup> |
| AUX_WIDTH | width of auxiliary line. Value must be >= 4. <sup>[2]</sup> |
| WB2_ADDR_BITS | width of 2nd wishbone address bus for debugging (only relevant if SECOND_WISHBONE = 1). |
| WB2_DATA_BITS | width of 2nd wishbone data bus for debugging (only relevant if SECOND_WISHBONE = 1). |
| OPT_LOWPOWER | _has no effect yet_ |
| OPT_BUS_ABORT | _has no effect yet_ |
| MICRON_SIM | set to 1 if used in Micron DDR3 model to shorten power-on sequence, otherwise 0. |
| TEST_DATAMASK | set to 1 if datamask needs to be tested on the calibration sequence, otherwise 0. |
| ODELAY_SUPPORTED | set to 1 if ODELAYE2 primitive is supported by the FPGA, otherwise 0. [3]|
| ODELAY_SUPPORTED | set to 1 if ODELAYE2 primitive is supported by the FPGA, otherwise 0. <sup>[3]</sup> |
| SECOND_WISHBONE | set to 1 if 2nd wishbone for debugging is needed , otherwise 0.|
***
After the parameters, connect the ports of the top module to your design. Below are the **ports for clocks and reset**:
| Ports | Function |
| :---: | :--- |
@ -37,6 +39,8 @@ After the parameters, connect the ports of the top module to your design. Below
| i_rst_n | Active-low synchronous reset for the entire DDR3 controller and PHY |
***
Below are the **main wishbone ports**:
| Ports | Function |
@ -51,6 +55,8 @@ Below are the **main wishbone ports**:
| o_wb_ack | Acknowledgement signal. Indicates that a read or write request has been completed. |
| o_wb_data | Data bus for read operations. Similar to `i_wb_data`, the data width for a 4:1 controller is 8 times the DDR3 pins `8`x`DQ_BITS`x`LANES`.
***
Below are the **auxiliary ports** associated with the main wishbone. This is not required for normal operation, but is intended for AXI-interface compatibility *which is not yet available*:
| Ports | Function |
| :---: | :--- |
@ -58,10 +64,12 @@ Below are the **auxiliary ports** associated with the main wishbone. This is not
| o_aux | Request ID line with width of `AUX_WIDTH`. The Request ID is sent back concurrently with the acknowledgement signal. |
**Note:**
***
### Note:
[1]: For x16 DDR3 like in Arty S7, use `DQ_BITS` of 8 and `LANES` of 2.
[2]: The auxiliary line is intended for AXI-interface compatibility but is also utilized in the reset sequence, which is the origin of the minimum required width of 4.
[3]: ODELAYE2 is supported if DDR3 device is connected to an HP (High-Powered) bank of FPGA. HR (High-Rank) bank does not support ODELAYE2 as based on [UG471 7-Series Select Guide (page 134)](https://docs.xilinx.com/v/u/en-US/ug471_7Series_SelectIO).
# Verify Design
# Verify Design