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Updated User Documentation (markdown)

Angelo Jacobo 2023-11-26 10:32:01 +08:00
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User-Documentation.md

@ -112,19 +112,18 @@ Last is the [Symbiyosys Formal Verification](https://symbiyosys.readthedocs.io/e
# Simulation
Import all simulation files under [./testbench](https://github.com/AngeloJacobo/DDR3_Controller/tree/main/testbench) to Vivado then run simulation. The `ddr3_dimm_micron_sim_behav.wcfg` contains the waveform. Shown below are the clocks:
![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/f11afd00-ea17-4669-bebb-9f22e8ae6f6d)
`command_used` shows the command issued at a specific time. As shown below, during reads the `dqs` should toggle and `dq` should have a valid value, else they must be in high-impedance `Z`.
As shown below, `command_used` shows the command issued at a specific time. During reads the `dqs` should toggle and `dq` should have a valid value, else they must be in high-impedance `Z`. Precharge and activate also happens between reads when row addresses are different.
![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/a289066f-2a5c-4d08-9660-a76cf537383a)
A part of internal test is to do alternate write then read consecutively as shown below. The data written must match the data read. `dqs` should also toggle along with the data written and read.
![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/817124fa-43d0-4e9f-94c4-2889614d7c87)
There are counters for the number of correct and wrong read data: `correct_read_data` and `wrong_read_data`. As shown below, the `wrong_read_data` must remain zero while `correct_read_data` must increment until it reaches the maximum (3499 on this example).
![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/06d7b4c0-cd40-4fd1-9bc3-6329237e46e3)