Updated User Documentation (markdown)

User-Documentation.md

@@ -1,5 +1,5 @@
 # Specifications and Brief Description
-This DDR3 controller was originally designed to be used on the [10-Gigabit Ethernet Project](https://github.com/ZipCPU/eth10g) but is now being designed to be a more general memory controller with multiple supported FPGA boards. This is a 4:1 memory controller with configurable timing parameters and mode registers so it can be configured to any DDR3 memory device. The interface is the basic Wishbone.
+This DDR3 controller was originally designed to be used on the [10-Gigabit Ethernet Project](https://github.com/ZipCPU/eth10g) but is now being designed to be a more general memory controller with multiple supported FPGA boards. This is a 4:1 memory controller with configurable timing parameters and mode registers so it can be configured to any DDR3 memory device. The interface is the basic Wishbone. The main usecase now is for the 10-Gigabit Ethernet Project which utilizes this controller for an 8-lane x8 DDR3 module running at 800 MHz DDR.
 
 
 # Getting Started
@@ -175,7 +175,7 @@ The summary under `TEST CALIBRATION` are the results from the **internal** read/
 
 This will run the DDR3 controller at 333 MHz (3 ns clock period) which is the [maximum clock period for Arty-S7](https://digilent.com/reference/programmable-logic/arty-s7/reference-manual). Upload the bitstream to Arty-S7, after around 2 seconds the 4 LEDS should light up.
 
-- The [10Gb Ethernet Switch](https://github.com/ZipCPU/eth10g) project utilizes this DDR3 controller for accessing a single-rank DDR3 module (8 lanes of x8 DDR3).
+- The [10Gb Ethernet Switch](https://github.com/ZipCPU/eth10g) project utilizes this DDR3 controller for accessing a single-rank DDR3 module (8 lanes of x8 DDR3) at DDR3-800 (100 MHz controller and 400 MHz PHY).
 
 # Other Open-Sourced DDR3 Controllers
 (soon...)