Updated User Documentation (markdown)

User-Documentation.md

@@ -3,7 +3,7 @@ This DDR3 controller was originally designed to be used on the [10-Gigabit Ether
 
 This memory controller is optimized to maintain a high data throughput and continuous sequential burst operations. The controller handles the reset sequence, refresh sequence, mode register configuration, bank status tracking, timing delay tracking, command issuing, and the PHY's internal calibration. The PHY's internal calibration handles the bitslip training, read dqs alignment via MPR (read calibration), write dqs alignment via write leveling (write calibration), and also an optional comprehensive read/write test. The internal read/write test include a burst access, random access, and alternating read-write access tests. Only if no error is found on these tests will the calibration end and user can start accessing the wishbone interface. 
 
-This design is formally verified and simulated using the Micron DDR3 model.
+This design is [formally verified](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#lint-and-formal-verification) and [simulated using the Micron DDR3 model](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#simulation).
 
 # Getting Started
 The recommended way to instantiate this IP is to use the top module [`rtl/ddr3_top.v`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/rtl/ddr3_top.v), a template for instantiation is also included in that file. Steps to include this DDR3 memory controller IP is to instantiate design, create the constraint file, then edit the localparams.