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Updated User Documentation (markdown)

Angelo Jacobo 2023-11-25 12:47:05 +08:00
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User-Documentation.md

@ -101,7 +101,11 @@ Disregard these errors as Verilator cannot access the verilog files for Xilinx-e
After Verilator lint is compilation with Yosys, this will show warnings
> Warning: Replacing memory ... with list of registers.
Disregards this kind of warning as it just converts small memory elements in the design into a series of register elements.
After Yosys compilation is Icarus Verilog compilation, this should not show any warning or errors but will display the `Test Functions` to verify that the verilog-functions return the correct values, and `Controller Parameters` to verify the top-level parameters are set properly. Delay values are also shown.
Lastly is the Symbiyosys Formal Verification, this will run the [`ddr3.sby`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/ddr3.sby). These will run multiple verification tasks and will take time (running each task might take 10 mins or so). A summary is shown at the end where all task passed: