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Updated User Documentation (markdown)

Angelo Jacobo 2023-11-15 15:39:53 +08:00
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User-Documentation.md

@ -33,9 +33,22 @@ After the parameters, connect the ports of the top module to your design. Below
| i_ddr3_clk | clock of the DDR3 interface with period of `DDR3_CLK_PERIOD` |
| i_ref_clk | reference clock for IDELAYCTRL primitive with frequency of 200 MHz |
| i_ddr3_clk_90 | clock required only if ODELAY_SUPPORTED = 0, otherwise can be left unconnected. Has a period of `DDR3_CLK_PERIOD` with 90° phase shift. |
| i_rst_n | Active-low reset for the entire DDR3 controller and PHY |
| i_rst_n | Active-low synchronous reset for the entire DDR3 controller and PHY |
Below are the main wishbone ports:
| Ports | Function |
| :---: | :--- |
| i_wb_cyc | Indicates if a bus cycle is active. A high value (1) signifies normal operation, while a low value (0) signals the cancellation of all ongoing transactions. |
| i_wb_stb | Strobe or transfer request signal. It's asserted (set to 1) to request a data transfer. |
| i_wb_we | Write-enable signal. A high value (1) indicates a write operation, and a low value (0) indicates a read operation. |
| i_wb_addr | Address bus. Used to specify the address for the current read or write operation. Formatted as {row, bank, column}. |
| i_wb_data | Data bus for write operations. In a 4:1 controller, the data width is 8 times the data width `DQ_BITS`x`LANES`. |
**Note:**
[1]: For x16 DDR3 like in Arty S7, use `DQ_BITS` of 8 and `LANES` of 2.
[2]: ODELAYE2 is supported if DDR3 device is connected to an HP (High-Powered) bank of FPGA. HR (High-Rank) bank does not support ODELAYE2 as based on [UG471 7-Series Select Guide (page 134)](https://docs.xilinx.com/v/u/en-US/ug471_7Series_SelectIO).
[2]: ODELAYE2 is supported if DDR3 device is connected to an HP (High-Powered) bank of FPGA. HR (High-Rank) bank does not support ODELAYE2 as based on [UG471 7-Series Select Guide (page 134)](https://docs.xilinx.com/v/u/en-US/ug471_7Series_SelectIO).
# Verify Design