Updated User Documentation (markdown)

User-Documentation.md

@@ -1,13 +1,9 @@
 # Specifications and Brief Description
 This DDR3 controller was originally designed to be used on the [10-Gigabit Ethernet Project](https://github.com/ZipCPU/eth10g) but is now being designed to be a more general memory controller with multiple supported FPGA boards. This is a 4:1 memory controller with configurable timing parameters and mode registers so it can be configured to any DDR3 memory device. The interface is the basic Wishbone. The main usecase now is for the 10-Gigabit Ethernet Project which utilizes this controller for an 8-lane x8 DDR3 module running at 800 MHz DDR. 
 
-Controller is optimized to maintain a high data throughput and continuous sequential burst operations. The controller handles the reset sequence, refresh sequence, mode register configuration, bank status tracking, timing delay tracking, command issuing, and the PHY's internal calibration. The PHY's internal calibration handles the bitslip training, read dqs alignment via MPR (read calibration), write dqs alignment via write leveling (write calibration),  
+Controller is optimized to maintain a high data throughput and continuous sequential burst operations. The controller handles the reset sequence, refresh sequence, mode register configuration, bank status tracking, timing delay tracking, command issuing, and the PHY's internal calibration. The PHY's internal calibration handles the bitslip training, read dqs alignment via MPR (read calibration), write dqs alignment via write leveling (write calibration), and also an optional comprehensive read/write test. The internal read/write test include a burst access, random access, and alternating read-write access. Only if no error is found on this comprehensive read/write test will the calibration ends and user can start accessing the wishbone interface. 
 
-The calibration is per-byte
-
-There is also an optional internal test 
-
-Formally verified, simulated using Micron DDR3 model, read/write calibration,
+This design is formally verified and simulated using the Micron DDR3 model.
 
 # Getting Started
 The recommended way to instantiate this IP is to use the top module [`rtl/ddr3_top.v`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/rtl/ddr3_top.v), a template for instantiation is also included in that file. Steps to include this DDR3 memory controller IP is to instantiate design, create the constraint file, then edit the localparams.