Updated User Documentation (markdown)

Angelo Jacobo 2023-11-16 13:20:31 +08:00
parent 3716b7a97a
commit 23232da241
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@ -41,7 +41,7 @@ It is recommended to generate all these clocks from a single PLL or clock-genera
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Below are the **main wishbone ports**:
Next are the **main wishbone ports**:
| Ports | Function |
| :---: | :--- |