UberDDR3/temp.log

run all
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43451402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43453902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43456402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43458902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43461402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43463902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43466402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43468902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43601480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43603980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43606480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43608980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43611480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43613980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43616480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43618980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45552600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45555100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45557600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45560100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45562600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45565100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45567600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45570100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45702600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45705100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45707600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45710100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45712600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45715100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45717600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45720100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46301402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46303902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46306402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46308902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46311402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46313902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46316402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46318902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46451480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46453980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46456480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46458980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46461480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46463980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46466480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46468980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48402600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48405100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48407600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48410100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48412600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48415100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48417600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48420100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48552600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48555100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48557600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48560100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48562600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48565100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48567600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48570100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49151402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49153902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49156402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49158902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49161402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49163902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49166402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49168902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49301480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49303980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49306480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49308980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49311480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49313980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49316480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49318980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51252600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51255100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51257600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51260100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51262600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51265100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51267600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51270100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51402600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51405100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51407600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51410100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51412600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51415100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51417600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51420100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52001402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52003902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52006402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52008902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52011402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52013902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52016402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52018902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52151480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52153980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52156480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52158980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52161480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52163980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52166480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52168980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54102600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54105100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54107600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54110100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54112600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54115100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54117600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54120100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54252600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54255100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54257600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54260100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54262600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54265100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54267600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54270100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54851402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54853902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54856402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54858902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54861402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54863902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54866402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54868902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55001480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55003980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55006480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55008980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55011480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55013980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55016480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55018980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56952600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56955100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56957600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56960100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56962600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56965100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56967600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56970100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57102600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57105100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57107600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57110100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57112600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57115100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57117600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57120100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57701402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57703902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57706402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57708902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57711402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57713902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57716402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57718902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57851480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57853980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57856480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57858980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57861480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57863980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57866480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57868980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59802600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59805100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59807600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59810100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59812600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59815100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59817600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59820100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59952600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59955100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59957600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59960100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59962600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59965100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59967600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59970100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60401350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60403850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60406350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60408850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60411350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60413850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60416350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60418850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60551350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60551402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60553850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60553902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60556350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60556402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60558850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60558902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60561350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60561402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60563850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60563902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60566350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60566402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60568850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60568902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60701350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60701480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60703850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60703980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60706350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60706480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60708850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60708980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60711350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60711480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60713850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60713980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60716350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60716480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60718850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60718980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60851350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60853850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60856350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60858850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60861350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60863850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60866350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60868850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61001350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61003850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61006350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61008850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61011350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61013850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61016350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61018850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61151350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61153850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61156350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61158850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61161350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61163850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61166350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61168850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61301350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61303850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61306350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61308850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61311350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61313850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61316350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61318850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61451350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61453850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61456350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61458850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61461350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61463850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61466350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61468850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61601350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61603850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61606350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61608850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61611350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61613850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61616350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61618850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61751350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61753850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61756350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61758850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61761350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61763850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61766350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61768850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61901350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61903850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61906350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61908850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61911350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61913850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61916350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61918850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62051350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62053850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62056350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62058850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62061350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62063850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62066350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62068850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62201350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62203850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62206350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62208850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62211350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62213850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62216350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62218850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62351350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62353850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62356350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62358850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62361350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62363850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62366350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62368850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62501350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62503850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62506350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62508850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62511350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62513850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62516350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62518850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62651350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62652600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62653850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62655100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62656350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62657600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62658850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62660100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62661350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62662600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62663850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62665100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62666350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62667600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62668850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62670100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62801350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62802600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62803850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62805100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62806350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62807600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62808850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62810100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62811350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62812600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62813850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62815100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62816350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62817600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62818850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62820100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62951350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62952650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62953850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62955150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62956350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62957650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62958850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62960150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62961350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62963850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62966350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62968850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63101350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63102650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63103850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63105150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63106350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63107650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63108850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63110150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63111350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63113850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63116350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63118850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63251350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63252650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63253850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63255150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63256350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63257650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63258850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63260150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63261350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63263850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63266350.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63268850.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63401402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63402650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63403902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63405150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63406402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63407650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63408902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63410150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63411402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63413902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63416402.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63418902.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63551480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63552650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63553980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63555150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63556480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63557650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63558980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63560150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63561480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63563980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63566480.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63568980.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63702650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63705150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63707650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63710150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63852650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63855150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63857650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63860150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64002650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64005150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64007650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64010150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64152650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64155150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64157650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64160150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64302650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64305150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64307650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64310150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64452650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64455150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64457650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64460150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64602650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64605150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64607650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64610150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64752650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64755150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64757650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64760150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64902650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64905150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64907650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64910150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65052650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65055150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65057650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65060150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65202650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65205150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65207650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65210150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65352650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65355150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65357650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65360150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65502600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65502650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65505100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65505150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65507600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65507650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65510100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65510150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65512600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65515100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65517600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65520100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65652600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65652650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65655100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65655150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65657600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65657650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65660100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65660150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65662600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65665100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65667600.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65670100.0 ps WARNING: tWLH violation on DQS bit           0 positive edge.   Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit  0 positive edge.  Indeterminate CK capture is possible.
Write: Address = 0, Data = 800fd000800ec200800db400800ca600800b9800800a8c0080097e00800870008007620080065400800546008004380080032a0080021c0080010e0012153524
Write: Address = 1, Data = 8020ac00801fa000801e9200801d8400801c7600801b6800801a5a0080194c0080183e00801730008016220080151600801408008012fa008011ec008010de00
Write: Address = 2, Data = 80318a0080307c00802f6e00802e6000802d5200802c4400802b3600802a2a0080291c0080280e00802700008025f2008024e4008023d6008022c8008021ba00
Write: Address = 3, Data = 804266008041580080404a00803f3e00803e3000803d2200803c1400803b06008039f8008038ea008037dc008036ce008035c0008034b4008033a60080329800
Write: Address = 4, Data = 80534400805236008051280080501a00804f0c00804dfe00804cf000804be200804ad4008049c8008048ba008047ac0080469e00804590008044820080437400
Write: Address = 5, Data = 8064200080631200806204008060f600805fe800805edc00805dce00805cc000805bb200805aa400805996008058880080577a0080566c0080555e0080545200
Write: Address = 6, Data = 8074fc008073f0008072e2008071d4008070c600806fb800806eaa00806d9c00806c8e00806b8000806a7200806966008068580080674a0080663c0080652e00
Write: Address = 7, Data = 8085da018084cc018083be018082b0018081a20180809401807f8600807e7a00807d6c00807c5e00807b5000807a420080793400807826008077180080760a00
Write: Address = 8, Data = 8096b6018095a80180949a0180938e01809280018091720180906401808f5601808e4801808d3a01808c2c01808b1e01808a1001808904018087f6018086e801
Write: Address = 9, Data = 80a7940180a6860180a5780180a46a0180a35c0180a24e0180a1400180a03201809f2401809e1801809d0a01809bfc01809aee018099e0018098d2018097c401
Write: Address = 10, Data = 80b8700180b7620180b6540180b5460180b4380180b32c0180b21e0180b1100180b0020180aef40180ade60180acd80180abca0180aabc0180a9ae0180a8a201
Write: Address = 11, Data = 80c94c0180c8400180c7320180c6240180c5160180c4080180c2fa0180c1ec0180c0de0180bfd00180bec20180bdb60180bca80180bb9a0180ba8c0180b97e01
Write: Address = 12, Data = 80da2a0180d91c0180d80e0180d7000180d5f20180d4e40180d3d60180d2ca0180d1bc0180d0ae0180cfa00180ce920180cd840180cc760180cb680180ca5a01
Write: Address = 13, Data = 80eb060180e9f80180e8ea0180e7de0180e6d00180e5c20180e4b40180e3a60180e2980180e18a0180e07c0180df6e0180de600180dd540180dc460180db3801
Write: Address = 14, Data = 80fbe40180fad60180f9c80180f8ba0180f7ac0180f69e0180f5900180f4820180f3740180f2680180f15a0180f04c0180ef3e0180ee300180ed220180ec1401
Write: Address = 15, Data = 810cc002810bb202810aa4028109960281088a0281077c0281066e02810560028104520281034402810236028101280281001a0280ff0c0180fdfe0180fcf201
Write: Address = 16, Data = 811d9e02811c9002811b8202811a7402811966028118580281174a0281163c0281152e028114200281131402811206028110f802810fea02810edc02810dce02
Write: Address = 17, Data = 812e7a02812d6c02812c5e02812b5002812a4202812934028128280281271a0281260c028124fe028123f0028122e2028121d4028120c602811fb802811eaa02
Write: Address = 18, Data = 813f5602813e4802813d3c02813c2e02813b2002813a1202813904028137f6028136e8028135da028134cc028133be028132b2028131a40281309602812f8802
Write: Address = 19, Data = 81503402814f2602814e1802814d0a02814bfc02814aee028149e0028148d2028147c6028146b8028145aa0281449c0281438e02814280028141720281406402
Write: Address = 20, Data = 8161100281600202815ef402815de602815cda02815bcc02815abe028159b0028158a20281579402815686028155780281546a0281535c028152500281514202
Write: Address = 21, Data = 8171ee028170e002816fd202816ec402816db602816ca802816b9a02816a8c0281697e028168700281676402816656028165480281643a0281632c0281621e02
Write: Address = 22, Data = 8182ca038181bc038180ae03817fa002817e9202817d8402817c7802817b6a02817a5c0281794e0281784002817732028176240281751602817408028172fa02
Write: Address = 23, Data = 8193a6038192980381918c0381907e03818f7003818e6203818d5403818c4603818b3803818a2a0381891c0381880e03818702038185f4038184e6038183d803
Write: Address = 24, Data = 81a4840381a3760381a2680381a15a0381a04c03819f3e03819e3003819d2203819c1603819b08038199fa038198ec038197de038196d0038195c2038194b403
Write: Address = 25, Data = 81b5600381b4520381b3440381b2360381b12a0381b01c0381af0e0381ae000381acf20381abe40381aad60381a9c80381a8ba0381a7ac0381a6a00381a59203
Write: Address = 26, Data = 81c63e0381c5300381c4220381c3140381c2060381c0f80381bfea0381bedc0381bdce0381bcc00381bbb40381baa60381b9980381b88a0381b77c0381b66e03
Write: Address = 27, Data = 81d71a0381d60c0381d4fe0381d3f00381d2e20381d1d40381d0c80381cfba0381ceac0381cd9e0381cc900381cb820381ca740381c9660381c8580381c74a03
Write: Address = 28, Data = 81e7f60381e6e80381e5dc0381e4ce0381e3c00381e2b20381e1a40381e0960381df880381de7a0381dd6c0381dc5e0381db520381da440381d9360381d82803
Write: Address = 29, Data = 81f8d40381f7c60381f6b80381f5aa0381f49c0381f38e0381f2800381f1720381f0660381ef580381ee4a0381ed3c0381ec2e0381eb200381ea120381e90403
Write: Address = 30, Data = 8209b0048208a204820794048206860482057a0482046c0482035e0482025004820142048200340481ff260381fe180381fd0a0381fbfc0381faf00381f9e203
Write: Address = 31, Data = 821a8e04821980048218720482176404821656048215480482143a0482132c0482121e048211100482100404820ef604820de804820cda04820bcc04820abe04
Write: Address = 32, Data = 822b6a04822a5c0482294e048228400482273204822626048225180482240a048222fc048221ee048220e004821fd204821ec404821db604821ca804821b9c04
Write: Address = 33, Data = 823c4604823b3a04823a2c0482391e0482381004823702048235f4048234e6048233d8048232ca048231bc048230b004822fa204822e9404822d8604822c7804
Write: Address = 34, Data = 824d2404824c1604824b08048249fa048248ec048247de048246d0048245c4048244b6048243a80482429a0482418c0482407e04823f7004823e6204823d5404
Write: Address = 35, Data = 825e0004825cf204825be404825ad8048259ca048258bc048257ae048256a0048255920482548404825376048252680482515a0482504e04824f4004824e3204
Write: Address = 36, Data = 826ede04826dd004826cc204826bb404826aa6048269980482688a0482677c0482666e048265620482645404826346048262380482612a0482601c04825f0e04
Write: Address = 37, Data = 827fba04827eac04827d9e04827c9004827b8204827a76048279680482785a0482774c0482763e04827530048274220482731404827206048270f804826fec04
Write: Address = 38, Data = 82909605828f8a05828e7c05828d6e05828c6005828b5205828a4405828936058288280582871a0582860c05828500058283f2058282e4058281d6058280c805
Write: Address = 39, Data = 82a1740582a06605829f5805829e4a05829d3c05829c2e05829b2005829a1405829906058297f8058296ea058295dc058294ce058293c0058292b2058291a405
Write: Address = 40, Data = 82b2500582b1420582b0340582af280582ae1a0582ad0c0582abfe0582aaf00582a9e20582a8d40582a7c60582a6b80582a5aa0582a49e0582a3900582a28205
Write: Address = 41, Data = 82c32e0582c2200582c1120582c0040582bef60582bde80582bcda0582bbcc0582babe0582b9b20582b8a40582b7960582b6880582b57a0582b46c0582b35e05
Write: Address = 42, Data = 82d40a0582d2fc0582d1ee0582d0e00582cfd20582cec60582cdb80582ccaa0582cb9c0582ca8e0582c9800582c8720582c7640582c6560582c5480582c43c05
Write: Address = 43, Data = 82e4e60582e3da0582e2cc0582e1be0582e0b00582dfa20582de940582dd860582dc780582db6a0582da5c0582d9500582d8420582d7340582d6260582d51805
Write: Address = 44, Data = 82f5c40582f4b60582f3a80582f29a0582f18c0582f07e0582ef700582ee640582ed560582ec480582eb3a0582ea2c0582e91e0582e8100582e7020582e5f405
Write: Address = 45, Data = 8306a00683059206830484068303780683026a0683015c0683004e0682ff400582fe320582fd240582fc160582fb080582f9fa0582f8ee0582f7e00582f6d205
Write: Address = 46, Data = 83177e06831670068315620683145406831346068312380683112a0683101c06830f0e06830e0206830cf406830be606830ad8068309ca068308bc068307ae06
Write: Address = 47, Data = 83285a0683274c0683263e06832530068324240683231606832208068320fa06831fec06831ede06831dd006831cc206831bb406831aa6068319980683188c06
Write: Address = 48, Data = 8339380683382a0683371c0683360e06833500068333f2068332e4068331d6068330c806832fba06832eae06832da006832c9206832b8406832a760683296806
Write: Address = 49, Data = 834a1406834906068347f8068346ea068345dc068344ce068343c2068342b4068341a60683409806833f8a06833e7c06833d6e06833c6006833b5206833a4406
Write: Address = 50, Data = 835af0068359e2068358d6068357c8068356ba068355ac0683549e0683539006835282068351740683506606834f5806834e4c06834d3e06834c3006834b2206
Write: Address = 51, Data = 836bce06836ac0068369b2068368a406836796068366880683657a0683646c0683636006836252068361440683603606835f2806835e1a06835d0c06835bfe06
Write: Address = 52, Data = 837caa06837b9c06837a8e068379800683787406837766068376580683754a0683743c0683732e06837220068371120683700406836ef606836dea06836cdc06
Write: Address = 53, Data = 838d8807838c7a07838b6c07838a5e07838950078388420783873407838626078385180783840a078382fe078381f0078380e207837fd406837ec606837db806
Write: Address = 54, Data = 839e6407839d5607839c4807839b3a07839a2c0783991e0783981207839704078395f6078394e8078393da078392cc078391be078390b007838fa207838e9407
Write: Address = 55, Data = 83af400783ae320783ad260783ac180783ab0a0783a9fc0783a8ee0783a7e00783a6d20783a5c40783a4b60783a3a80783a29c0783a18e0783a08007839f7207
Write: Address = 56, Data = 83c01e0783bf100783be020783bcf40783bbe60783bad80783b9ca0783b8bc0783b7b00783b6a20783b5940783b4860783b3780783b26a0783b15c0783b04e07
Write: Address = 57, Data = 83d0fa0783cfec0783cede0783cdd00783ccc40783cbb60783caa80783c99a0783c88c0783c77e0783c6700783c5620783c4540783c3460783c23a0783c12c07
Write: Address = 58, Data = 83e1d80783e0ca0783dfbc0783deae0783dda00783dc920783db840783da760783d9680783d85a0783d74e0783d6400783d5320783d4240783d3160783d20807
Write: Address = 59, Data = 83f2b40783f1a60783f0980783ef8a0783ee7c0783ed6e0783ec620783eb540783ea460783e9380783e82a0783e71c0783e60e0783e5000783e3f20783e2e407
Write: Address = 60, Data = 8403900884028208840176088400680883ff5a0783fe4c0783fd3e0783fc300783fb220783fa140783f9060783f7f80783f6ec0783f5de0783f4d00783f3c207
Write: Address = 61, Data = 84146e0884136008841252088411440884103608840f2808840e1a08840d0c08840c0008840af2088409e4088408d6088407c8088406ba088405ac0884049e08
Write: Address = 62, Data = 84254a0884243c0884232e08842220088421140884200608841ef808841dea08841cdc08841bce08841ac0088419b2088418a4088417960884168a0884157c08
Write: Address = 63, Data = 8436280884351a0884340c088432fe088431f0088430e208842fd408842ec608842db808842caa08842b9e08842a900884298208842874088427660884265808
Read: Address = 0
Read: Address = 1
Read: Address = 2
Read: Address = 3
Read: Address = 4
Read: Address = 5
Read: Address = 6
Read: Address = 7
Read: Address = 8
SUCCESSFUL: Address = 0, expected data = 800fd000800ec200800db400800ca600800b9800800a8c0080097e00800870008007620080065400800546008004380080032a0080021c0080010e0012153524, read data = 800fd000800ec200800db400800ca600800b9800800a8c0080097e00800870008007620080065400800546008004380080032a0080021c0080010e0012153524
Read: Address = 9
SUCCESSFUL: Address = 1, expected data = 8020ac00801fa000801e9200801d8400801c7600801b6800801a5a0080194c0080183e00801730008016220080151600801408008012fa008011ec008010de00, read data = 8020ac00801fa000801e9200801d8400801c7600801b6800801a5a0080194c0080183e00801730008016220080151600801408008012fa008011ec008010de00
Read: Address = 10
Read: Address = 11
SUCCESSFUL: Address = 2, expected data = 80318a0080307c00802f6e00802e6000802d5200802c4400802b3600802a2a0080291c0080280e00802700008025f2008024e4008023d6008022c8008021ba00, read data = 80318a0080307c00802f6e00802e6000802d5200802c4400802b3600802a2a0080291c0080280e00802700008025f2008024e4008023d6008022c8008021ba00
Read: Address = 12
SUCCESSFUL: Address = 3, expected data = 804266008041580080404a00803f3e00803e3000803d2200803c1400803b06008039f8008038ea008037dc008036ce008035c0008034b4008033a60080329800, read data = 804266008041580080404a00803f3e00803e3000803d2200803c1400803b06008039f8008038ea008037dc008036ce008035c0008034b4008033a60080329800
Read: Address = 13
SUCCESSFUL: Address = 4, expected data = 80534400805236008051280080501a00804f0c00804dfe00804cf000804be200804ad4008049c8008048ba008047ac0080469e00804590008044820080437400, read data = 80534400805236008051280080501a00804f0c00804dfe00804cf000804be200804ad4008049c8008048ba008047ac0080469e00804590008044820080437400
Read: Address = 14
SUCCESSFUL: Address = 5, expected data = 8064200080631200806204008060f600805fe800805edc00805dce00805cc000805bb200805aa400805996008058880080577a0080566c0080555e0080545200, read data = 8064200080631200806204008060f600805fe800805edc00805dce00805cc000805bb200805aa400805996008058880080577a0080566c0080555e0080545200
Read: Address = 15
SUCCESSFUL: Address = 6, expected data = 8074fc008073f0008072e2008071d4008070c600806fb800806eaa00806d9c00806c8e00806b8000806a7200806966008068580080674a0080663c0080652e00, read data = 8074fc008073f0008072e2008071d4008070c600806fb800806eaa00806d9c00806c8e00806b8000806a7200806966008068580080674a0080663c0080652e00
Read: Address = 16
SUCCESSFUL: Address = 7, expected data = 8085da018084cc018083be018082b0018081a20180809401807f8600807e7a00807d6c00807c5e00807b5000807a420080793400807826008077180080760a00, read data = 8085da018084cc018083be018082b0018081a20180809401807f8600807e7a00807d6c00807c5e00807b5000807a420080793400807826008077180080760a00
Read: Address = 17
SUCCESSFUL: Address = 8, expected data = 8096b6018095a80180949a0180938e01809280018091720180906401808f5601808e4801808d3a01808c2c01808b1e01808a1001808904018087f6018086e801, read data = 8096b6018095a80180949a0180938e01809280018091720180906401808f5601808e4801808d3a01808c2c01808b1e01808a1001808904018087f6018086e801
Read: Address = 18
SUCCESSFUL: Address = 9, expected data = 80a7940180a6860180a5780180a46a0180a35c0180a24e0180a1400180a03201809f2401809e1801809d0a01809bfc01809aee018099e0018098d2018097c401, read data = 80a7940180a6860180a5780180a46a0180a35c0180a24e0180a1400180a03201809f2401809e1801809d0a01809bfc01809aee018099e0018098d2018097c401
Read: Address = 19
SUCCESSFUL: Address = 10, expected data = 80b8700180b7620180b6540180b5460180b4380180b32c0180b21e0180b1100180b0020180aef40180ade60180acd80180abca0180aabc0180a9ae0180a8a201, read data = 80b8700180b7620180b6540180b5460180b4380180b32c0180b21e0180b1100180b0020180aef40180ade60180acd80180abca0180aabc0180a9ae0180a8a201
Read: Address = 20
SUCCESSFUL: Address = 11, expected data = 80c94c0180c8400180c7320180c6240180c5160180c4080180c2fa0180c1ec0180c0de0180bfd00180bec20180bdb60180bca80180bb9a0180ba8c0180b97e01, read data = 80c94c0180c8400180c7320180c6240180c5160180c4080180c2fa0180c1ec0180c0de0180bfd00180bec20180bdb60180bca80180bb9a0180ba8c0180b97e01
Read: Address = 21
SUCCESSFUL: Address = 12, expected data = 80da2a0180d91c0180d80e0180d7000180d5f20180d4e40180d3d60180d2ca0180d1bc0180d0ae0180cfa00180ce920180cd840180cc760180cb680180ca5a01, read data = 80da2a0180d91c0180d80e0180d7000180d5f20180d4e40180d3d60180d2ca0180d1bc0180d0ae0180cfa00180ce920180cd840180cc760180cb680180ca5a01
Read: Address = 22
SUCCESSFUL: Address = 13, expected data = 80eb060180e9f80180e8ea0180e7de0180e6d00180e5c20180e4b40180e3a60180e2980180e18a0180e07c0180df6e0180de600180dd540180dc460180db3801, read data = 80eb060180e9f80180e8ea0180e7de0180e6d00180e5c20180e4b40180e3a60180e2980180e18a0180e07c0180df6e0180de600180dd540180dc460180db3801
Read: Address = 23
SUCCESSFUL: Address = 14, expected data = 80fbe40180fad60180f9c80180f8ba0180f7ac0180f69e0180f5900180f4820180f3740180f2680180f15a0180f04c0180ef3e0180ee300180ed220180ec1401, read data = 80fbe40180fad60180f9c80180f8ba0180f7ac0180f69e0180f5900180f4820180f3740180f2680180f15a0180f04c0180ef3e0180ee300180ed220180ec1401
Read: Address = 24
SUCCESSFUL: Address = 15, expected data = 810cc002810bb202810aa4028109960281088a0281077c0281066e02810560028104520281034402810236028101280281001a0280ff0c0180fdfe0180fcf201, read data = 810cc002810bb202810aa4028109960281088a0281077c0281066e02810560028104520281034402810236028101280281001a0280ff0c0180fdfe0180fcf201
Read: Address = 25
SUCCESSFUL: Address = 16, expected data = 811d9e02811c9002811b8202811a7402811966028118580281174a0281163c0281152e028114200281131402811206028110f802810fea02810edc02810dce02, read data = 811d9e02811c9002811b8202811a7402811966028118580281174a0281163c0281152e028114200281131402811206028110f802810fea02810edc02810dce02
Read: Address = 26
SUCCESSFUL: Address = 17, expected data = 812e7a02812d6c02812c5e02812b5002812a4202812934028128280281271a0281260c028124fe028123f0028122e2028121d4028120c602811fb802811eaa02, read data = 812e7a02812d6c02812c5e02812b5002812a4202812934028128280281271a0281260c028124fe028123f0028122e2028121d4028120c602811fb802811eaa02
Read: Address = 27
SUCCESSFUL: Address = 18, expected data = 813f5602813e4802813d3c02813c2e02813b2002813a1202813904028137f6028136e8028135da028134cc028133be028132b2028131a40281309602812f8802, read data = 813f5602813e4802813d3c02813c2e02813b2002813a1202813904028137f6028136e8028135da028134cc028133be028132b2028131a40281309602812f8802
Read: Address = 28
SUCCESSFUL: Address = 19, expected data = 81503402814f2602814e1802814d0a02814bfc02814aee028149e0028148d2028147c6028146b8028145aa0281449c0281438e02814280028141720281406402, read data = 81503402814f2602814e1802814d0a02814bfc02814aee028149e0028148d2028147c6028146b8028145aa0281449c0281438e02814280028141720281406402
Read: Address = 29
SUCCESSFUL: Address = 20, expected data = 8161100281600202815ef402815de602815cda02815bcc02815abe028159b0028158a20281579402815686028155780281546a0281535c028152500281514202, read data = 8161100281600202815ef402815de602815cda02815bcc02815abe028159b0028158a20281579402815686028155780281546a0281535c028152500281514202
Read: Address = 30
SUCCESSFUL: Address = 21, expected data = 8171ee028170e002816fd202816ec402816db602816ca802816b9a02816a8c0281697e028168700281676402816656028165480281643a0281632c0281621e02, read data = 8171ee028170e002816fd202816ec402816db602816ca802816b9a02816a8c0281697e028168700281676402816656028165480281643a0281632c0281621e02
Read: Address = 31
SUCCESSFUL: Address = 22, expected data = 8182ca038181bc038180ae03817fa002817e9202817d8402817c7802817b6a02817a5c0281794e0281784002817732028176240281751602817408028172fa02, read data = 8182ca038181bc038180ae03817fa002817e9202817d8402817c7802817b6a02817a5c0281794e0281784002817732028176240281751602817408028172fa02
Read: Address = 32
SUCCESSFUL: Address = 23, expected data = 8193a6038192980381918c0381907e03818f7003818e6203818d5403818c4603818b3803818a2a0381891c0381880e03818702038185f4038184e6038183d803, read data = 8193a6038192980381918c0381907e03818f7003818e6203818d5403818c4603818b3803818a2a0381891c0381880e03818702038185f4038184e6038183d803
Read: Address = 33
SUCCESSFUL: Address = 24, expected data = 81a4840381a3760381a2680381a15a0381a04c03819f3e03819e3003819d2203819c1603819b08038199fa038198ec038197de038196d0038195c2038194b403, read data = 81a4840381a3760381a2680381a15a0381a04c03819f3e03819e3003819d2203819c1603819b08038199fa038198ec038197de038196d0038195c2038194b403
Read: Address = 34
SUCCESSFUL: Address = 25, expected data = 81b5600381b4520381b3440381b2360381b12a0381b01c0381af0e0381ae000381acf20381abe40381aad60381a9c80381a8ba0381a7ac0381a6a00381a59203, read data = 81b5600381b4520381b3440381b2360381b12a0381b01c0381af0e0381ae000381acf20381abe40381aad60381a9c80381a8ba0381a7ac0381a6a00381a59203
Read: Address = 35
SUCCESSFUL: Address = 26, expected data = 81c63e0381c5300381c4220381c3140381c2060381c0f80381bfea0381bedc0381bdce0381bcc00381bbb40381baa60381b9980381b88a0381b77c0381b66e03, read data = 81c63e0381c5300381c4220381c3140381c2060381c0f80381bfea0381bedc0381bdce0381bcc00381bbb40381baa60381b9980381b88a0381b77c0381b66e03
Read: Address = 36
SUCCESSFUL: Address = 27, expected data = 81d71a0381d60c0381d4fe0381d3f00381d2e20381d1d40381d0c80381cfba0381ceac0381cd9e0381cc900381cb820381ca740381c9660381c8580381c74a03, read data = 81d71a0381d60c0381d4fe0381d3f00381d2e20381d1d40381d0c80381cfba0381ceac0381cd9e0381cc900381cb820381ca740381c9660381c8580381c74a03
Read: Address = 37
SUCCESSFUL: Address = 28, expected data = 81e7f60381e6e80381e5dc0381e4ce0381e3c00381e2b20381e1a40381e0960381df880381de7a0381dd6c0381dc5e0381db520381da440381d9360381d82803, read data = 81e7f60381e6e80381e5dc0381e4ce0381e3c00381e2b20381e1a40381e0960381df880381de7a0381dd6c0381dc5e0381db520381da440381d9360381d82803
Read: Address = 38
SUCCESSFUL: Address = 29, expected data = 81f8d40381f7c60381f6b80381f5aa0381f49c0381f38e0381f2800381f1720381f0660381ef580381ee4a0381ed3c0381ec2e0381eb200381ea120381e90403, read data = 81f8d40381f7c60381f6b80381f5aa0381f49c0381f38e0381f2800381f1720381f0660381ef580381ee4a0381ed3c0381ec2e0381eb200381ea120381e90403
Read: Address = 39
SUCCESSFUL: Address = 30, expected data = 8209b0048208a204820794048206860482057a0482046c0482035e0482025004820142048200340481ff260381fe180381fd0a0381fbfc0381faf00381f9e203, read data = 8209b0048208a204820794048206860482057a0482046c0482035e0482025004820142048200340481ff260381fe180381fd0a0381fbfc0381faf00381f9e203
Read: Address = 40
SUCCESSFUL: Address = 31, expected data = 821a8e04821980048218720482176404821656048215480482143a0482132c0482121e048211100482100404820ef604820de804820cda04820bcc04820abe04, read data = 821a8e04821980048218720482176404821656048215480482143a0482132c0482121e048211100482100404820ef604820de804820cda04820bcc04820abe04
Read: Address = 41
SUCCESSFUL: Address = 32, expected data = 822b6a04822a5c0482294e048228400482273204822626048225180482240a048222fc048221ee048220e004821fd204821ec404821db604821ca804821b9c04, read data = 822b6a04822a5c0482294e048228400482273204822626048225180482240a048222fc048221ee048220e004821fd204821ec404821db604821ca804821b9c04
Read: Address = 42
SUCCESSFUL: Address = 33, expected data = 823c4604823b3a04823a2c0482391e0482381004823702048235f4048234e6048233d8048232ca048231bc048230b004822fa204822e9404822d8604822c7804, read data = 823c4604823b3a04823a2c0482391e0482381004823702048235f4048234e6048233d8048232ca048231bc048230b004822fa204822e9404822d8604822c7804
Read: Address = 43
SUCCESSFUL: Address = 34, expected data = 824d2404824c1604824b08048249fa048248ec048247de048246d0048245c4048244b6048243a80482429a0482418c0482407e04823f7004823e6204823d5404, read data = 824d2404824c1604824b08048249fa048248ec048247de048246d0048245c4048244b6048243a80482429a0482418c0482407e04823f7004823e6204823d5404
Read: Address = 44
SUCCESSFUL: Address = 35, expected data = 825e0004825cf204825be404825ad8048259ca048258bc048257ae048256a0048255920482548404825376048252680482515a0482504e04824f4004824e3204, read data = 825e0004825cf204825be404825ad8048259ca048258bc048257ae048256a0048255920482548404825376048252680482515a0482504e04824f4004824e3204
Read: Address = 45
SUCCESSFUL: Address = 36, expected data = 826ede04826dd004826cc204826bb404826aa6048269980482688a0482677c0482666e048265620482645404826346048262380482612a0482601c04825f0e04, read data = 826ede04826dd004826cc204826bb404826aa6048269980482688a0482677c0482666e048265620482645404826346048262380482612a0482601c04825f0e04
Read: Address = 46
SUCCESSFUL: Address = 37, expected data = 827fba04827eac04827d9e04827c9004827b8204827a76048279680482785a0482774c0482763e04827530048274220482731404827206048270f804826fec04, read data = 827fba04827eac04827d9e04827c9004827b8204827a76048279680482785a0482774c0482763e04827530048274220482731404827206048270f804826fec04
Read: Address = 47
SUCCESSFUL: Address = 38, expected data = 82909605828f8a05828e7c05828d6e05828c6005828b5205828a4405828936058288280582871a0582860c05828500058283f2058282e4058281d6058280c805, read data = 82909605828f8a05828e7c05828d6e05828c6005828b5205828a4405828936058288280582871a0582860c05828500058283f2058282e4058281d6058280c805
Read: Address = 48
SUCCESSFUL: Address = 39, expected data = 82a1740582a06605829f5805829e4a05829d3c05829c2e05829b2005829a1405829906058297f8058296ea058295dc058294ce058293c0058292b2058291a405, read data = 82a1740582a06605829f5805829e4a05829d3c05829c2e05829b2005829a1405829906058297f8058296ea058295dc058294ce058293c0058292b2058291a405
Read: Address = 49
SUCCESSFUL: Address = 40, expected data = 82b2500582b1420582b0340582af280582ae1a0582ad0c0582abfe0582aaf00582a9e20582a8d40582a7c60582a6b80582a5aa0582a49e0582a3900582a28205, read data = 82b2500582b1420582b0340582af280582ae1a0582ad0c0582abfe0582aaf00582a9e20582a8d40582a7c60582a6b80582a5aa0582a49e0582a3900582a28205
Read: Address = 50
SUCCESSFUL: Address = 41, expected data = 82c32e0582c2200582c1120582c0040582bef60582bde80582bcda0582bbcc0582babe0582b9b20582b8a40582b7960582b6880582b57a0582b46c0582b35e05, read data = 82c32e0582c2200582c1120582c0040582bef60582bde80582bcda0582bbcc0582babe0582b9b20582b8a40582b7960582b6880582b57a0582b46c0582b35e05
Read: Address = 51
SUCCESSFUL: Address = 42, expected data = 82d40a0582d2fc0582d1ee0582d0e00582cfd20582cec60582cdb80582ccaa0582cb9c0582ca8e0582c9800582c8720582c7640582c6560582c5480582c43c05, read data = 82d40a0582d2fc0582d1ee0582d0e00582cfd20582cec60582cdb80582ccaa0582cb9c0582ca8e0582c9800582c8720582c7640582c6560582c5480582c43c05
Read: Address = 52
SUCCESSFUL: Address = 43, expected data = 82e4e60582e3da0582e2cc0582e1be0582e0b00582dfa20582de940582dd860582dc780582db6a0582da5c0582d9500582d8420582d7340582d6260582d51805, read data = 82e4e60582e3da0582e2cc0582e1be0582e0b00582dfa20582de940582dd860582dc780582db6a0582da5c0582d9500582d8420582d7340582d6260582d51805
Read: Address = 53
SUCCESSFUL: Address = 44, expected data = 82f5c40582f4b60582f3a80582f29a0582f18c0582f07e0582ef700582ee640582ed560582ec480582eb3a0582ea2c0582e91e0582e8100582e7020582e5f405, read data = 82f5c40582f4b60582f3a80582f29a0582f18c0582f07e0582ef700582ee640582ed560582ec480582eb3a0582ea2c0582e91e0582e8100582e7020582e5f405
Read: Address = 54
SUCCESSFUL: Address = 45, expected data = 8306a00683059206830484068303780683026a0683015c0683004e0682ff400582fe320582fd240582fc160582fb080582f9fa0582f8ee0582f7e00582f6d205, read data = 8306a00683059206830484068303780683026a0683015c0683004e0682ff400582fe320582fd240582fc160582fb080582f9fa0582f8ee0582f7e00582f6d205
Read: Address = 55
SUCCESSFUL: Address = 46, expected data = 83177e06831670068315620683145406831346068312380683112a0683101c06830f0e06830e0206830cf406830be606830ad8068309ca068308bc068307ae06, read data = 83177e06831670068315620683145406831346068312380683112a0683101c06830f0e06830e0206830cf406830be606830ad8068309ca068308bc068307ae06
Read: Address = 56
SUCCESSFUL: Address = 47, expected data = 83285a0683274c0683263e06832530068324240683231606832208068320fa06831fec06831ede06831dd006831cc206831bb406831aa6068319980683188c06, read data = 83285a0683274c0683263e06832530068324240683231606832208068320fa06831fec06831ede06831dd006831cc206831bb406831aa6068319980683188c06
Read: Address = 57
SUCCESSFUL: Address = 48, expected data = 8339380683382a0683371c0683360e06833500068333f2068332e4068331d6068330c806832fba06832eae06832da006832c9206832b8406832a760683296806, read data = 8339380683382a0683371c0683360e06833500068333f2068332e4068331d6068330c806832fba06832eae06832da006832c9206832b8406832a760683296806
Read: Address = 58
SUCCESSFUL: Address = 49, expected data = 834a1406834906068347f8068346ea068345dc068344ce068343c2068342b4068341a60683409806833f8a06833e7c06833d6e06833c6006833b5206833a4406, read data = 834a1406834906068347f8068346ea068345dc068344ce068343c2068342b4068341a60683409806833f8a06833e7c06833d6e06833c6006833b5206833a4406
Read: Address = 59
SUCCESSFUL: Address = 50, expected data = 835af0068359e2068358d6068357c8068356ba068355ac0683549e0683539006835282068351740683506606834f5806834e4c06834d3e06834c3006834b2206, read data = 835af0068359e2068358d6068357c8068356ba068355ac0683549e0683539006835282068351740683506606834f5806834e4c06834d3e06834c3006834b2206
Read: Address = 60
SUCCESSFUL: Address = 51, expected data = 836bce06836ac0068369b2068368a406836796068366880683657a0683646c0683636006836252068361440683603606835f2806835e1a06835d0c06835bfe06, read data = 836bce06836ac0068369b2068368a406836796068366880683657a0683646c0683636006836252068361440683603606835f2806835e1a06835d0c06835bfe06
Read: Address = 61
SUCCESSFUL: Address = 52, expected data = 837caa06837b9c06837a8e068379800683787406837766068376580683754a0683743c0683732e06837220068371120683700406836ef606836dea06836cdc06, read data = 837caa06837b9c06837a8e068379800683787406837766068376580683754a0683743c0683732e06837220068371120683700406836ef606836dea06836cdc06
Read: Address = 62
SUCCESSFUL: Address = 53, expected data = 838d8807838c7a07838b6c07838a5e07838950078388420783873407838626078385180783840a078382fe078381f0078380e207837fd406837ec606837db806, read data = 838d8807838c7a07838b6c07838a5e07838950078388420783873407838626078385180783840a078382fe078381f0078380e207837fd406837ec606837db806
Read: Address = 63
SUCCESSFUL: Address = 54, expected data = 839e6407839d5607839c4807839b3a07839a2c0783991e0783981207839704078395f6078394e8078393da078392cc078391be078390b007838fa207838e9407, read data = 839e6407839d5607839c4807839b3a07839a2c0783991e0783981207839704078395f6078394e8078393da078392cc078391be078390b007838fa207838e9407
SUCCESSFUL: Address = 55, expected data = 83af400783ae320783ad260783ac180783ab0a0783a9fc0783a8ee0783a7e00783a6d20783a5c40783a4b60783a3a80783a29c0783a18e0783a08007839f7207, read data = 83af400783ae320783ad260783ac180783ab0a0783a9fc0783a8ee0783a7e00783a6d20783a5c40783a4b60783a3a80783a29c0783a18e0783a08007839f7207
SUCCESSFUL: Address = 56, expected data = 83c01e0783bf100783be020783bcf40783bbe60783bad80783b9ca0783b8bc0783b7b00783b6a20783b5940783b4860783b3780783b26a0783b15c0783b04e07, read data = 83c01e0783bf100783be020783bcf40783bbe60783bad80783b9ca0783b8bc0783b7b00783b6a20783b5940783b4860783b3780783b26a0783b15c0783b04e07
SUCCESSFUL: Address = 57, expected data = 83d0fa0783cfec0783cede0783cdd00783ccc40783cbb60783caa80783c99a0783c88c0783c77e0783c6700783c5620783c4540783c3460783c23a0783c12c07, read data = 83d0fa0783cfec0783cede0783cdd00783ccc40783cbb60783caa80783c99a0783c88c0783c77e0783c6700783c5620783c4540783c3460783c23a0783c12c07
SUCCESSFUL: Address = 58, expected data = 83e1d80783e0ca0783dfbc0783deae0783dda00783dc920783db840783da760783d9680783d85a0783d74e0783d6400783d5320783d4240783d3160783d20807, read data = 83e1d80783e0ca0783dfbc0783deae0783dda00783dc920783db840783da760783d9680783d85a0783d74e0783d6400783d5320783d4240783d3160783d20807
SUCCESSFUL: Address = 59, expected data = 83f2b40783f1a60783f0980783ef8a0783ee7c0783ed6e0783ec620783eb540783ea460783e9380783e82a0783e71c0783e60e0783e5000783e3f20783e2e407, read data = 83f2b40783f1a60783f0980783ef8a0783ee7c0783ed6e0783ec620783eb540783ea460783e9380783e82a0783e71c0783e60e0783e5000783e3f20783e2e407
SUCCESSFUL: Address = 60, expected data = 8403900884028208840176088400680883ff5a0783fe4c0783fd3e0783fc300783fb220783fa140783f9060783f7f80783f6ec0783f5de0783f4d00783f3c207, read data = 8403900884028208840176088400680883ff5a0783fe4c0783fd3e0783fc300783fb220783fa140783f9060783f7f80783f6ec0783f5de0783f4d00783f3c207
SUCCESSFUL: Address = 61, expected data = 84146e0884136008841252088411440884103608840f2808840e1a08840d0c08840c0008840af2088409e4088408d6088407c8088406ba088405ac0884049e08, read data = 84146e0884136008841252088411440884103608840f2808840e1a08840d0c08840c0008840af2088409e4088408d6088407c8088406ba088405ac0884049e08
SUCCESSFUL: Address = 62, expected data = 84254a0884243c0884232e08842220088421140884200608841ef808841dea08841cdc08841bce08841ac0088419b2088418a4088417960884168a0884157c08, read data = 84254a0884243c0884232e08842220088421140884200608841ef808841dea08841cdc08841bce08841ac0088419b2088418a4088417960884168a0884157c08
SUCCESSFUL: Address = 63, expected data = 8436280884351a0884340c088432fe088431f0088430e208842fd408842ec608842db808842caa08842b9e08842a900884298208842874088427660884265808, read data = 8436280884351a0884340c088432fe088431f0088430e208842fd408842ec608842db808842caa08842b9e08842a900884298208842874088427660884265808


------- SUMMARY -------
Number of Writes = 64
Number of Reads = 64
Number of Success = 64
Number of Fails = 0

$stop called at time : 68955 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/DDR3 SDRAM Verilog Model/ddr3_dimm_micron_sim.v" Line 269