AngeloJacobo 83b7b95af4 pass verilator warning		2023-08-20 12:32:51 +08:00
..
ddr3_controller.v	pass formal for 8-lane config and pass verilator linting	2023-08-20 11:07:22 +08:00
ddr3_phy.v	reset for IO is released only after IDELAYCTRL is ready, added also IODELAY_GROUP	2023-08-20 11:09:38 +08:00
ddr3_top.v	pass verilator warning	2023-08-20 12:32:51 +08:00
fwb_slave.v	make stall and accessible outside, removed added assumptions with i_slave_busy	2023-07-13 18:48:34 +08:00